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Commit Graph

80587 Commits

Author SHA1 Message Date
Chandler Carruth
3b6ab8a33e Provide the 32-bit variant of the golden tests. Not sure how I forgot to
do this initially, sorry.

llvm-svn: 151857
2012-03-01 23:06:19 +00:00
Jakob Stoklund Olesen
b87ff8f772 Handle regmasks in Thumb1RegisterInfo::saveScavengerRegister().
This function could have r12 live across a function call when compiling
thumb1 code.

The test case for this is not included because it is very long. It must
provoke emergency spilling near a function call. The behavior is
provoked by MultiSource/Applications/JM/lencod, and it triggers an
assertion in the scavenger.

<rdar://problem/10963642>

llvm-svn: 151855
2012-03-01 22:57:32 +00:00
Eric Christopher
3d271eb540 Reorder the sections being output to reduce the number of assembler
fixups that are being used to determine section offsets. Reduces
the total number of fixups by 50% for a non-trivial testcase.

Part of rdar://10413936

llvm-svn: 151852
2012-03-01 22:50:31 +00:00
Jim Grosbach
cd931af452 ARM use the right opcode for FP<->Integer move in fast-isel.
rdar://10965031

llvm-svn: 151850
2012-03-01 22:47:09 +00:00
Michael J. Spencer
0eb4a851f6 Minimal changes for LLVM to compile under VS11.
llvm-svn: 151849
2012-03-01 22:42:52 +00:00
Akira Hatanaka
6336ac5257 Changes for migrating to using register mask operands.
llvm-svn: 151847
2012-03-01 22:27:29 +00:00
David Meyer
7f21ecb667 [Object]
Add ObjectFile::getLoadName() for retrieving the soname/installname of a shared object.

llvm-svn: 151845
2012-03-01 22:19:54 +00:00
Kevin Enderby
26dad6994b Change ARMInstPrinter::printPredicateOperand() so it will not abort if it
runs into the undefined 15 condition code value.

llvm-svn: 151844
2012-03-01 22:13:02 +00:00
Akira Hatanaka
75b06f4a49 Fix bugs which were introduced when support for base+index floating point loads
and stores was added.

- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
  floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.

llvm-svn: 151843
2012-03-01 22:12:30 +00:00
Benjamin Kramer
88e1073516 BumpPtrAllocator: Make sure threshold cannot be initialized with a value smaller than the slab size.
This replaces r151834 with a simpler fix.

llvm-svn: 151842
2012-03-01 22:10:16 +00:00
Chandler Carruth
5bca3bef43 Fix two warnings in this code that I missed.
llvm-svn: 151839
2012-03-01 21:45:51 +00:00
Argyrios Kyrtzidis
cdf7b1a45c If BumpPtrAllocator is requested to allocate a size that exceeds the slab size,
increase the slab size.

llvm-svn: 151834
2012-03-01 20:36:32 +00:00
Preston Gurd
29cb4871db Trivial change to make the test use Use –mcpu=generic,
so that the test will not fail when run on an Intel Atom
processor, due to the Atom scheduler producing an instruction sequence that is
different from that which is normally expected.

llvm-svn: 151832
2012-03-01 19:57:20 +00:00
Argyrios Kyrtzidis
791437e5f8 Move include/llvm/ADT/SaveAndRestore.h -> include/llvm/Support/SaveAndRestore.h
llvm-svn: 151828
2012-03-01 19:45:47 +00:00
Chandler Carruth
f5c22e9409 Add the source file with trivial definitions in it that was missing from
r151822, sorry sorry. =[

We need 'git svn nothave' or some such...

llvm-svn: 151824
2012-03-01 18:58:59 +00:00
Chandler Carruth
cc9b4516cb Rewrite LLVM's generalized support library for hashing to follow the API
of the proposed standard hashing interfaces (N3333), and to use
a modified and tuned version of the CityHash algorithm.

Some of the highlights of this change:
 -- Significantly higher quality hashing algorithm with very well
    distributed results, and extremely few collisions. Should be close to
    a checksum for up to 64-bit keys. Very little clustering or clumping of
    hash codes, to better distribute load on probed hash tables.
 -- Built-in support for reserved values.
 -- Simplified API that composes cleanly with other C++ idioms and APIs.
 -- Better scaling performance as keys grow. This is the fastest
    algorithm I've found and measured for moderately sized keys (such as
    show up in some of the uniquing and folding use cases)
 -- Support for enabling per-execution seeds to prevent table ordering
    or other artifacts of hashing algorithms to impact the output of
    LLVM. The seeding would make each run different and highlight these
    problems during bootstrap.

This implementation was tested extensively using the SMHasher test
suite, and pased with flying colors, doing better than the original
CityHash algorithm even.

I've included a unittest, although it is somewhat minimal at the moment.
I've also added (or refactored into the proper location) type traits
necessary to implement this, and converted users of GeneralHash over.

My only immediate concerns with this implementation is the performance
of hashing small keys. I've already started working to improve this, and
will continue to do so. Currently, the only algorithms faster produce
lower quality results, but it is likely there is a better compromise
than the current one.

Many thanks to Jeffrey Yasskin who did most of the work on the N3333
paper, pair-programmed some of this code, and reviewed much of it. Many
thanks also go to Geoff Pike Pike and Jyrki Alakuijala, the original
authors of CityHash on which this is heavily based, and Austin Appleby
who created MurmurHash and the SMHasher test suite.

Also thanks to Nadav, Tobias, Howard, Jay, Nick, Ahmed, and Duncan for
all of the review comments! If there are further comments or concerns,
please let me know and I'll jump on 'em.

llvm-svn: 151822
2012-03-01 18:55:25 +00:00
Benjamin Kramer
111608aae1 Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.
llvm-svn: 151821
2012-03-01 18:16:35 +00:00
Chad Rosier
3bdd700004 Revert r151816 as Jim has the appropriate fix.
llvm-svn: 151818
2012-03-01 17:41:19 +00:00
Chad Rosier
89b9ecae75 Fix testcases from r151807.
llvm-svn: 151816
2012-03-01 17:31:30 +00:00
Jim Grosbach
9b3f9f1d37 Move TargetRegisterInfo::getSubReg() to MCRegisterInfo.
Allows us to de-virtualize the function and provides access to it in
the instruction printer, which is useful for handling composite
physical registers (e.g., ARM register lists).

llvm-svn: 151815
2012-03-01 17:30:39 +00:00
Jim Grosbach
36aec6e397 Revert "Emit the SubRegTable with the smallest possible integer type."
This reverts commit 151760.

We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo,
but to do that, the type of the lookup table needs to be the same for
all targets.

llvm-svn: 151814
2012-03-01 17:30:35 +00:00
Jim Grosbach
e41072bbb4 Add missing triple for tests.
Make darwin bots happier.

llvm-svn: 151813
2012-03-01 17:30:32 +00:00
Jia Liu
d95fe4d1fa rplace Alpha with ARM in docs/WritingAnLLVMBackend.html, patch by chenwj
llvm-svn: 151811
2012-03-01 15:14:19 +00:00
James Molloy
1038b57cac Fix a codegen fault in which log2 or exp2 could be dead-code eliminated even though they could have sideeffects.
Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone".

llvm-svn: 151807
2012-03-01 14:32:18 +00:00
Benjamin Kramer
44c3c88cb7 Make TargetRegisterClasses non-virtual by making the only virtual function a function pointer.
This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static
initializer and a ton of cruft from the generated code.

Shrinks ARMBaseRegisterInfo.o by ~100k.

llvm-svn: 151806
2012-03-01 13:37:55 +00:00
NAKAMURA Takumi
9d35e6f60f llvm/test/CMakeLists.txt: Update dependencies to add llvm-readobj to "check".
llvm-svn: 151795
2012-03-01 03:14:13 +00:00
Benjamin Kramer
c57a6d4a2a Emit the "is an intrinsic overloaded" table as a bitfield.
llvm-svn: 151792
2012-03-01 02:16:57 +00:00
Akira Hatanaka
7964a20cf6 Pass endian information to constructors. Define separate functions to create
objects for big endian and little endian targets.

Patch by Jack Carter.

llvm-svn: 151788
2012-03-01 01:53:15 +00:00
Jakob Stoklund Olesen
2055fc1331 Make InlineSpiller bundle-aware.
Simply treat bundles as instructions. Spill code is inserted between
bundles, never inside a bundle.  Rewrite all operands in a bundle at
once.

Don't attempt and memory operand folding inside bundles.

llvm-svn: 151787
2012-03-01 01:43:25 +00:00
David Meyer
44201a2d17 [Object]
* Add begin_dynamic_table() / end_dynamic_table() private interface to ELFObjectFile.
* Add begin_libraries_needed() / end_libraries_needed() interface to ObjectFile, for grabbing the list of needed libraries for a shared object or dynamic executable.
* Implement this new interface completely for ELF, leave stubs for COFF and MachO.
* Add 'llvm-readobj' tool for dumping ObjectFile information.

llvm-svn: 151785
2012-03-01 01:36:50 +00:00
Jakob Stoklund Olesen
1885bf0ac7 Move getBundleStart() into MachineInstrBundle.h.
This allows the function to be inlined, and makes it suitable for use in
getInstructionIndex().

Also provide a const version. C++ is great for touch typing practice.

llvm-svn: 151782
2012-03-01 01:26:01 +00:00
Benjamin Kramer
14d729cf6a Emit the intrinsic modref info as a lookup table instead of a huge switch.
Shrinks BasicAliasAnalysis.o from 106k to 56k on i386.

llvm-svn: 151781
2012-03-01 01:18:32 +00:00
Lang Hames
6cd018d0bc Don't redundantly copy implicit operands when rematerializing.
While we're at it - don't copy vreg implicit operands while rematerializing.
This fixes PR12138.

llvm-svn: 151779
2012-03-01 00:41:17 +00:00
Richard Trieu
4eaabe29a7 Fix flags for test in MC/MachO/ARM/empty-function-nop.ll
llvm-svn: 151778
2012-03-01 00:29:09 +00:00
Sean Callanan
171b2ddfbd Fixed the 32-bit runtime dynamic loader to allocate
code sections when needed.  It just had a conditional
the wrong way around.

llvm-svn: 151777
2012-03-01 00:15:29 +00:00
Benjamin Kramer
16bdd01e87 Implement getSubRegIndex as a linear search on the SubRegTable instead of using a big switch.
- The search bounds are constant, in the worst case (ARM target) it will scan over 30 uint16_ts.
- This method isn't very hot, I had problems finding a testcase where it's called more than a dozen of times (no perf impact).

llvm-svn: 151773
2012-02-29 23:46:50 +00:00
Kevin Enderby
46c639cf8a Added annotations for x86 pc relative loads to llvm's 'C' disassembler.
So with darwin's otool(1) an x86_64 hello world .o file will print:
leaq	L_.str(%rip), %rax ## literal pool for: Hello world

llvm-svn: 151769
2012-02-29 22:58:34 +00:00
Jim Grosbach
2c1ad70f1e Tidy up. 80 columns.
llvm-svn: 151764
2012-02-29 22:07:56 +00:00
Benjamin Kramer
e4ab085322 Emit the SubRegTable with the smallest possible integer type.
Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets.

llvm-svn: 151760
2012-02-29 21:57:08 +00:00
Jim Grosbach
ccc97aa21e Tidy up. Spelling.
llvm-svn: 151758
2012-02-29 21:46:32 +00:00
Jim Grosbach
f0509324e0 Move the subregister indicies enum into the REGINFO_ENUM section.
llvm-svn: 151756
2012-02-29 21:43:16 +00:00
Daniel Dunbar
0f3c632848 BitstreamWriter: Use SmallVector::append instead of multiple push_back calls.
llvm-svn: 151755
2012-02-29 21:02:05 +00:00
Jim Grosbach
1105208aec Switch TargetRegisterInfo::getSubReg() to use a lookup table.
Instead of nested switch statements, use a lookup table. On ARM, this replaces
a 23k (x86_64 release build) function with a 16k table. Its not unlikely to
be faster, as well.

llvm-svn: 151751
2012-02-29 20:31:17 +00:00
Daniel Dunbar
ce00dc437f BitstreamWriter: Change primary output buffer to be a SmallVector instead of an
std::vector.
 - Good for 1-2% speedup on writing PCH for Cocoa.h.
 - Clang side API match to follow shortly, there wasn't an easy way to make this
   non-breaking.

llvm-svn: 151750
2012-02-29 20:31:09 +00:00
Daniel Dunbar
4b6c24ce7c BitstreamWriter: Isolate access to the underlying buffer.
llvm-svn: 151749
2012-02-29 20:31:05 +00:00
Daniel Dunbar
769ebcfda1 BitcodeWriter: Expose less implementation details -- make BackpatchWord private
and remove getBuffer().

llvm-svn: 151748
2012-02-29 20:31:01 +00:00
Daniel Dunbar
b887c34acf Bitcode: Don't expose WriteBitcodeToStream to clients.
llvm-svn: 151747
2012-02-29 20:30:56 +00:00
Andrew Trick
cf63a3d03a Intel Atom instruction itineraries for mov sign extension and mov zero extension.
Patch by Tyler Nowicki!

llvm-svn: 151743
2012-02-29 19:44:41 +00:00
Hal Finkel
51e5e05946 Add myself to the credits file
llvm-svn: 151732
2012-02-29 16:43:11 +00:00
Benjamin Kramer
1b5aa9f5cd LegalizeIntegerTypes: Reorder operations in the "big shift by small amount" optimization, making the lives of later passes easier.
llvm-svn: 151722
2012-02-29 13:27:00 +00:00