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20053 Commits

Author SHA1 Message Date
Jim Grosbach
3e9384b103 ARM NEON two-operand aliases for VSHL(register). 
llvm-svn: 146123
 2011-12-08 01:12:35 +00:00
Jakob Stoklund Olesen
533f7a0f7a Simplify offset verification. 
llvm-svn: 146121
 2011-12-08 01:10:05 +00:00
Jim Grosbach
1ec6357689 Fix copy/past-o. 
llvm-svn: 146120
 2011-12-08 01:02:26 +00:00
Jim Grosbach
7e59d1c4db ARM NEON two-operand aliases for VMUL. 
llvm-svn: 146119
 2011-12-08 00:59:47 +00:00
Jakob Stoklund Olesen
ff1463af3b Don't include alignment padding in BBInfo.Size. 
Compute alignment padding before and after basic blocks dynamically.

Heed basic block alignment.

This simplifies bookkeeping because we don't have to constantly add and
remove padding from BBInfo.Size.  It also makes it possible to track the
extra known alignment bits we get after a tBR_JTr terminator and when
entering an aligned basic block.

This makes the ARMConstantIslandPass aware of aligned basic blocks.

It is tricky to model block alignment correctly when dealing with inline
assembly and tBR_JTr instructions that have variable size.  If inline
assembly turns out to be smaller than expected, that may cause following
alignment padding to be larger than expected.  This could cause constant
pool entries to move out of range.

To avoid that problem, we use the worst case alignment padding following
inline assembly. This may cause slightly suboptimal constant island
placement in aligned basic blocks following inline assembly.  Normal
functions should be unaffected.

llvm-svn: 146118
 2011-12-08 00:55:02 +00:00
Jim Grosbach
597cb99d62 ARM VFP support 'fmrs/fmsr' aliases for 'vldr' 
llvm-svn: 146116
 2011-12-08 00:52:55 +00:00
Jim Grosbach
fa73a483a9 ARM VFP support 'flds/fldd' aliases for 'vldr' 
llvm-svn: 146115
 2011-12-08 00:49:29 +00:00
Jim Grosbach
3b4d5c0510 ARM optional destination operand variants for VEXT instructions. 
llvm-svn: 146114
 2011-12-08 00:43:47 +00:00
Jim Grosbach
c1cf417595 ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". 
llvm-svn: 146111
 2011-12-08 00:31:07 +00:00
Jim Grosbach
6146f79b7d ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands. 
For 'gas' compatibility.

llvm-svn: 146106
 2011-12-07 23:40:58 +00:00
Akira Hatanaka
5c18dd9da0 Modify class ReadHardware and add definition of 64-bit version of instruction 
RDHWR. 

llvm-svn: 146101
 2011-12-07 23:31:26 +00:00
Akira Hatanaka
9aac8897da Add newline. 
llvm-svn: 146100
 2011-12-07 23:26:03 +00:00
Akira Hatanaka
5b94220d32 Add 64-bit HWR29 register. 
llvm-svn: 146099
 2011-12-07 23:23:52 +00:00
Akira Hatanaka
dcdd599065 32 to 64-bit anyext pattern. 
llvm-svn: 146097
 2011-12-07 23:21:19 +00:00
Akira Hatanaka
7db0038ac0 32 to 64-bit zext pattern. 
llvm-svn: 146096
 2011-12-07 23:14:41 +00:00
Jim Grosbach
dd3788b044 ARM two-operand aliases for VAND/VEOR/VORR instructions. 
llvm-svn: 146095
 2011-12-07 23:08:12 +00:00
Jim Grosbach
da0a3e310a ARM two-operand aliases for VADDW instructions. 
llvm-svn: 146093
 2011-12-07 23:01:10 +00:00
Jim Grosbach
ecf9c2bb21 ARM two-operand aliases for VADD instructions. 
llvm-svn: 146091
 2011-12-07 22:52:54 +00:00
Bruno Cardoso Lopes
96a462ec03 Variable cleanup. Based on past patch submittals variable names have 
been normalized and more descriptive comments added. Patch by Reed
Kotler and Jack Carter.

llvm-svn: 146088
 2011-12-07 22:35:30 +00:00
Akira Hatanaka
b8e63b4c07 64-bit WrapperPICPat patterns. 
llvm-svn: 146086
 2011-12-07 22:11:43 +00:00
Akira Hatanaka
61b72249eb Define base class for WrapperPICPat. 
llvm-svn: 146081
 2011-12-07 21:54:54 +00:00
Akira Hatanaka
2b45547782 Modify LowerFCOPYSIGN to handle Mips64. 
llvm-svn: 146080
 2011-12-07 21:48:50 +00:00
Akira Hatanaka
b170dc0eff Fix comment. 
llvm-svn: 146063
 2011-12-07 20:15:01 +00:00
Akira Hatanaka
e5c8837ed0 Fix comment. 
llvm-svn: 146062
 2011-12-07 20:13:53 +00:00
Akira Hatanaka
19d6cd4d0e Fix 64-bit immediate patterns. 
llvm-svn: 146059
 2011-12-07 20:10:24 +00:00
Jim Grosbach
268b95034c Nuke inadvertant debugging commit. 
llvm-svn: 146057
 2011-12-07 19:56:16 +00:00
Jim Grosbach
2f57374e32 Darwin assembler improved relocs when w/o subsections_via_symbols. 
When the file isn't being built with subsections-via-symbols, symbol
differences involving non-local symbols can be resolved more aggressively.
Needed for gas compatibility.

llvm-svn: 146054
 2011-12-07 19:46:59 +00:00
Jim Grosbach
1ccae84fa7 Thumb2 alias for long-form pop and friends. 
rdar://10542474

llvm-svn: 146046
 2011-12-07 18:32:28 +00:00
Jim Grosbach
81cb9952c9 ARM support the .arm and .thumb directives for assembly mode switching. 
llvm-svn: 146042
 2011-12-07 18:04:19 +00:00
Jim Grosbach
3352ab97ca ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
llvm-svn: 146039
 2011-12-07 17:51:15 +00:00
Craig Topper
6b3cc1405f Fix a bunch of SSE/AVX patterns to use proper memop types. In particular, not using integer loads other than v2i64/v4i64 since the others are all promoted. 
llvm-svn: 146031
 2011-12-07 08:30:53 +00:00
Bill Wendling
4741665fb1 Adjust the stack by one pointer size for all frameless stacks. 
llvm-svn: 146030
 2011-12-07 07:58:55 +00:00
Bill Wendling
757cba38ba Fix off-by-one error when encoding the stack size for a frameless stack. 
llvm-svn: 146029
 2011-12-07 07:49:49 +00:00
Evan Cheng
1acd685d87 Add bundle aware API for querying instruction properties and switch the code 
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
 2011-12-07 07:15:52 +00:00
Hal Finkel
01f7c7a17e make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs 
llvm-svn: 146024
 2011-12-07 06:34:06 +00:00
Hal Finkel
604156e099 make base register selection used in eliminateFrameIndex 64-bit clean 
llvm-svn: 146023
 2011-12-07 06:34:02 +00:00
Hal Finkel
8589827358 set mayStore and mayLoad on CR pseudos 
llvm-svn: 146022
 2011-12-07 06:33:57 +00:00
Hal Finkel
fa3b46319d 64-bit LR8 load should use X11 not R11 
llvm-svn: 146021
 2011-12-07 06:32:37 +00:00
Jakob Stoklund Olesen
2f0e1e182f Eliminate delta argument from AdjustBBOffsetsAfter. 
The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.

Eliminate one redundant AdjustBBOffsetsAfter call.

llvm-svn: 146018
 2011-12-07 05:17:30 +00:00
Jakob Stoklund Olesen
90c2c87a91 Compute some alignment information for each basic block. 
These fields are not used for anything yet.

llvm-svn: 146017
 2011-12-07 04:17:35 +00:00
Jim Grosbach
a740cc6bc9 ARM tidy up and remove no longer needed InstAlias definitions. 
The TokenAlias handling of data type suffices renders these unnecessary.

llvm-svn: 146010
 2011-12-07 01:50:36 +00:00
Jakob Stoklund Olesen
d3e5443796 Move common expression into a method. 
llvm-svn: 146008
 2011-12-07 01:22:52 +00:00
Jim Grosbach
19d37b966b ARM Implement ARM ARM Table A7-3 via TokenAlias. 
Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.

rdar://10435076

llvm-svn: 146007
 2011-12-07 01:17:58 +00:00
Jakob Stoklund Olesen
a2d7f79da0 Group BBSizes and BBOffsets into a single vector<BasicBlockInfo>. 
No functional change is intended.

llvm-svn: 146005
 2011-12-07 01:08:25 +00:00
Jim Grosbach
57478f4961 ARM: NEON SHLL instruction immediate operand range checking. 
llvm-svn: 146003
 2011-12-07 01:07:24 +00:00
Bruno Cardoso Lopes
d610f464bf Add a few moreLocal/Global R_MIPS_GOT related fixups and 
make the addend fixup code a bit more generic

Patch by Jack Carter.

llvm-svn: 145998
 2011-12-07 00:28:57 +00:00
Jim Grosbach
960e6c5a43 ARM: Parameterize the immediate operand type for NEON VSHLL. 
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.

llvm-svn: 145994
 2011-12-07 00:02:17 +00:00
Jakob Stoklund Olesen
436d9f98e3 Revert r145971: "Use conservative size estimate for tBR_JTr." 
This caused more offset errors.

llvm-svn: 145980
 2011-12-06 22:41:31 +00:00
Bill Wendling
7380d4e412 Explicitly check for the different SUB instructions. 
llvm-svn: 145976
 2011-12-06 22:14:27 +00:00
Evan Cheng
5061553f9d First chunk of MachineInstr bundle support. 
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975
 2011-12-06 22:12:01 +00:00