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20053 Commits

Author SHA1 Message Date
Akira Hatanaka
4068c25521 Lower 64-bit constant pool node. 
llvm-svn: 144849
 2011-11-16 22:44:38 +00:00
Akira Hatanaka
5f347432ca Lower 64-bit block address. 
llvm-svn: 144847
 2011-11-16 22:42:10 +00:00
Jim Grosbach
a14a3d22b1 Fix encoding of NOP used for padding in ARM mode .align. 
llvm-svn: 144842
 2011-11-16 22:40:25 +00:00
Akira Hatanaka
ca79236173 Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool 
nodes.

llvm-svn: 144841
 2011-11-16 22:39:56 +00:00
Akira Hatanaka
bb56ec5caf 64-bit jump register instruction. 
llvm-svn: 144840
 2011-11-16 22:36:01 +00:00
Evan Cheng
5bae2333cb Another missing X86ISD::MOVLPD pattern. rdar://10450317 
llvm-svn: 144839
 2011-11-16 22:24:44 +00:00
Jim Grosbach
8c8d091ecc ARM assembly parsing for shifted register operands for MOV instruction. 
llvm-svn: 144837
 2011-11-16 21:50:05 +00:00
Jim Grosbach
6007a95d57 Clean up debug printing of ARM shifted operands. 
llvm-svn: 144836
 2011-11-16 21:46:50 +00:00
Jim Grosbach
e9b1f2aead ARM assmebly two operand forms for LSR, ASR, LSL, ROR register. 
llvm-svn: 144814
 2011-11-16 19:12:24 +00:00
Jim Grosbach
18844fca8d ARM assembly parsing for RRX mnemonic. 
rdar://9704684

llvm-svn: 144812
 2011-11-16 19:05:59 +00:00
Pete Cooper
4f4a9794b2 Added missing comment about new custom lowering of DEC64 
llvm-svn: 144811
 2011-11-16 19:03:23 +00:00
Chad Rosier
69f9c432a6 Check to make sure we can select the instruction before trying to put the 
operands into a register.  Otherwise, we may materialize dead code.

llvm-svn: 144805
 2011-11-16 18:39:44 +00:00
Jim Grosbach
acb7c2d555 ARM mode aliases for bitwise instructions w/ register operands. 
rdar://9704684

llvm-svn: 144803
 2011-11-16 18:31:45 +00:00
Bob Wilson
70092e2b0a Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup. 
llvm-svn: 144798
 2011-11-16 17:09:59 +00:00
NAKAMURA Takumi
9a0c941fff lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled. 
llvm-svn: 144794
 2011-11-16 09:18:28 +00:00
Evan Cheng
2b239cbcf6 Sink codegen optimization level into MCCodeGenInfo along side relocation model 
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.

llvm-svn: 144788
 2011-11-16 08:38:26 +00:00
Craig Topper
7a4d482aaa Fix the execution domain on a bunch of SSE/AVX instructions. 
llvm-svn: 144784
 2011-11-16 07:30:46 +00:00
Bob Wilson
0e88464871 Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602> 
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal.  The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block.  The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op.  The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.

Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic.  Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.

llvm-svn: 144781
 2011-11-16 07:11:57 +00:00
Craig Topper
d842079270 Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636. 
llvm-svn: 144777
 2011-11-16 05:02:04 +00:00
Chad Rosier
17577c9394 Add FIXME comment. 
llvm-svn: 144743
 2011-11-16 00:32:20 +00:00
Jakob Stoklund Olesen
5ea426cfa8 Enable -widen-vmovs by default. 
This will widen 32-bit register vmov instructions to 64-bit when
possible.  The 64-bit vmovd instructions can then be translated to NEON
vorr instructions by the execution dependency fix pass.

The copies are only widened if they are marked as clobbering the whole
D-register.

llvm-svn: 144734
 2011-11-15 23:53:18 +00:00
Jim Grosbach
044acb8bee ARM assembly parsing for register range syntax for VLD/VST register lists. 
For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128

llvm-svn: 144727
 2011-11-15 23:19:15 +00:00
Jim Grosbach
778bed02bb ARM assembly parsing for data type suffices on NEON VMOV aliases. 
llvm-svn: 144722
 2011-11-15 22:54:42 +00:00
Nadav Rotem
63be4a26a9 AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code. 
llvm-svn: 144720
 2011-11-15 22:50:37 +00:00
Jim Grosbach
b8ebc386df ARM assembly parsing two operand forms for shift instructions. 
llvm-svn: 144713
 2011-11-15 22:27:54 +00:00
Jim Grosbach
d573473cb8 ARM VFP assembly parsing for VADD and VSUB two-operand forms. 
llvm-svn: 144710
 2011-11-15 22:15:10 +00:00
Jim Grosbach
e991d79b50 ARM accept an immediate offset in memory operands w/o the '#'. 
llvm-svn: 144709
 2011-11-15 22:14:41 +00:00
Pete Cooper
8441c08e0b Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used 
by later instructions.

Only done for DEC64m right now.

Fixes <rdar://problem/6172640>

llvm-svn: 144705
 2011-11-15 21:57:53 +00:00
Jim Grosbach
8f360855cf ARM enclosing curly braces optional on one-register VLD/VST instruction lists. 
'vld1.f32 d4, [r7]' should be parsed as equivalent to 'vld1.f32 {d4}, [r7]'

rdar://10450488.

llvm-svn: 144701
 2011-11-15 21:45:55 +00:00
Jim Grosbach
3c205132ff ARM size suffix on VFP single-precision 'vmov' is optional. 
rdar://10435114

llvm-svn: 144698
 2011-11-15 21:18:35 +00:00
Jim Grosbach
f68b81adb7 Fix typo. 
llvm-svn: 144695
 2011-11-15 21:01:30 +00:00
Jim Grosbach
4d0ad5a4e0 ARM alternate size suffices for VTRN instructions. 
rdar://10435076

llvm-svn: 144694
 2011-11-15 20:49:46 +00:00
Owen Anderson
f71db061ba Fix a misplaced paren bug. 
llvm-svn: 144692
 2011-11-15 20:30:41 +00:00
Jim Grosbach
8987b277cb ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. 
Yet more of rdar://10435076.

llvm-svn: 144691
 2011-11-15 20:29:42 +00:00
Jim Grosbach
f0690cd90c ARM assembly parsing for two-operand form of 'mul' instruction. 
rdar://10449856.

llvm-svn: 144689
 2011-11-15 20:14:51 +00:00
Jim Grosbach
8b1d4c989c ARM assembly parsing for two-operand form of 'mul' instruction. 
Ongoing rdar://10435114.

llvm-svn: 144688
 2011-11-15 20:02:06 +00:00
Jim Grosbach
6dbfffcbf7 Thumb2 two-operand 'mul' instruction wide encoding parsing. 
rdar://10449724

llvm-svn: 144684
 2011-11-15 19:55:16 +00:00
Owen Anderson
35f049f1fb Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. 
llvm-svn: 144683
 2011-11-15 19:55:00 +00:00
Jim Grosbach
df951fa128 Thumb2 assembly parsing for mul.w in IT block fix. 
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

llvm-svn: 144679
 2011-11-15 19:29:45 +00:00
Akira Hatanaka
040e92857f Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit 
registers and instructions when ABI is N64.

llvm-svn: 144666
 2011-11-15 18:53:55 +00:00
Akira Hatanaka
a6c12123f1 Set nomacro before emitting the sequence of instructions that set global pointer 
register.

llvm-svn: 144665
 2011-11-15 18:44:44 +00:00
Akira Hatanaka
666a872159 Simplify function PassByValArg64. 
llvm-svn: 144664
 2011-11-15 18:42:25 +00:00
Akira Hatanaka
4cbb3e4ca4 Delete files. 
llvm-svn: 144655
 2011-11-15 18:22:48 +00:00
Akira Hatanaka
ef7310d4a2 Remove MipsMCSymbolRefExpr. 
llvm-svn: 144654
 2011-11-15 18:20:08 +00:00
Jim Grosbach
61c3f1b35b ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions. 
rdar://10435076

llvm-svn: 144650
 2011-11-15 17:49:59 +00:00
Jay Foad
ebf2ec40e0 Fix typo in comment. 
llvm-svn: 144633
 2011-11-15 07:50:05 +00:00
Jay Foad
b4bb79247a Make use of MachinePointerInfo::getFixedStack. This removes all mention 
of PseudoSourceValue from lib/Target/.

llvm-svn: 144632
 2011-11-15 07:34:52 +00:00
Jay Foad
7d05fea7f8 Remove some unnecessary includes of PseudoSourceValue.h. 
llvm-svn: 144631
 2011-11-15 07:24:32 +00:00
Craig Topper
320d3ef477 Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled. 
llvm-svn: 144629
 2011-11-15 06:39:01 +00:00
Craig Topper
a584521daa Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370. 
llvm-svn: 144622
 2011-11-15 05:55:35 +00:00
Evan Cheng
47d8f8af84 Add vmov.f32 to materialize f32 immediate splats which cannot be handled by 
integer variants. rdar://10437054

llvm-svn: 144608
 2011-11-15 02:12:34 +00:00
Jim Grosbach
2ac98a24aa ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions. 
rdar://10435076

llvm-svn: 144606
 2011-11-15 01:46:57 +00:00
Jakob Stoklund Olesen
2709f65821 Break false dependencies before partial register updates. 
Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix
about instructions with partial register updates causing false unwanted
dependencies.

The ExecutionDepsFix pass will break the false dependencies if the
updated register was written in the previoius N instructions.

The small loop added to sse-domains.ll runs twice as fast with
dependency-breaking instructions inserted.

llvm-svn: 144602
 2011-11-15 01:15:30 +00:00
Jim Grosbach
6846540505 ARM parsing datatype suffix variants for non-writeback VST1 instructions. 
rdar://10435076

llvm-svn: 144593
 2011-11-14 23:43:46 +00:00
Jim Grosbach
a1a28df278 ARM parsing datatype suffix variants for non-writeback VLD1 instructions. 
rdar://10435076

llvm-svn: 144592
 2011-11-14 23:32:59 +00:00
Jim Grosbach
8ec84fbe99 Add explanatory comment. 
llvm-svn: 144589
 2011-11-14 23:21:09 +00:00
Jim Grosbach
1d07736422 Split out the plain '.{8|16|32|64}' suffix handling. 
Make it easier to deal with aliases for instructions that do require a suffix
but accept more specific variants of the same size.

llvm-svn: 144588
 2011-11-14 23:20:14 +00:00
Jim Grosbach
00283a5c8e ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions. 
rdar://10435076

llvm-svn: 144587
 2011-11-14 23:11:19 +00:00
Chad Rosier
4e05d7f12c Supporting inline memmove isn't going to be worthwhile. The only way to avoid 
violating a dependency is to emit all loads prior to stores.  This would likely
cause a great deal of spillage offsetting any potential gains.

llvm-svn: 144585
 2011-11-14 23:04:09 +00:00
Jim Grosbach
4a2f107b04 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

llvm-svn: 144583
 2011-11-14 23:03:21 +00:00
Chad Rosier
48b92815e0 Add support for inlining small memcpys. 
rdar://10412592

llvm-svn: 144578
 2011-11-14 22:46:17 +00:00
Chad Rosier
8aa8f14940 Fix a performance regression from r144565. Positive offsets were being lowered 
into registers, rather then encoded directly in the load/store.

llvm-svn: 144576
 2011-11-14 22:34:48 +00:00
Jim Grosbach
009733c9e4 ARM assembly parsing type suffix options for VLDR/VSTR. 
rdar://10435076

llvm-svn: 144575
 2011-11-14 22:28:39 +00:00
Evan Cheng
2034ff3b0b Add a missing pattern for X86ISD::MOVLPD. rdar://10436044 
llvm-svn: 144566
 2011-11-14 20:35:52 +00:00
Chad Rosier
65395ac4d0 Add support for Thumb load/stores with negative offsets. 
rdar://10412592

llvm-svn: 144565
 2011-11-14 20:22:27 +00:00
Benjamin Kramer
8450065be6 Unbreak Release builds. 
llvm-svn: 144560
 2011-11-14 19:51:48 +00:00
Pete Cooper
c9d6834f38 Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom lowered 
Constant idx case is still done in tablegen but other cases are then expanded

Fixes <rdar://problem/10435460>

llvm-svn: 144557
 2011-11-14 19:38:42 +00:00
Akira Hatanaka
9dd2dd0320 32-to-64-bit extended load. 
llvm-svn: 144554
 2011-11-14 19:06:14 +00:00
Akira Hatanaka
282b708fcb AnalyzeCallOperands function for N32/64. 
N32/64 places all variable arguments in integer registers (or on stack),
regardless of their types, but follows calling convention of non-vaarg function
when it handles fixed arguments.

llvm-svn: 144553
 2011-11-14 19:02:54 +00:00
Akira Hatanaka
b147de0ada Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64. 
llvm-svn: 144552
 2011-11-14 19:01:09 +00:00
Justin Holewinski
4e7a1c571b PTX: Let LLVM use loads/stores for all mem* intrinsics, instead of relying on custom implementations. 
llvm-svn: 144551
 2011-11-14 18:58:20 +00:00
Akira Hatanaka
db610fb423 Remove variable that keeps the size of area used to save byval or variable 
argument registers on the callee's stack frame, along with functions that set
and get it.
    
It is not necessary to add the size of this area when computing stack size in
emitPrologue, since it has already been accounted for in
PEI::calculateFrameObjectOffsets.

llvm-svn: 144549
 2011-11-14 18:56:20 +00:00
Jim Grosbach
d791cf718c Tidy up. 80 column. 
llvm-svn: 144538
 2011-11-14 17:52:47 +00:00
Craig Topper
ee3a3cf35c Add AVX2 version of instructions to load folding tables. Also add a bunch of missing SSE/AVX instructions. 
llvm-svn: 144525
 2011-11-14 08:07:55 +00:00
Craig Topper
e0b34012db Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway. 
llvm-svn: 144522
 2011-11-14 06:46:21 +00:00
Chad Rosier
0e5094ca87 Add support for ARM halfword load/stores and signed byte loads with negative 
offsets.
rdar://10412592

llvm-svn: 144518
 2011-11-14 04:09:28 +00:00
Craig Topper
0c7b1d7cf1 Add BLSI, BLSMSK, and BLSR to getTargetNodeName. 
llvm-svn: 144502
 2011-11-13 17:31:07 +00:00
Chad Rosier
58ab241006 The order in which the predicate is added differs between Thumb and ARM mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. 
llvm-svn: 144494
 2011-11-13 09:44:21 +00:00
Chad Rosier
8cfccc356e Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing failures. 
llvm-svn: 144492
 2011-11-13 05:14:43 +00:00
Chad Rosier
0770c4834a Fix comments. 
llvm-svn: 144490
 2011-11-13 04:25:02 +00:00
Chad Rosier
acd199b5a4 Add support for emitting both signed- and zero-extend loads. Fix 
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1

llvm-svn: 144488
 2011-11-13 02:23:59 +00:00
Craig Topper
0458cdf64a Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code. 
llvm-svn: 144457
 2011-11-12 09:58:49 +00:00
Akira Hatanaka
58e0babe25 Fix typo. 
llvm-svn: 144453
 2011-11-12 02:38:12 +00:00
Akira Hatanaka
53f5f9bc9f Implement Mips64's handling of byval arguments in LowerCall. 
llvm-svn: 144452
 2011-11-12 02:34:50 +00:00
Akira Hatanaka
26219cc439 Implement Mips64's handling of byval arguments in LowerFormalArguments. 
llvm-svn: 144449
 2011-11-12 02:29:58 +00:00
Akira Hatanaka
892b99b327 64-bit arbitrary immediate pattern. 
llvm-svn: 144448
 2011-11-12 02:25:00 +00:00
Akira Hatanaka
a0188ffa09 Function for handling byval arguments. 
llvm-svn: 144447
 2011-11-12 02:20:46 +00:00
Daniel Dunbar
73d41b0f03 build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies. 
- The hope is that we have a tool/test to verify these are accurate (and tight) soon.

llvm-svn: 144444
 2011-11-12 02:10:57 +00:00
Jim Grosbach
7e41554aa7 ARM refactor simple immediate asm operand render methods. 
These immediate operands all use the same simple logic for rendering to
MCInst, so have them share the method for doing so.

llvm-svn: 144439
 2011-11-12 00:58:43 +00:00
Jim Grosbach
312b583950 Re-apply 144430, this time with the associated isel and disassmbler bits. 
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'

llvm-svn: 144437
 2011-11-12 00:31:53 +00:00
Jim Grosbach
7fccd540c9 Oops. Missed the isel half of this. revert while I sort that out. 
llvm-svn: 144431
 2011-11-11 23:51:31 +00:00
Jim Grosbach
13af5276a1 ARM assembly parsing for VST1 two-register encoding. 
llvm-svn: 144430
 2011-11-11 23:45:47 +00:00
Jim Grosbach
13b7ab7527 ARM optional size suffix for VLDR/VSTR syntax. 
llvm-svn: 144427
 2011-11-11 23:34:43 +00:00
Chad Rosier
a2a0fbeded Add support in fast-isel for selecting memset/memcpy/memmove intrinsics. 
llvm-svn: 144426
 2011-11-11 23:31:03 +00:00
Daniel Dunbar
67b8edce31 CMake: Fix CMake build for new Mips tblgen file. 
llvm-svn: 144423
 2011-11-11 23:12:56 +00:00
Jim Grosbach
bc077320e1 ARM vldm and vstm VFP instructions can take a data type suffix. 
It's ignored by the assembler when present, but is legal syntax. Other
instructions have something similar, but for some mnemonics it's
only sometimes not significant, so this quick check in the parser will
need refactored into something more robust soon-ish. This gets some
basics working in the meantime.

Partial for rdar://10435264

llvm-svn: 144422
 2011-11-11 23:08:10 +00:00
Daniel Dunbar
a626481a77 Target/LLVMBuild: Order components alphabetically. 
llvm-svn: 144415
 2011-11-11 22:59:16 +00:00
Bruno Cardoso Lopes
bc4e9ca90e Mips MC object code emission improvements: 
"With this patch we can now generate runnable Mips code through LLVM
direct object emission. We have run numerous simple programs, both C
and C++ and with -O0 and -O3 from the output. The code is not production
ready, but quite useful for experimentation." Patch and message by
Jack Carter

llvm-svn: 144414
 2011-11-11 22:58:42 +00:00
Jim Grosbach
01a7117803 Nuke no longer accurate comment. 
llvm-svn: 144411
 2011-11-11 22:30:06 +00:00
Andrew Trick
6ff75a5d8d Preserve MachineMemOperands in ARMLoadStoreOptimizer. 
Fixes PR8113.

llvm-svn: 144409
 2011-11-11 22:18:09 +00:00
Jim Grosbach
1d581ecb00 ARM allow Q registers in vldm/vstm register lists. 
rdar://9672822

llvm-svn: 144407
 2011-11-11 21:27:40 +00:00
Dan Bailey
ad6c209a79 allow non-device function calls in PTX when natively handling device-side printf 
llvm-svn: 144388
 2011-11-11 14:45:12 +00:00
Dan Bailey
6c29989135 add rules in tabgen for PTX COPY_ADDRESS of frameindex 
llvm-svn: 144387
 2011-11-11 14:45:06 +00:00
Benjamin Kramer
e5295a772e Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler. 
llvm-svn: 144384
 2011-11-11 12:39:41 +00:00
Benjamin Kramer
e2cdc6f3e7 Remove the unnecessary dependency on libMBlazeCodeGen from libMBlazeDisassembler. 
llvm-svn: 144383
 2011-11-11 12:39:35 +00:00
Craig Topper
50df7c3842 Add lowering for AVX2 shift instructions. 
llvm-svn: 144380
 2011-11-11 07:39:23 +00:00
Chad Rosier
98f48b009e Rename variables to avoid confusion. No functionallity change intended. 
llvm-svn: 144377
 2011-11-11 06:27:41 +00:00
Chad Rosier
feb72bfc08 Add support for using immediates with select instructions. 
rdar://10412592

llvm-svn: 144376
 2011-11-11 06:20:39 +00:00
Akira Hatanaka
4ff64c3ed4 Do not try to detect DAG combine patterns for integer multiply-add/sub if value 
type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.

llvm-svn: 144373
 2011-11-11 04:18:21 +00:00
Akira Hatanaka
3b1457c21d 64-bit atomic instructions. 
llvm-svn: 144372
 2011-11-11 04:14:30 +00:00
Akira Hatanaka
40d8c440ad Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64. 
llvm-svn: 144371
 2011-11-11 04:11:56 +00:00
Akira Hatanaka
23c5cb5daf Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC. 
llvm-svn: 144370
 2011-11-11 04:06:38 +00:00
Akira Hatanaka
b83d016dd7 64-bit versions of jal, jalr and bal. 
llvm-svn: 144368
 2011-11-11 04:03:54 +00:00
Akira Hatanaka
5f233b2627 Emit Mips64's sequence of instructions that set global register in prologue. 
llvm-svn: 144367
 2011-11-11 04:00:29 +00:00
Akira Hatanaka
e56d824b2e Fix printing of MCSymbolRegExpr. Needs three closing parentheses for 
VK_Mips_GPOFF_HI/LO.

llvm-svn: 144366
 2011-11-11 03:58:36 +00:00
Eli Friedman
285b451941 Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3. 
llvm-svn: 144361
 2011-11-11 03:16:38 +00:00
Chad Rosier
38f07d3f9c When loading a value, treat an i1 as an i8. 
llvm-svn: 144356
 2011-11-11 02:38:59 +00:00
Bill Wendling
3c30beb55a If we have to reset the calculation of the compact encoding, then also reset the 
"saved register" index.
<rdar://problem/10430076>

llvm-svn: 144350
 2011-11-11 00:59:14 +00:00
Chad Rosier
ac92994773 Add support for using MVN to materialize negative constants. 
rdar://10412592

llvm-svn: 144348
 2011-11-11 00:36:21 +00:00
Daniel Dunbar
846fb32afc LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler. 
llvm-svn: 144344
 2011-11-11 00:23:56 +00:00
Jim Grosbach
ddf85f6be2 Thumb2 ldm/stm updating w/ one register in the list are LDR/STR. 
rdar://10429490

llvm-svn: 144338
 2011-11-10 23:58:34 +00:00
Jim Grosbach
d1d04109ff ARM let processInstruction() tranforms chain. 
llvm-svn: 144337
 2011-11-10 23:42:14 +00:00
Jim Grosbach
bd7df609b7 Thumb2 parsing for push/pop w/ hi registers in the reglist. 
rdar://10130228.

llvm-svn: 144331
 2011-11-10 23:17:11 +00:00
Jim Grosbach
615c824de4 Thumb1 diagnostics for reglist on PUSH/POP fix. 
Was not checking the first register in the register list.

llvm-svn: 144329
 2011-11-10 23:01:27 +00:00
Jim Grosbach
c3651cb620 Thumb MUL assembly parsing for 3-operand form. 
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

llvm-svn: 144322
 2011-11-10 22:10:12 +00:00
Daniel Dunbar
57e8d2b3d0 build/MBlazeDisassembler: Some compilers may generate an MBlaze disassembler 
that depends on MBlazeCodeGen. This is a layering violation that should really
be fixed.

llvm-svn: 144321
 2011-11-10 22:00:37 +00:00
Chad Rosier
7b7dced006 When in ARM mode, LDRH/STRH require special handling of negative offsets. 
For correctness, disable this for now.
rdar://10418009

llvm-svn: 144316
 2011-11-10 21:09:49 +00:00
Jim Grosbach
614f35bb30 ARM .thumb_func directive for quoted symbol names. 
Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.

rdar://10428015

llvm-svn: 144315
 2011-11-10 20:48:53 +00:00
Jim Grosbach
f5943e4c5e ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

llvm-svn: 144301
 2011-11-10 19:18:01 +00:00
Jim Grosbach
b66dfc2999 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

llvm-svn: 144293
 2011-11-10 16:44:55 +00:00
Daniel Dunbar
710e8f8758 build: Rename CBackend and CppBackend libraries to have CodeGen suffix, for 
consistency with other targets.

llvm-svn: 144292
 2011-11-10 15:35:14 +00:00
Nadav Rotem
e3d8f1a069 AVX2: Add variable shift from memory. 
Note: These patterns only works in some cases because
many times the load sd node is bitcasted from a load
node of a different type.

llvm-svn: 144266
 2011-11-10 06:54:20 +00:00
Chad Rosier
69cdae5eb9 For immediate encodings of icmp, zero or sign extend first. Then 
determine if the value is negative and flip the sign accordingly.
rdar://10422026

llvm-svn: 144258
 2011-11-10 01:30:39 +00:00
Daniel Dunbar
138437ad27 build/Make & CMake: Pass the appropriate --native-target and --enable-targets 
options to llvm-build, so the all-targets etc. components are defined properly.

llvm-svn: 144255
 2011-11-10 01:16:48 +00:00
Daniel Dunbar
f0c4aed0ab llvm-build: Add --native-target and --enable-targets options, and add logic to 
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
 - We still require these components to be in the project (currently in
   lib/Target) so that we have a place to document them and hopefully make it
   more obvious that they are "magic".

llvm-svn: 144253
 2011-11-10 00:50:07 +00:00
Daniel Dunbar
ce64a65fea llvm-build: Change CBackend and CppBackend to not use library_name. This will 
change the generated library .a file name once we fully switch over, but
simplifies how we treat these targets without requiring more special casing
(since their library group name and the codegen library name currently map to
the same "llvm-config" style component name).

llvm-svn: 144251
 2011-11-10 00:49:55 +00:00
Daniel Dunbar
c09b47db8f llvm-build: Add an explicit component type to represent targets. 
- Gives us a place to hang target specific metadata (like whether the target has a JIT).

llvm-svn: 144250
 2011-11-10 00:49:51 +00:00
Jim Grosbach
ee70556a4e Tidy up. 
llvm-svn: 144244
 2011-11-10 00:02:33 +00:00
Jim Grosbach
8591bd2bab Thumb2 assembly parsing STMDB w/ optional .w suffix. 
rdar://10422955

llvm-svn: 144242
 2011-11-09 23:44:23 +00:00
Eli Friedman
c93f8aa514 Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM. 
llvm-svn: 144241
 2011-11-09 23:36:02 +00:00
Chad Rosier
f47b941510 The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12. 
rdar://10418009

llvm-svn: 144213
 2011-11-09 21:30:12 +00:00
Nadav Rotem
ddc6bfa543 AVX2: Add patterns for variable shift operations 
llvm-svn: 144212
 2011-11-09 21:22:13 +00:00
Devang Patel
afcf6238fe Remove unnecessary include. 
llvm-svn: 144211
 2011-11-09 21:11:02 +00:00
Nadav Rotem
e66a72a2c4 Add AVX2 support for vselect of v32i8 
llvm-svn: 144187
 2011-11-09 13:21:28 +00:00
Craig Topper
432dd8d623 Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions. 
llvm-svn: 144179
 2011-11-09 09:37:21 +00:00
Craig Topper
7ff77dc2b1 Add instruction selection for AVX2 integer comparisons. 
llvm-svn: 144176
 2011-11-09 08:06:13 +00:00
Craig Topper
d82abb7156 Add AVX2 instruction lowering for add, sub, and mul. 
llvm-svn: 144174
 2011-11-09 07:28:55 +00:00
Chad Rosier
e32fed6868 Add support for encoding immediates in icmp and fcmp. Hopefully, this will 
remove a fair number of unnecessary materialized constants.
rdar://10412592

llvm-svn: 144163
 2011-11-09 03:22:02 +00:00
Evan Cheng
2b29230fcf Hide cpu name checking in ARMSubtarget. 
llvm-svn: 144154
 2011-11-09 01:57:03 +00:00
Bruno Cardoso Lopes
dc0559bff4 Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts. 
Patch by Jack Carter.

llvm-svn: 144139
 2011-11-08 22:26:47 +00:00
Evan Cheng
08e61752f2 Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs. 
llvm-svn: 144123
 2011-11-08 21:21:09 +00:00
Chad Rosier
24a6e399f8 ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this. 
No functional change intended.

llvm-svn: 144122
 2011-11-08 21:12:00 +00:00
Lang Hames
ee7de1cff0 Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported. 
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.

llvm-svn: 144102
 2011-11-08 18:56:23 +00:00
Pete Cooper
224434deec Added invariant field to the DAG.getLoad method and changed all calls. 
When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses

llvm-svn: 144100
 2011-11-08 18:42:53 +00:00
Bruno Cardoso Lopes
0c9933e29f This patch handles unaligned loads and stores in Mips JIT. Mips backend 
implements unaligned loads and stores with assembler macro-instructions
ulw, usw, ulh, ulhu, ush, and this patch emits corresponding instructions
instead of these macros. Since each unaligned load/store is expanded
into two corresponding loads/stores where offset for second load/store is
modified by +3 (for words) or +1 (for halfwords).

Patch by Petar Jovanovic and Sasa Stankovic.

llvm-svn: 144081
 2011-11-08 12:47:11 +00:00
NAKAMURA Takumi
167a2260c8 PPCInstrInfo.cpp: Fix one "unused" warning. 
llvm-svn: 144071
 2011-11-08 04:00:07 +00:00
Eli Friedman
d5ba38a3d2 Make sure to mark vector extload's as expand on ARM. Fixes PR11319. 
llvm-svn: 144057
 2011-11-08 01:43:53 +00:00
Evan Cheng
4a63100fe3 Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222 
llvm-svn: 144052
 2011-11-08 00:31:58 +00:00
Chad Rosier
4b12a5b7fc Enable support for returning i1, i8, and i16. Nothing special todo as it's the 
callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).

llvm-svn: 144047
 2011-11-08 00:03:32 +00:00
Chad Rosier
7e0e075322 Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well. 
llvm-svn: 144021
 2011-11-07 21:43:40 +00:00
Akira Hatanaka
36db890397 Various Mips64 floating point instruction patterns. 
llvm-svn: 144019
 2011-11-07 21:38:58 +00:00
Akira Hatanaka
cc6491001f Add definition of the base class for floating point comparison instructions 
and add Mips64's version too.

llvm-svn: 144018
 2011-11-07 21:37:33 +00:00
Akira Hatanaka
dad0ae9302 Add code needed for copying between 64-bit integer and floating pointer 
registers.

llvm-svn: 144017
 2011-11-07 21:35:45 +00:00
Akira Hatanaka
db8cbab444 Add definitions of 64-bit instructions which move data between integer and 
floating pointer registers.

llvm-svn: 144016
 2011-11-07 21:32:58 +00:00
Benjamin Kramer
89ebc7ab4b Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

llvm-svn: 144013
 2011-11-07 21:00:59 +00:00
Benjamin Kramer
34f13a0e6a Simplify code. No functionality change. 
llvm-svn: 144012
 2011-11-07 21:00:43 +00:00
Jakob Stoklund Olesen
b53be3a67d Expand V_SET0 to xorps by default. 
The xorps instruction is smaller than pxor, so prefer that encoding.

The ExecutionDepsFix pass will switch the encoding to pxor and xorpd
when appropriate.

llvm-svn: 143996
 2011-11-07 19:15:58 +00:00
Akira Hatanaka
1114d3b99d Add definition of 64-bit load upper immediate. 
llvm-svn: 143994
 2011-11-07 19:10:49 +00:00
Akira Hatanaka
8a1197eb04 Include RegSaveAreaSize in the computation of stack size. 
llvm-svn: 143993
 2011-11-07 19:07:35 +00:00
Akira Hatanaka
b464657da4 Define functions that get or set the size of area on callee's stack frame which 
is used to save va_arg or byval arguments passed in registers.

llvm-svn: 143992
 2011-11-07 19:06:10 +00:00
Akira Hatanaka
3841f239d0 Use array_lengthof to compute the number of iterations of a loop. 
llvm-svn: 143991
 2011-11-07 19:03:40 +00:00
Akira Hatanaka
d2343cd98f Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted 
when shift amount is larger than 32.

llvm-svn: 143990
 2011-11-07 19:01:49 +00:00
Akira Hatanaka
11fea5de78 Make the type of shift amount i32 in order to reduce the number of shift 
instruction definitions.

llvm-svn: 143989
 2011-11-07 18:59:49 +00:00
Akira Hatanaka
89c8797a02 Add 64-bit to 32-bit trunc pattern. 
llvm-svn: 143988
 2011-11-07 18:57:41 +00:00
Craig Topper
7eab73f510 Add AVX2 variable shift instructions and intrinsics. 
llvm-svn: 143915
 2011-11-07 08:26:24 +00:00
Craig Topper
b1ef950217 Add AVX2 VPMOVMASK instructions and intrinsics. 
llvm-svn: 143904
 2011-11-07 03:20:35 +00:00
Craig Topper
d422190c0f Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects. 
llvm-svn: 143902
 2011-11-07 02:00:04 +00:00
Craig Topper
01b852b95a More AVX2 instructions and their intrinsics. 
llvm-svn: 143895
 2011-11-06 23:04:08 +00:00
Benjamin Kramer
c597902ecc Replace (Lower|Upper)caseString in favor of StringRef's newest methods. 
llvm-svn: 143891
 2011-11-06 20:37:06 +00:00
Craig Topper
31b1d79474 Add more AVX2 instructions and intrinsics. 
llvm-svn: 143861
 2011-11-06 06:12:20 +00:00
Chad Rosier
806ffd8918 Add support for passing i1, i8, and i16 call parameters. Also, be sure to 
zero-extend the constant integer encoding.  Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.

llvm-svn: 143821
 2011-11-05 20:16:15 +00:00
Benjamin Kramer
3c2ba1a51a Add more PRI.64 macros for MSVC and use them throughout the codebase. 
llvm-svn: 143799
 2011-11-05 08:57:40 +00:00
Chad Rosier
af23ffd465 Allow i1 to be promoted to i32 for ARM APCS calling convention. 
llvm-svn: 143755
 2011-11-05 00:02:56 +00:00
Eli Friedman
1478b657c8 Enhanced vzeroupper insertion pass that avoids inserting vzeroupper where it is unnecessary through local analysis. Patch from Bruno Cardoso Lopes, with some additional changes. 
I'm going to wait for any review comments and perform some additional testing before turning this on by default.

llvm-svn: 143750
 2011-11-04 23:46:11 +00:00
Chad Rosier
5e54485e51 Cannot create a result register for non-legal types. 
llvm-svn: 143749
 2011-11-04 23:45:39 +00:00
Chad Rosier
a900a3e2f6 When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit 
in a 16-bit immediate.  However, for the shorter non-legal types (i.e., i1, i8,
i16) we should not sign-extend.  This prevents us from materializing things
such as 'true' (i.e., i1 1).

llvm-svn: 143743
 2011-11-04 23:09:49 +00:00
Chad Rosier
0143eb6f22 Enable support for materializing i1, i8, and i16 integers via move immediate. 
llvm-svn: 143739
 2011-11-04 22:29:00 +00:00
Daniel Dunbar
9d4a3de49f build/cmake: Coalesce the configuration time header include fragment generation 
for target definitions.

llvm-svn: 143731
 2011-11-04 19:04:42 +00:00
Daniel Dunbar
799f4bb723 build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just 
added a layer of indirection with no value (not even conciseness).

llvm-svn: 143727
 2011-11-04 19:04:23 +00:00
Eli Friedman
7c94e3bdad Add missing argument for atomic instructions in c++ backend. PR11268, part 2. 
llvm-svn: 143712
 2011-11-04 17:29:35 +00:00
Craig Topper
80cdc1ee12 Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructions 
llvm-svn: 143683
 2011-11-04 06:59:49 +00:00
Evan Cheng
e4d6efb7c4 Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. 
llvm-svn: 143675
 2011-11-04 01:48:58 +00:00
Chad Rosier
8836fe3bbd Indentation. 
llvm-svn: 143670
 2011-11-04 00:58:10 +00:00
Chad Rosier
21cd759234 Add fast-isel support for returning i1, i8, and i16. 
llvm-svn: 143669
 2011-11-04 00:50:21 +00:00
Dan Gohman
a5f382da8b Reapply r143206, with fixes. Disallow physical register lifetimes 
across calls, and only check for nested dependences on the special
call-sequence-resource register.

llvm-svn: 143660
 2011-11-03 21:49:52 +00:00
Dan Bailey
986e6b02b8 fixed global array handling for ptx to use the correct bit widths 
llvm-svn: 143640
 2011-11-03 19:24:46 +00:00
Daniel Dunbar
3760ebeebb build: Add initial cut at LLVMBuild.txt files. 
llvm-svn: 143634
 2011-11-03 18:53:17 +00:00
Craig Topper
124b2fd08c Add new X86 AVX2 VBROADCAST instructions. 
llvm-svn: 143612
 2011-11-03 07:35:53 +00:00
Chad Rosier
74c4e2c2d9 Add support for sign-extending non-legal types in SelectSIToFP(). 
llvm-svn: 143603
 2011-11-03 02:04:59 +00:00
Lang Hames
ba63f9da8b Fixed parameter name. 
llvm-svn: 143594
 2011-11-02 23:37:04 +00:00
Lang Hames
ceec8ec67e Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits. 
llvm-svn: 143582
 2011-11-02 22:52:45 +00:00
Chad Rosier
8a613c5ec5 Add support for comparing integer non-legal types. 
llvm-svn: 143559
 2011-11-02 18:08:25 +00:00
Owen Anderson
ac9fd95057 Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. 
llvm-svn: 143557
 2011-11-02 18:03:14 +00:00
Owen Anderson
66d22d36d2 The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552. 
llvm-svn: 143553
 2011-11-02 17:46:18 +00:00
Owen Anderson
9b966e47e2 Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case. 
llvm-svn: 143552
 2011-11-02 17:41:23 +00:00
Chad Rosier
e94ff7c26e Factor out an EmitIntExt function. No functionality change intended. 
llvm-svn: 143547
 2011-11-02 17:20:24 +00:00
Craig Topper
a2a55bd0b4 More AVX2 instructions and intrinsics. 
llvm-svn: 143536
 2011-11-02 06:54:17 +00:00
Craig Topper
c5482eb697 Add a bunch more X86 AVX2 instructions and their corresponding intrinsics. 
llvm-svn: 143529
 2011-11-02 04:42:13 +00:00
Chad Rosier
f72870096b Factor out a SelectTrunc function. No functionality change intended. 
llvm-svn: 143523
 2011-11-02 00:18:48 +00:00
Jim Grosbach
577b0f181e ARM label operands can be quoted. 
For example, labels from Objective-C sources.

llvm-svn: 143511
 2011-11-01 22:38:31 +00:00
Jim Grosbach
e5b5830aa1 ARM label operands can have an optional '#' before them. 
llvm-svn: 143510
 2011-11-01 22:37:37 +00:00
Owen Anderson
0d69f6aa51 Fix disassembly of some VST1 instructions. 
llvm-svn: 143507
 2011-11-01 22:18:13 +00:00
Sebastian Pop
f72a853709 rename getHostTriple into getDefaultTargetTriple 
llvm-svn: 143502
 2011-11-01 21:32:20 +00:00
Eli Friedman
c60a0ad611 Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant splat value. Fixes PR11289. 
llvm-svn: 143498
 2011-11-01 21:18:39 +00:00
Richard Osborne
5a9e575e81 Don't fold negative offsets into cp / dp accesses to avoid relocation errors. 
This can happen if the address + addend is less than the start of the cp / dp.

llvm-svn: 143459
 2011-11-01 11:31:53 +00:00
Jim Grosbach
c5f44d0b71 ARM VLD/VST assembly parsing for symbolic address operands. 
llvm-svn: 143413
 2011-11-01 01:24:45 +00:00
Eli Friedman
dc05741b6e Add support for new atomics to cpp backend. Misc other fixes while I'm here. PR11268. 
llvm-svn: 143406
 2011-10-31 23:59:22 +00:00
Jim Grosbach
76dd8a9702 ARM VST1 w/ writeback assembly parsing and encoding. 
llvm-svn: 143369
 2011-10-31 21:50:31 +00:00
Jim Grosbach
1cca1d4e60 ARM writeback vs. stride operands for VST/VLD. 
The _fixed variants have a writeback operand, but not a stride operand.
Split the conditional flag to distinguish the cases.

llvm-svn: 143356
 2011-10-31 19:11:23 +00:00
Owen Anderson
d7700cb13f More not-crashing NEON disassembly updates for the vld refactoring. 
llvm-svn: 143351
 2011-10-31 17:17:32 +00:00
Craig Topper
6eaf58df7c Begin adding AVX2 instructions. No selection support yet other than intrinsics. 
llvm-svn: 143331
 2011-10-31 02:15:10 +00:00
Nick Lewycky
7308946be2 Switch new .file directive emission off by default, change llc's flag for it to 
-enable-dwarf-directory.

llvm-svn: 143326
 2011-10-31 01:06:02 +00:00
Craig Topper
f2a9bd3a4a Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. 
llvm-svn: 143319
 2011-10-30 19:57:21 +00:00
Benjamin Kramer
c0001c42c6 X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in. 
llvm-svn: 143315
 2011-10-30 17:31:21 +00:00
Nadav Rotem
8282fc9e3b Fix pr11266. 
On x86: (shl V, 1) -> add V,V

Hardware support for vector-shift is sparse and in many cases we scalarize the
result. Additionally, on sandybridge padd is faster than shl.

llvm-svn: 143311
 2011-10-30 13:24:22 +00:00
Benjamin Kramer
7b1acc52c1 PPC: Disable moves for all CR subregisters. 
Should fix assertion failures on ppc buildbots.

llvm-svn: 143290
 2011-10-29 19:43:38 +00:00
Dan Gohman
826cec9a4b Revert r143206, as there are still some failing tests. 
llvm-svn: 143262
 2011-10-29 00:41:52 +00:00
Jim Grosbach
37119b8a01 ARM mode 'mov' to 'mvn' assembler alias. 
llvm-svn: 143237
 2011-10-28 22:50:54 +00:00
Jim Grosbach
f3285dba99 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm". 
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224

llvm-svn: 143235
 2011-10-28 22:36:30 +00:00
Owen Anderson
5fdb303642 Specify that the high bit of the alignment field is fixed to 0 on these instructions. 
llvm-svn: 143220
 2011-10-28 20:43:24 +00:00
Akira Hatanaka
f71673c585 Make changes necessary in LowerFormalArguments to support Mips64. 
llvm-svn: 143218
 2011-10-28 19:55:48 +00:00
Akira Hatanaka
3069ec27da Make changes necessary in LowerCall to support Mips64. 
llvm-svn: 143217
 2011-10-28 19:49:00 +00:00
Akira Hatanaka
856f4e30b2 Add variable IsO32 to MipsTargetLowering. 
llvm-svn: 143213
 2011-10-28 18:47:24 +00:00
Owen Anderson
3dd6c949a5 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. 
llvm-svn: 143208
 2011-10-28 18:02:13 +00:00
Dan Gohman
dedcc22bcd Reapply r143177 and r143179 (reverting r143188), with scheduler 
fixes: Use a separate register, instead of SP, as the
calling-convention resource, to avoid spurious conflicts with
actual uses of SP. Also, fix unscheduling of calling sequences,
which can be triggered by pseudo-two-address dependencies.

llvm-svn: 143206
 2011-10-28 17:55:38 +00:00
Owen Anderson
5ccc0979a0 Revert r143202. 
llvm-svn: 143203
 2011-10-28 17:38:30 +00:00
Owen Anderson
5c58be2852 Specify fixed bits on CPS instructions to enable roundtripping. 
llvm-svn: 143202
 2011-10-28 17:29:39 +00:00
Jim Grosbach
72ab459378 Thumb2 ADD/SUB instructions encoding selection outside IT block. 
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481

llvm-svn: 143201
 2011-10-28 16:57:07 +00:00
Duncan Sands
a6507c4bcb Speculatively disable Dan's commits 143177 and 143179 to see if 
it fixes the dragonegg self-host (it looks like gcc is miscompiled).
Original commit messages:
Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.

Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.

Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.

Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.

This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.

Delete #if 0 code accidentally left in.

llvm-svn: 143188
 2011-10-28 09:55:57 +00:00
Dan Gohman
484df993bd Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW 
on every node as it legalizes them. This makes it easier to use
hasOneUse() heuristics, since unneeded nodes can be removed from the
DAG earlier.

Make LegalizeOps visit the DAG in an operands-last order. It previously
used operands-first, because LegalizeTypes has to go operands-first, and
LegalizeTypes used to be part of LegalizeOps, but they're now split.
The operands-last order is more natural for several legalization tasks.
For example, it allows lowering code for nodes with floating-point or
vector constants to see those constants directly instead of seeing the
lowered form (often constant-pool loads). This makes some things
somewhat more complicated today, though it ought to allow things to be
simpler in the future. It also fixes some bugs exposed by Legalizing
using RAUW aggressively.

Remove the part of LegalizeOps that attempted to patch up invalid chain
operands on libcalls generated by LegalizeTypes, since it doesn't work
with the new LegalizeOps traversal order. Instead, define what
LegalizeTypes is doing to be correct, and transfer the responsibility
of keeping calls from having overlapping calling sequences into the
scheduler.

Teach the scheduler to model callseq_begin/end pairs as having a
physical register definition/use to prevent calls from having
overlapping calling sequences. This is also somewhat complicated, though
there are ways it might be simplified in the future.

This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others.
Please direct high-level questions about this patch to management.

llvm-svn: 143177
 2011-10-28 01:29:32 +00:00
Jim Grosbach
dac7815a91 ARM Allow 'q' registers in VLD/VST vector lists. 
Just treat it as if the constituent D registers where specified.

rdar://10348896

llvm-svn: 143167
 2011-10-28 00:06:50 +00:00
Dan Gohman
892b86e74c Remove the Alpha backend. 
llvm-svn: 143164
 2011-10-27 22:56:32 +00:00
Owen Anderson
d35df0aaeb Add some NEON stores to the VLD decoding hook that were accidentally omitted previously. 
llvm-svn: 143162
 2011-10-27 22:53:10 +00:00
Jakob Stoklund Olesen
de21509dcd Also set addrmode6 alignment when align==size. 
Previously, we were only setting the alignment bits on over-aligned
loads and stores.

llvm-svn: 143160
 2011-10-27 22:39:16 +00:00
Jim Grosbach
67d4fb4bc0 ARM isel for vld1, opcode selection for register stride post-index pseudos. 
llvm-svn: 143158
 2011-10-27 22:25:42 +00:00
Evan Cheng
75271d09f1 Avoid partial CPSR dependency from loop backedges. rdar://10357570 
llvm-svn: 143145
 2011-10-27 21:21:05 +00:00
Kevin Enderby
837c1d56a2 Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and 
not depend on In32BitMode.  Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode.  rdar://9738584

llvm-svn: 143112
 2011-10-27 17:40:41 +00:00
Jim Grosbach
4f7964293a Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix. 
rdar://10348844

llvm-svn: 143110
 2011-10-27 17:33:59 +00:00
Jim Grosbach
e1ec953149 Thumb2 t2MVNi assembly parsing to recognize ".w" suffix. 
rdar://10348584

llvm-svn: 143108
 2011-10-27 17:16:55 +00:00
Chad Rosier
e76ba1b654 A branch predicated on a constant can just FastEmit an unconditional branch. 
llvm-svn: 143086
 2011-10-27 00:21:16 +00:00