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134 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
9d1c8ecf05 Add a SPR register class to the ARM target. 
Certain Thumb instructions require only SP (e.g. tSTRspi).

llvm-svn: 91944
 2009-12-22 23:54:44 +00:00
Johnny Chen
04b3259f9d Renamed "tCMNZ" to "tCMNz" to be consistent with other similar namings. 
llvm-svn: 91571
 2009-12-16 23:36:52 +00:00
Johnny Chen
7339b74117 Add encoding bits for some Thumb instructions. Plus explicitly set the top two 
bytes of Inst to 0x0000 for the benefit of the Thumb decoder.

llvm-svn: 91496
 2009-12-16 02:32:54 +00:00
Johnny Chen
8ef481b5d7 Added encoding bits for the Thumb ISA. Initial checkin. 
llvm-svn: 91434
 2009-12-15 17:24:14 +00:00
Jim Grosbach
5541b5f793 Thumb1 exception handling setjmp 
llvm-svn: 90246
 2009-12-01 18:10:36 +00:00
Evan Cheng
9f57c4916e Remat VLDRD from constpool. Clean up some instruction property specifications. 
llvm-svn: 89478
 2009-11-20 19:57:15 +00:00
Evan Cheng
987b8c3d9a More consistent thumb1 asm printing. 
llvm-svn: 89328
 2009-11-19 06:57:41 +00:00
Evan Cheng
6e3e66375a - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative 
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304
 2009-11-06 23:52:48 +00:00
Evan Cheng
22121f4c69 The .n suffix must go after the predicate. 
llvm-svn: 86019
 2009-11-04 07:38:48 +00:00
Evan Cheng
1a06b12330 Use ldr.n to workaround a darwin assembler bug. 
llvm-svn: 85980
 2009-11-04 00:00:39 +00:00
Bob Wilson
97331f70ca For Thumb indirect branches, use "mov pc, reg" which does not switch 
between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.

llvm-svn: 85874
 2009-11-03 06:29:56 +00:00
Bob Wilson
3144715b53 Put BlockAddresses into ARM constant pools. 
llvm-svn: 85824
 2009-11-02 20:59:23 +00:00
Evan Cheng
de16fff3e8 Use cbz and cbnz instructions. 
llvm-svn: 85698
 2009-10-31 23:46:45 +00:00
Bob Wilson
95064e348a Add ARM codegen for indirect branches. 
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577
 2009-10-30 05:45:42 +00:00
Dan Gohman
3393a4c997 Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a 
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517
 2009-10-29 18:10:34 +00:00
Bob Wilson
af37728221 Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the 
opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411
 2009-10-28 18:26:41 +00:00
Evan Cheng
f30e5556ba Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space. 
llvm-svn: 85184
 2009-10-27 00:08:59 +00:00
Evan Cheng
241092d89f Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, 
ld / st pairs, etc.

llvm-svn: 83197
 2009-10-01 08:22:27 +00:00
Evan Cheng
4dd7d7156e Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions. 
llvm-svn: 83191
 2009-10-01 01:33:39 +00:00
Jim Grosbach
2d057f09e8 Add "isBarrier = 1" to return instructions. 
Patch by Sylvere Teissier.

llvm-svn: 83135
 2009-09-30 01:35:11 +00:00
Evan Cheng
6c89bc0472 Remove comments which don't add much to .s readibility. 
llvm-svn: 81306
 2009-09-09 01:38:23 +00:00
David Goodwin
0dd9e9edb4 Calls clobber FPSCR. 
llvm-svn: 80956
 2009-09-03 22:12:28 +00:00
Evan Cheng
493eee1fc7 Remove .n suffix for some 16-bit opcodes now that Darwin assembler is fixed. 
llvm-svn: 80615
 2009-08-31 20:14:07 +00:00
Evan Cheng
d53546a6cd Print a nl before pic labels so they start at a new line. This makes assembly more readable. 
llvm-svn: 80350
 2009-08-28 06:59:37 +00:00
Evan Cheng
2d5d3700e9 v4, v5 does not support sxtb / sxth. 
llvm-svn: 80322
 2009-08-28 00:31:43 +00:00
Bob Wilson
9482015a0a Rename ARM "lane_cst" operands to "nohash_imm" since they are used for 
several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676
 2009-08-21 21:58:55 +00:00
Evan Cheng
86546fb692 Fix an obvious copy-n-paste bug. 
llvm-svn: 79535
 2009-08-20 17:01:04 +00:00
David Goodwin
d57f44783c Update Cortex-A8 instruction itineraries for integer instructions. 
llvm-svn: 79436
 2009-08-19 18:00:44 +00:00
Evan Cheng
d4d2a3d0a6 Fix revsh pattern. 
llvm-svn: 79318
 2009-08-18 05:43:23 +00:00
Evan Cheng
7d8caa143b Also shrink immediate branches; also more assembler workarounds. 
llvm-svn: 79014
 2009-08-14 18:31:44 +00:00
Evan Cheng
45d6a21e21 Shrink ADR and LDR from constantpool late during constantpool island pass. 
llvm-svn: 78970
 2009-08-14 00:32:16 +00:00
David Goodwin
dd797db6bd Finalize itineraries for cortex-a8 integer multiply 
llvm-svn: 78908
 2009-08-13 15:51:13 +00:00
David Goodwin
90e7f9873c Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one. 
llvm-svn: 78827
 2009-08-12 18:31:53 +00:00
Evan Cheng
c369ccbe83 Shrink Thumb2 movcc instructions. 
llvm-svn: 78790
 2009-08-12 05:17:19 +00:00
Evan Cheng
410447e028 80 col violation. 
llvm-svn: 78778
 2009-08-12 02:03:03 +00:00
Evan Cheng
a29ee9f509 Shrinkify Thumb2 r = add sp, imm. 
llvm-svn: 78745
 2009-08-11 23:00:31 +00:00
Evan Cheng
783028063e Shrinkify Thumb2 load / store multiple instructions. 
llvm-svn: 78717
 2009-08-11 21:11:32 +00:00
Owen Anderson
48f2f0ae72 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
 2009-08-11 20:47:22 +00:00
Owen Anderson
b4bce99769 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
llvm-svn: 78610
 2009-08-10 22:56:29 +00:00
Evan Cheng
ad380aa97a Add support to reduce most of 32-bit Thumb2 arithmetic instructions. 
llvm-svn: 78550
 2009-08-10 02:37:24 +00:00
Anton Korobeynikov
44fa9f179c Use subclassing to print lane-like immediates (w/o hash) eliminating 
'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514
 2009-08-08 23:10:41 +00:00
Evan Cheng
fb833354b6 tADDhirr should target GPR, not tGPR. 
llvm-svn: 78454
 2009-08-08 03:19:44 +00:00
Evan Cheng
5af3c8154b tBfar is bl, which clobbers LR. 
llvm-svn: 78370
 2009-08-07 05:45:07 +00:00
Evan Cheng
48b49cf5b9 It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. 
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361
 2009-08-07 00:34:42 +00:00
David Goodwin
3aafcc1dd2 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
llvm-svn: 78321
 2009-08-06 16:52:47 +00:00
Evan Cheng
e366789b50 Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode. 
llvm-svn: 78126
 2009-08-04 23:47:55 +00:00
Evan Cheng
5ef6928dff Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same 
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756
 2009-08-01 00:16:10 +00:00
Evan Cheng
90a1ca6e17 Make sure Thumb2 uses the right call instructions. 
llvm-svn: 77507
 2009-07-29 21:26:42 +00:00
Evan Cheng
c8d3891c87 - Fix an obvious copy and paste error. 
- Darwin Thumb2 call clobbers r9.

llvm-svn: 77500
 2009-07-29 20:10:36 +00:00
Evan Cheng
cf483eb0c0 In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
llvm-svn: 77364
 2009-07-28 20:53:24 +00:00