Evan Cheng
ef8a1bcbc3
Each ARM use predicate operand is now made up of two components. The new component is the CPSR register.
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llvm-svn: 37895
2007-07-05 07:13:32 +00:00
Dan Gohman
9cbc3fb1ab
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Dan Gohman
b60d8a92c9
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Evan Cheng
12b3002673
Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
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llvm-svn: 37643
2007-06-19 01:26:51 +00:00
Evan Cheng
8eff719058
tBcc is not a barrier.
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llvm-svn: 37516
2007-06-08 09:13:23 +00:00
Evan Cheng
7b433a2954
Mark these instructions clobbersPred. They modify the condition code register.
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llvm-svn: 37468
2007-06-06 10:17:05 +00:00
Evan Cheng
b09bf9914f
ARM::tB is also predicable.
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llvm-svn: 37125
2007-05-16 21:53:43 +00:00
Evan Cheng
9f0ffdf4b3
Add PredicateOperand to all ARM instructions that have the condition field.
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llvm-svn: 37066
2007-05-15 01:29:07 +00:00
Evan Cheng
73abcaa525
Switch BCC, MOVCCr, etc. to PredicateOperand.
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llvm-svn: 36948
2007-05-08 21:08:43 +00:00
Evan Cheng
01853831d2
Doh. PC displacement is between the constantpool and the add instruction.
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llvm-svn: 36630
2007-05-01 20:27:19 +00:00
Lauro Ramos Venancio
f385b56870
ARM TLS: implement "general dynamic", "initial exec" and "local exec" models.
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llvm-svn: 36506
2007-04-27 13:54:47 +00:00
Evan Cheng
75ed5c5cb2
Back out previous check-in. Incorrect.
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llvm-svn: 36503
2007-04-27 07:50:02 +00:00
Evan Cheng
b54f757b65
tLEApcrel is a AddrModeTs, i.e. pc relative.
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llvm-svn: 36502
2007-04-27 07:37:22 +00:00
Lauro Ramos Venancio
7e21418680
- Divides the comparisons in two types: comparisons that only use N and Z
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flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP).
- Defines the instructions: TST, TEQ (ARM) and TST (Thumb).
llvm-svn: 35573
2007-04-02 01:30:03 +00:00
Evan Cheng
3a6b488265
Can't re-materialize mov r, imm in thumb since mov would clobber the condition code.
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llvm-svn: 35479
2007-03-29 21:38:31 +00:00
Lauro Ramos Venancio
8b2e32de5a
bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK.
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llvm-svn: 35381
2007-03-27 16:19:21 +00:00
Lauro Ramos Venancio
11d7d3fcaf
bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
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mov lr, pc
bx lr
So, the function was not called.
llvm-svn: 35218
2007-03-20 17:57:23 +00:00
Evan Cheng
8d374caead
Fix naming inconsistencies.
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llvm-svn: 35163
2007-03-19 07:48:02 +00:00
Evan Cheng
7cbf4c4582
Special LDR instructions to load from non-pc-relative constantpools. These are
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rematerializable. Only used for constant generation for now.
llvm-svn: 35162
2007-03-19 07:20:03 +00:00
Evan Cheng
389cf8e719
Constant generation instructions are re-materializable.
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llvm-svn: 35161
2007-03-19 07:09:02 +00:00
Evan Cheng
60bde0ebb1
Spill / restore should avoid modifying the condition register.
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llvm-svn: 33971
2007-02-07 00:06:56 +00:00
Evan Cheng
d3dc2eefc2
.set pc relative displacement bug: label should be moved down one instruction
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to just before the add r1, pc:
Before:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
Now:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
mov r1, #PCRELV0
LPCRELL0:
add r1, pc
llvm-svn: 33744
2007-02-01 03:04:49 +00:00
Evan Cheng
439dcbedba
Special epilogue for vararg functions. We cannot do a pop to pc because
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there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
pop {r4, r5, r6, r7}
pop {r3}
add sp, #3 * 4
bx r3
llvm-svn: 33739
2007-02-01 01:49:46 +00:00
Evan Cheng
a08ef111bb
Thumb asm syntax does not want 's' suffix for flag setting opcodes.
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llvm-svn: 33717
2007-01-31 20:12:31 +00:00
Evan Cheng
0f07707270
- Fix codegen for pc relative constant (e.g. JT) in thumb mode:
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.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
add r1, pc, #PCRELV0
This is not legal since add r1, pc, #c requires the constant be a multiple of 4.
Do the following instead:
.set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
mov r1, #PCRELV0
add r1, pc
- In thumb mode, it's not possible to use .set generate a pc relative stub
address. The stub is ARM code which is in a different section from the thumb
code. Load the value from a constpool instead.
- Some asm printing clean up.
llvm-svn: 33664
2007-01-30 20:37:08 +00:00
Evan Cheng
99a2f7d598
Change the operand orders to t_addrmode_s* to make it easier to morph
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instructions that use these address modes to instructions that use
t_addrmode_sp.
llvm-svn: 33651
2007-01-30 02:35:32 +00:00
Evan Cheng
a16118a6cf
Use BL to implement Thumb far jumps.
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llvm-svn: 33649
2007-01-30 01:13:37 +00:00
Evan Cheng
4618d3131c
Thumb jumptable support.
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llvm-svn: 33568
2007-01-27 02:29:45 +00:00
Evan Cheng
9805b66063
Thumb add / sub with carry.
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llvm-svn: 33562
2007-01-27 00:07:15 +00:00
Evan Cheng
55455f0532
Represent tADDspi and tSUBspi as two-address instructions.
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llvm-svn: 33551
2007-01-26 21:33:19 +00:00
Evan Cheng
d0c39ef1ca
extload -> zextload
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llvm-svn: 33542
2007-01-26 19:13:16 +00:00
Evan Cheng
c6db78ab84
Use PC relative ldr to load from a constantpool in Thumb mode.
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llvm-svn: 33484
2007-01-24 08:53:17 +00:00
Evan Cheng
5f947e4e2f
- Reorg Thumb load / store instructions. Combine each rr and ri pair of
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instructions into one (e.g. tLDRrr, tLDRri -> tLDR).
- Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the
address is not an add, materialize a 0 immediate into a register and use
it as the offset field.
llvm-svn: 33470
2007-01-23 22:59:13 +00:00
Evan Cheng
c6e1d453d3
ARM backend contribution from Apple.
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llvm-svn: 33353
2007-01-19 07:51:42 +00:00