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Author SHA1 Message Date
Chris Lattner
4218b7524c use Constant::getAggregateElement to simplify a bunch of code. 
llvm-svn: 148934
 2012-01-25 06:48:06 +00:00
Craig Topper
c2b030401c Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specific nodes so we can remove the isel patterns. 
llvm-svn: 148933
 2012-01-25 06:43:11 +00:00
Chris Lattner
6791b23efa constify some methods and add a new Constant::getAggregateElement 
helper method for the common operation of extracting an element
out of a constant aggregate.

llvm-svn: 148931
 2012-01-25 06:16:32 +00:00
Chris Lattner
473bdbaabc use ConstantVector::getSplat in a few places. 
llvm-svn: 148929
 2012-01-25 06:02:56 +00:00
Craig Topper
9edaa5c15a Custom lower phadd and phsub intrinsics to target specific nodes. Remove the patterns that are no longer necessary. 
llvm-svn: 148927
 2012-01-25 05:37:32 +00:00
Chris Lattner
276264ed59 reapply r148901 with a crucial fix. 
"Introduce a new ConstantVector::getSplat constructor function to 
simplify a really common case."

llvm-svn: 148924
 2012-01-25 05:19:54 +00:00
Craig Topper
c968a4ccc9 Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been removed a while ago. 
llvm-svn: 148922
 2012-01-25 04:42:03 +00:00
Akira Hatanaka
d4dbda9412 Mark 64-bit register RA_64 unused too. 
llvm-svn: 148918
 2012-01-25 04:19:22 +00:00
Akira Hatanaka
175341c860 Modify MipsFrameLowering::emitPrologue and emitEpilogue. 
- Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit.
- Change the types of variables so that they are sufficiently large to handle
  64-bit pointers.
- Emit instructions to set register $28 in a function prologue after
  instructions which store callee-saved registers have been emitted. 
 

llvm-svn: 148917
 2012-01-25 04:12:04 +00:00
Akira Hatanaka
9a829c1762 Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate to 
expand offsets that do not fit in the 16-bit immediate field of load and store
instructions. Also change the types of variables so that they are sufficiently
large to handle 64-bit pointers.

llvm-svn: 148916
 2012-01-25 03:55:10 +00:00
Craig Topper
f4166abe42 Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction definitions. Matches non-AVX version of same instructions. 
llvm-svn: 148914
 2012-01-25 03:52:09 +00:00
Rafael Espindola
e3e205900c -fvisibility-inlines-hidden is a c++ only option. 
Thanks to Peter Collingbourne for noticing it.

llvm-svn: 148913
 2012-01-25 03:39:26 +00:00
NAKAMURA Takumi
9c48741bbe MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc. 
inttypes.h is not supplied in msvc.

llvm-svn: 148912
 2012-01-25 03:34:41 +00:00
Nick Lewycky
8b7c7ba376 Fix assert("msg"). Fix unused-variable warnings complaining about VT used only 
in asserts.

llvm-svn: 148910
 2012-01-25 03:20:12 +00:00
NAKAMURA Takumi
77cf8a4b29 Target/Mips: Unbreak CMake build. 
llvm-svn: 148909
 2012-01-25 03:15:46 +00:00
Akira Hatanaka
6880302ac2 Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. 
Add a test case to show fewer instructions are needed to load an immediate
with the new way of loading immediates.

llvm-svn: 148908
 2012-01-25 03:01:35 +00:00
Argyrios Kyrtzidis
c5d8deed3f Revert r148901 because it crashes llvm tests. 
Original log:
    Introduce a new ConstantVector::getSplat constructor function to
    simplify a really common case.

llvm-svn: 148906
 2012-01-25 02:42:41 +00:00
Chris Lattner
33f1fdff02 Introduce a new ConstantVector::getSplat constructor function to 
simplify a really common case.

llvm-svn: 148901
 2012-01-25 01:53:58 +00:00
Akira Hatanaka
f8475c3fa9 Add class MipsAnalyzeImmediate which comes up with an instruction sequence to 
load an immediate. 

llvm-svn: 148900
 2012-01-25 01:43:36 +00:00
Chris Lattner
884a2b01e2 Remove the Type::getNumElements() method, which is only called in 4 places, 
did something extremely surprising, and shadowed actually useful 
implementations that had completely different behavior.

llvm-svn: 148898
 2012-01-25 01:32:59 +00:00
Chris Lattner
834679362f Use the right method to get the # elements in a CDS. 
llvm-svn: 148897
 2012-01-25 01:27:20 +00:00
Jim Grosbach
e8095f3b49 NEON VLD4(all lanes) assembly parsing and encoding. 
llvm-svn: 148884
 2012-01-25 00:01:08 +00:00
Jim Grosbach
9c21d45c29 Tidy up. Rename VLD4DUP patterns for consistency. 
llvm-svn: 148883
 2012-01-24 23:47:07 +00:00
Jim Grosbach
f478b2a706 NEON VLD3(all lanes) assembly parsing and encoding. 
llvm-svn: 148882
 2012-01-24 23:47:04 +00:00
Talin
12820f024e Additional methods for SmallString. 
llvm-svn: 148881
 2012-01-24 23:43:59 +00:00
Jakob Stoklund Olesen
fe157f5fc1 Set correct <def,undef> flags when lowering REG_SEQUENCE. 
A REG_SEQUENCE instruction is lowered into a sequence of partial defs:

  %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0
  %vreg7:ssub_1<def> = COPY %vreg2
  %vreg7:ssub_2<def> = COPY %vreg2
  %vreg7:ssub_3<def> = COPY %vreg2

The first def needs an <undef> flag to indicate it is the beginning of
the live range, while the other defs are read-modify-write.  Previously,
we depended on LiveIntervalAnalysis to notice and fix the missing
<def,undef>, but that solution was never robust, it was causing problems
with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE
instructions.

This fixes PR11841.

llvm-svn: 148879
 2012-01-24 23:28:42 +00:00
Jakob Stoklund Olesen
17321093c2 Use the standard MachineFunction::print() after SlotIndexes. 
llvm-svn: 148878
 2012-01-24 23:28:38 +00:00
Akira Hatanaka
0d04fc2918 Sign-extend 32-bit integer arguments when they are passed in 64-bit registers, 
which is what N32/64 does.

llvm-svn: 148875
 2012-01-24 23:18:43 +00:00
Akira Hatanaka
00e3847fc8 Pass CCState by reference. 
llvm-svn: 148871
 2012-01-24 22:07:36 +00:00
Akira Hatanaka
12cdcf3bc6 Pattern for f32 to i64 conversion. 
llvm-svn: 148869
 2012-01-24 22:05:25 +00:00
Jim Grosbach
012239e10a ARM Darwin symbol ref differences w/o subsection-via-symbols. 
When not using subsections via symbols, the assembler can resolve
symbol differences (including pcrel references) to non-local
labels at assembly time, not just those in the same atom.

llvm-svn: 148865
 2012-01-24 21:45:25 +00:00
Devang Patel
0da753c9e6 Intel Syntax: Extend special hand coded logic, to recognize special instructions, for intel syntax. 
llvm-svn: 148864
 2012-01-24 21:43:36 +00:00
Akira Hatanaka
7b1d08124d 64-bit sign extension in register instructions. 
llvm-svn: 148862
 2012-01-24 21:41:09 +00:00
Jim Grosbach
8ed72f3cc0 Tidy up. Trailing whitespace. 
llvm-svn: 148856
 2012-01-24 21:06:59 +00:00
Matt Beaumont-Gay
b86c4c6d24 Sink assert-only variables into the asserts 
llvm-svn: 148849
 2012-01-24 19:43:30 +00:00
Kostya Serebryany
ca8b911b2d [asan] enable asan only for the functions that have Attribute::AddressSafety 
llvm-svn: 148846
 2012-01-24 19:34:43 +00:00
Jim Grosbach
e151b15949 NEON VST4(one lane) assembly parsing and encoding. 
llvm-svn: 148836
 2012-01-24 18:53:13 +00:00
Owen Anderson
7492e4ff85 Widen the instruction encoder that TblGen emits to a 64 bits, which should accomodate every target I can think of offhand. 
llvm-svn: 148833
 2012-01-24 18:37:29 +00:00
Jim Grosbach
a78348fcda NEON VLD4(one lane) assembly parsing and encoding. 
llvm-svn: 148832
 2012-01-24 18:37:25 +00:00
Jakob Stoklund Olesen
c81d459349 Fix old doxygen comment. 
llvm-svn: 148825
 2012-01-24 18:09:18 +00:00
Jakob Stoklund Olesen
3ff9738293 Add an (interleave A, B, ...) SetTheory operator. 
This will interleave the elements from two or more lists.

llvm-svn: 148824
 2012-01-24 18:06:05 +00:00
Chandler Carruth
f26c121c21 Undo an over zealous rename. This bit of the CMake build really is 
dealing in the host triple, be honest about it and document the decision
to default the target triple to the host triple unless overridden.

llvm-svn: 148822
 2012-01-24 18:00:44 +00:00
Jim Grosbach
f3607eac5d NEON Two-operand assembly aliases for VSRA. 
llvm-svn: 148821
 2012-01-24 17:55:36 +00:00
Jim Grosbach
47f7ce80b8 Remove redundant test file. 
llvm-svn: 148820
 2012-01-24 17:55:32 +00:00
Jim Grosbach
630dd380c7 NEON Two-operand assembly aliases for VSLI. 
llvm-svn: 148819
 2012-01-24 17:49:15 +00:00
Jim Grosbach
42c0f99aa0 NEON Two-operand assembly aliases for VSRI. 
llvm-svn: 148818
 2012-01-24 17:46:58 +00:00
Jim Grosbach
703b0bb646 Tidy up. 
llvm-svn: 148817
 2012-01-24 17:46:54 +00:00
Jim Grosbach
e00b69bf5b NEON add correct predicates for some asm aliases. 
llvm-svn: 148815
 2012-01-24 17:23:29 +00:00
David Blaikie
1040475c84 Reword comment based on feedback by Duncan Sands. 
llvm-svn: 148809
 2012-01-24 16:18:30 +00:00
Chris Lattner
380a325520 basic instcombine support for CDS. 
llvm-svn: 148806
 2012-01-24 14:31:22 +00:00