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Commit Graph

35 Commits

Author SHA1 Message Date
Bill Wendling
e5af8b6e5c Add "mayHaveSideEffects" and "neverHasSideEffects" flags to some instructions. I
based what flag to set on whether it was already marked as
"isRematerializable". If there was a further check to determine if it's "really"
rematerializable, then I marked it as "mayHaveSideEffects" and created a check
in the X86 back-end similar to the remat one.

llvm-svn: 45132
2007-12-17 23:07:56 +00:00
Bill Wendling
b33d6155da LD_Fp64m should have "isRematerializable" set.
llvm-svn: 45128
2007-12-17 22:17:14 +00:00
Anton Korobeynikov
cd9b16df61 Implement codegen for flt_rounds on x86
llvm-svn: 44183
2007-11-16 01:31:51 +00:00
Arnold Schwaighofer
6bcd9e7ec2 Corrected many typing errors. And removed 'nest' parameter handling
for fastcc from X86CallingConv.td.  This means that nested functions
are not supported for calling convention 'fastcc'.

llvm-svn: 42934
2007-10-12 21:30:57 +00:00
Evan Cheng
f3c130a8b6 Enabling new condition code modeling scheme.
llvm-svn: 42459
2007-09-29 00:00:36 +00:00
Evan Cheng
a58633d67b New style x87 cmp instructions.
llvm-svn: 42312
2007-09-25 19:08:02 +00:00
Evan Cheng
36b3babfde Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
all the kinks are worked out.

llvm-svn: 42285
2007-09-25 01:57:46 +00:00
Dale Johannesen
ea6ffa0b36 Fix PR 1681. When X86 target uses +sse -sse2,
keep f32 in SSE registers and f64 in x87.  This
is effectively a new codegen mode.
Change addLegalFPImmediate to permit float and
double variants to do different things.
Adjust callers.

llvm-svn: 42246
2007-09-23 14:52:20 +00:00
Evan Cheng
13797e4a74 Add implicit def of EFLAGS on those instructions that may modify flags.
llvm-svn: 41962
2007-09-14 21:48:26 +00:00
Evan Cheng
b43255bc68 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
llvm-svn: 41863
2007-09-11 19:55:27 +00:00
Evan Cheng
527fe7ab57 Mark load instructions with isLoad = 1.
llvm-svn: 41595
2007-08-30 05:49:43 +00:00
Dale Johannesen
6b8e91e7e3 Long double patch 8 of N: make it partially work in
SSE mode (all but conversions <-> other FP types, I think):
>>Do not mark all-80-bit operations as "Requires[FPStack]"
(which really means "not SSE").
>>Refactor load-and-extend to facilitate this.
>>Update comments.
>>Handle long double in SSE when computing FP_REG_KILL.

llvm-svn: 40906
2007-08-07 20:29:26 +00:00
Dale Johannesen
2c35d56edd Long double patch 7 of N, unless I lost count:).
Last x87 bits for full functionality (not
thoroughly tested, and long doubles do not work
in SSE modes at all - use -mcpu=i486 for now)

llvm-svn: 40886
2007-08-07 01:17:37 +00:00
Dale Johannesen
3ea9879011 Get X86 long double calling convention to work
(on Darwin, anyway).  Fix some table omissions for
LD arithmetic.

llvm-svn: 40877
2007-08-06 21:31:06 +00:00
Dale Johannesen
a85f11d870 Long double patch 4 of N: initial x87 implementation.
Lots of problems yet but some simple things work.

llvm-svn: 40847
2007-08-05 18:49:15 +00:00
Dan Gohman
e3464e6bec Change the x86 assembly output to use tab characters to separate the
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.

llvm-svn: 40648
2007-07-31 20:11:57 +00:00
Evan Cheng
3493ec0ce1 Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )
llvm-svn: 40628
2007-07-31 08:04:03 +00:00
Evan Cheng
53cb03b583 No more noResults.
llvm-svn: 40132
2007-07-21 00:34:19 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Dale Johannesen
ecef839eaa Fix fp_constant_op failure.
llvm-svn: 38514
2007-07-10 21:53:30 +00:00
Dale Johannesen
7325a82196 fix 80 columnn violations, increasing the world's
pedantic satisfaction level.

llvm-svn: 38512
2007-07-10 20:53:41 +00:00
Dale Johannesen
9072b65b0b Refactor X87 instructions. As a side effect, all
their names are changed.

llvm-svn: 37876
2007-07-04 21:07:47 +00:00
Dale Johannesen
0db4ba9f8a Some spacing fixes. Cosmetic.
llvm-svn: 37853
2007-07-03 17:07:33 +00:00
Dale Johannesen
7af19491d3 Fix for PR 1505 (and 1489). Rewrite X87 register
model to include f32 variants.  Some factoring
improvments forthcoming.

llvm-svn: 37847
2007-07-03 00:53:03 +00:00
Dan Gohman
9cbc3fb1ab Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Dan Gohman
b60d8a92c9 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Evan Cheng
00a5cbf9e7 Mark re-materializable instructions.
llvm-svn: 35230
2007-03-21 00:16:56 +00:00
Evan Cheng
fe5bb5dbe6 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
Evan Cheng
d22f3dd3ed Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
Evan Cheng
d58d54cf3e Handle BUILD_VECTOR with all zero elements.
llvm-svn: 27056
2006-03-24 07:29:27 +00:00
Evan Cheng
8dd794ea70 Use the generic vector register classes VR64 / VR128 rather than V4F32,
V8I16, etc.

llvm-svn: 26838
2006-03-18 01:23:20 +00:00
Evan Cheng
ee1a44d5d8 Move some pattern fragments to the right files.
llvm-svn: 26831
2006-03-17 19:55:52 +00:00
Evan Cheng
8ab6294f94 One more round of reorg so sabre doesn't freak out. :-)
llvm-svn: 26303
2006-02-21 20:00:20 +00:00
Evan Cheng
223d3a073a Moving things to their proper places.
llvm-svn: 26301
2006-02-21 19:26:52 +00:00
Evan Cheng
fee17dfff8 Split instruction info into multiple files, one for each of x87, MMX, and SSE.
llvm-svn: 26300
2006-02-21 19:13:53 +00:00