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Commit Graph

142933 Commits

Author SHA1 Message Date
Chris Bieneman
42d02eba7a [ObjectYAML] Support for DWARF line tables
One more try... relanding r291541 with a fix to properly gate MaxOpsPerInst on DWARF version.

Description from r291541:

This patch re-lands r291470, which failed on Linux bots. The issue (I believe) was undefined behavior because the size of llvm::dwarf::LineNumberOps was not explcitly specified or consistently respected. The updated patch adds an explcit underlying type to the enum and preserves the size more correctly.

Original description:

This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly.

llvm-svn: 291546
2017-01-10 06:22:49 +00:00
Craig Topper
31783d0fe9 AMD family 17h (znver1) enablement
Summary:
This patch enables the following
1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu).
2. ISAs that are enabled for "znver1" architecture.
3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used.
4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17.
5. For the time being, it uses the btver2 scheduler model.
6. Test file is updated to check this flag.

This item is linked to clang review item https://reviews.llvm.org/D28018

Patch by Ganesh Gopalasubramanian

Reviewers: RKSimon, craig.topper

Subscribers: vprasad, RKSimon, ashutosh.nema, llvm-commits

Differential Revision: https://reviews.llvm.org/D28017

llvm-svn: 291543
2017-01-10 06:01:16 +00:00
Chris Bieneman
c9fd2572d1 Revert "[ObjectYAML] Support for DWARF line tables"
This reverts commit r291541.

Still failing on a bot:

http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/47224/steps/test_llvm/logs/stdio

llvm-svn: 291542
2017-01-10 05:31:23 +00:00
Chris Bieneman
71155a9019 [ObjectYAML] Support for DWARF line tables
This patch re-lands r291470, which failed on Linux bots. The issue (I believe) was undefined behavior because the size of llvm::dwarf::LineNumberOps was not explcitly specified or consistently respected. The updated patch adds an explcit underlying type to the enum and preserves the size more correctly.

Original description:

This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly.

llvm-svn: 291541
2017-01-10 05:25:24 +00:00
Dean Michael Berris
4c2f162d01 [XRay] Use regular expression for finding symbols
Un-break the test in Windows.

Follow-up on D24376.

llvm-svn: 291538
2017-01-10 04:32:34 +00:00
Craig Topper
69c334dc1c [X86] When lowering uniform shifts, use X86ISD::VZEXT instead of using a ZERO_EXTEND_VECTOR_INREG. If we emit the ZERO_EXTEND_VECTOR_INREG too late it doesn't get lowered properly and makes it through to isel and fails.
Fixes PR31593.

llvm-svn: 291535
2017-01-10 04:12:24 +00:00
Craig Topper
6f8393bb6b [DAGCombiner] Remove code for optimizing select (xor Cond, 0), X, Y -> select Cond, X, Y. Just let combine on the xor itself take care of it.
llvm-svn: 291534
2017-01-10 04:12:19 +00:00
Dean Michael Berris
e894c3760d [XRay] Fixup includes for modules build
Remove unnecessary system header include.

Follow-up to D24376.

llvm-svn: 291533
2017-01-10 03:21:54 +00:00
Xin Tong
c6873eab4c Fix a typo and also test a new machine for commit. NFC.
llvm-svn: 291532
2017-01-10 03:13:52 +00:00
Dean Michael Berris
4591f50356 [XRay] Don't include <unistd.h> unnecessarily
Follow-up to D24376.

llvm-svn: 291531
2017-01-10 02:51:13 +00:00
Serge Pavlov
dda5fe0374 [StructurizeCfg] Update dominator info.
In some cases StructurizeCfg updates root node, but dominator info
remains unchanges, it causes crash when expensive checks are enabled.
To cope with this problem a new method was added to DominatorTreeBase
that allows adding new root nodes, it is called in StructurizeCfg to
put dominator tree in sync.

This change fixes PR27488.

Differential Revision: https://reviews.llvm.org/D28114

llvm-svn: 291530
2017-01-10 02:50:47 +00:00
Dean Michael Berris
303663342f [XRay] Implement llvm-xray convert -- trace file conversion
This is the second part of a multi-part change to define additional
subcommands to the `llvm-xray` tool.

This change defines a conversion subcommand to take XRay log files, and
turns them from one format to another (binary or YAML). This currently
only supports the first version of the log file format, defined in the
compiler-rt runtime.

Depends on D21987.

Reviewers: dblaikie, echristo

Subscribers: mehdi_amini, dberris, beanz, llvm-commits

Differential Revision: https://reviews.llvm.org/D24376

llvm-svn: 291529
2017-01-10 02:38:11 +00:00
Evandro Menezes
b116545236 [CodeGen] Implement the SUnit::print() method
This method seems to have had a troubled life.  This patch proposes that it
replaces the recently added helper function dumpSUIdentifier.  This way, the
method can be used in other files using the SUnit class.

Differential revision: https://reviews.llvm.org/D28488

llvm-svn: 291520
2017-01-10 01:08:01 +00:00
Reid Kleckner
8cff07fe72 Try once again to fix the MSVC build of AlignedCharArrayUnion
It was complaining about ambiguity between llvm::detail and
llvm::support::detail:
  error C2872: 'detail': ambiguous symbol
  note: could be 'llvm::detail'
  note: or       'llvm::support::detail'

Standardize on llvm::support::detail to hide these symbols further.

llvm-svn: 291519
2017-01-10 01:05:33 +00:00
Mehdi Amini
4ea5ac2fde [ThinLTO] Hash more part of the config to build cache entries
This has been fixed in the "new" LTO API used by Gold/LLD, this is
fixing the same issue in the libLTO API used by ld64 (amongst other)

llvm-svn: 291518
2017-01-10 00:55:47 +00:00
Xin Tong
fceed62090 Add an assert for hasLoopInvariantOperands
Summary: Add an assert for hasLoopInvariantOperands

Reviewers: danielcdh, sanjoy

Subscribers: mzolotukhin, llvm-commits

Differential Revision: https://reviews.llvm.org/D28501

llvm-svn: 291516
2017-01-10 00:39:49 +00:00
Reid Kleckner
76cc76d15b Revert the attempt to optimize the constexpr functions. MSVC does not handle this yet
llvm-svn: 291515
2017-01-10 00:29:05 +00:00
Reid Kleckner
f2ab1ce169 Fix MSVC build of AlignedCharArrayUnion
Use constexpr recursion for alignof like we do for sizeof. Seems to work
with Clang and MSVC. Also, don't recurse twice to avoid slowdowns in
compilers that don't memoize constexpr results (Clang).

llvm-svn: 291514
2017-01-10 00:26:56 +00:00
Sean Callanan
f0c5814829 Lift the 10-type limit for AlignedCharArrayUnion
This patch uses C++11 parameter packs and constexpr functions
to allow AlignedCharArrayUnion to hold an arbitrary number of
types.

Differential Revision: https://reviews.llvm.org/D28429

llvm-svn: 291503
2017-01-09 23:23:25 +00:00
James Y Knight
9f28b0a9ad Commit a test for match-full-lines.
I unfortunately neglected to add it in r260540, but it has been
sitting in my working dir ever since. D'oh.

Modified to work with r290069, which made the CHECK patterns
themselves whitespace-sensitive as well, and remove the test added
then, as this tests both strict and non-strict modes.

llvm-svn: 291499
2017-01-09 23:11:25 +00:00
Dan Gohman
0bfa1b6007 [WebAssembly] Add return type annotations in fast isel.
llvm-svn: 291498
2017-01-09 23:09:38 +00:00
Rui Ueyama
614d1a6d81 TarWriter: Fix a bug in Ustar header.
If we split a filename into `Name` and `Prefix`, `Prefix` is at most
145 bytes. We had a bug that didn't split a path correctly. This bug
was pointed out by Rafael in the post commit review.

This patch adds a unit test for TarWriter to verify the fix.

llvm-svn: 291494
2017-01-09 22:55:00 +00:00
Eugene Zelenko
8ca47825f7 [NVPTX] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 291490
2017-01-09 22:16:51 +00:00
Simon Pilgrim
7a825e69b0 [X86][AVX512VL] Added AVX512VL to 128/256 bit vector shift tests
llvm-svn: 291488
2017-01-09 22:13:51 +00:00
Easwaran Raman
c5adec85bf Refactor inline threshold update code.
Functional change: Previously, if a callee is cold, we used ColdThreshold if it minimizes the existing threshold. This was irrespective of whether we were optimizing for minsize (-Oz) or not. But -Oz uses very low threshold to begin with and the inlining with -Oz is expected to be tuned for lowering code size, so there is no good reason to set an even lower threshold for cold callees. We now lower the threshold for cold callees only when -Oz is not used. For default values of -inlinethreshold and -inlinecold-threshold, this change has no effect and this simplifies the code.

NFC changes: Group all threshold updates that are guarded by !Caller->optForMinSize() and within that group threshold updates that require profile summary info.

Differential revision: https://reviews.llvm.org/D28369

llvm-svn: 291487
2017-01-09 21:56:26 +00:00
Davide Italiano
bc2b08fb6d [SimplifyLibCalls] pow(x, -0.5) -> 1.0 / sqrt(x).
Differential Revision:  https://reviews.llvm.org/D28479

llvm-svn: 291486
2017-01-09 21:55:23 +00:00
Rafael Espindola
bdc220866d Support outputting to /dev/null.
When writing to a non regular file we cannot rename to it. Since we
have to write, we may as well create a temporary file to avoid trying
to create an unique file in /dev when trying to write to /dev/null.

llvm-svn: 291485
2017-01-09 21:52:35 +00:00
Matthias Braun
537f364e9a PeepholeOptimizer: Do not replace SubregToReg(bitcast like)
While we can usually replace bitcast like instructions
(MachineInstr::isBitcast()) with a COPY this is not legal if any of the
users uses SUBREG_TO_REG to assert the upper bits of the result are
zero.

Differential Revision: https://reviews.llvm.org/D28474

llvm-svn: 291483
2017-01-09 21:38:17 +00:00
Matthias Braun
f1a5cb7582 Drive by typo fix
llvm-svn: 291482
2017-01-09 21:38:14 +00:00
Matthias Braun
ea1c543874 MachineInstr: Print name for subreg index in SUBREG_TO_REG
SUBREG_TO_REG takes a subregister index as 3rd operand, print the name
instead of a number. We already do the same for INSERT_SUBREG and
REG_SEQUENCE.

llvm-svn: 291481
2017-01-09 21:38:10 +00:00
Rui Ueyama
9e72a594f6 TarWriter: Set "00" to Ustar version field.
Most (maybe all?) tar commands can handle tar archives with blank
version fields, but POSIX requires "00" to be set to the field, so
doing it is good for compliance.

llvm-svn: 291479
2017-01-09 21:20:42 +00:00
Michael Kuperstein
46f8da70bd Revert r291092 because it introduces a crash.
See PR31589 for details.

llvm-svn: 291478
2017-01-09 21:04:46 +00:00
Vyacheslav Klochkov
173ab70432 X86-specific path: Implemented the fusing of MUL+ADDSUB to FMADDSUB.
Differential Revision: https://reviews.llvm.org/D28087

llvm-svn: 291473
2017-01-09 20:26:17 +00:00
Sanjay Patel
3ac455e916 [InstCombine] add test to show missed fold using llvm.assume; NFC
llvm-svn: 291472
2017-01-09 20:18:30 +00:00
Chris Bieneman
1028eb06fe Revert "[ObjectYAML] Support for DWARF line tables"
This reverts commit r291470 due to failing bots:

http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/47209/steps/test_llvm/logs/stdio

llvm-svn: 291471
2017-01-09 20:04:55 +00:00
Chris Bieneman
458297f73c [ObjectYAML] Support for DWARF line tables
This patch adds support for the DWARF debug_lines section. The line table state machine opcodes are preserved, so this can be used to test the state machine evaluation directly.

llvm-svn: 291470
2017-01-09 20:01:37 +00:00
Sanjay Patel
a6e75ebdd0 [InstCombine] regenerate checks; NFC
llvm-svn: 291469
2017-01-09 19:43:26 +00:00
Sanjay Patel
dccdc2e25a [ValueTracking] regenerate checks; NFC
llvm-svn: 291468
2017-01-09 19:31:20 +00:00
Daniel Berlin
031f4f3070 Fix function regex in update_tests so it can handle {}'s in function args
llvm-svn: 291467
2017-01-09 19:24:19 +00:00
Sanjay Patel
02b3fa484b [InstCombine] regenerate checks; NFC
llvm-svn: 291464
2017-01-09 19:18:46 +00:00
Sanjay Patel
ac0df93034 [InstCombine] remove unnecessary attribute comments from test files; NFC
llvm-svn: 291463
2017-01-09 19:13:38 +00:00
Matthew Simpson
d47c4174f6 [LV] Fix-up external IV users after updating dominator tree
This patch delays the fix-up step for external induction variable users until
after the dominator tree has been properly updated. This should fix PR30742.
The SCEVExpander in InductionDescriptor::transform can generate code in the
wrong location if the dominator tree is not up-to-date. We should work towards
keeping the dominator tree up-to-date throughout the transformation.

Reference: https://llvm.org/bugs/show_bug.cgi?id=30742
Differential Revision: https://reviews.llvm.org/D28168

llvm-svn: 291462
2017-01-09 19:05:29 +00:00
Matt Arsenault
4872e0b42c AMDGPU: Add Assert[SZ]Ext during argument load creation
For i16 zeroext arguments when i16 was a legal type, the
known bits information from the truncate was lost. Insert
a zeroext so the known bits optimizations work with the 32-bit
loads.

Fixes code quality regressions vs. SI in min.ll test.

llvm-svn: 291461
2017-01-09 18:52:39 +00:00
Matt Arsenault
1f93f5639f Reapply r291025 ("AMDGPU: Remove unneccessary intermediate vector")
llvm-svn: 291460
2017-01-09 18:44:11 +00:00
Xin Tong
9aa14f6869 Intrinsic::Bitreverse is safe to speculate
Summary: Intrinsic::Bitreverse is safe to speculate

Reviewers: hfinkel, mkuper, arsenm, jmolloy

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D28471

llvm-svn: 291456
2017-01-09 17:57:08 +00:00
Sumanth Gundapaneni
c5b243c780 In the below scenario, we must be able to skip the a DBG_VALUE instruction and
remove the dead store.

%vreg0<def> = L2_loadri_io <fi#15>, 0; mem:LD4[%dataF](align=4)
DBG_VALUE %vreg0, %noreg, !"dataF", <!184>; IntRegs:%vreg0 
S2_storeri_io <fi#15>, 0, %vreg0; mem:ST4[%dataF]

In reality, this kind of stores are eliminated before Stack Slot Coloring pass,
possibly in instruction lowering

Differential Revision: https://reviews.llvm.org/D26616

llvm-svn: 291455
2017-01-09 17:45:02 +00:00
Simon Pilgrim
3f38e64dde [X86][AVX512] Enable v16i8/v32i8 vector shifts to use an extend+shift+truncate pattern.
Use the existing AVX2 v8i16 vector shift lowering for v16i8 (extending to v16i32) on AVX512 targets and v32i8 (extending to v32i16) on AVX512BW targets.

Cost model updates to follow.

llvm-svn: 291451
2017-01-09 17:20:03 +00:00
Sanjay Patel
5937e81c61 fix comment typos; NFC
llvm-svn: 291447
2017-01-09 16:27:56 +00:00
Simon Pilgrim
db020b791f [X86][AVX512DQ] Enable v16i16 vector shifts to use an extend+shift+truncate pattern.
Use the existing AVX2 v8i16 vector shift lowering for v16i16 on AVX512 targets (AVX512BW will have already have lowered with vpsravw).

Cost model updates to follow.

llvm-svn: 291445
2017-01-09 15:15:45 +00:00
Simon Pilgrim
27ef07a5f3 [X86][AVX512DQ] Added AVX512DQ to 128/256 bit vector shift tests
llvm-svn: 291444
2017-01-09 14:36:09 +00:00