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25 Commits

Author SHA1 Message Date
Kristof Beyls
a686678676 Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions. 
The Printer will now print instructions with the correct alignment specifier syntax, like
    vld1.8  {d16}, [r0:64]

llvm-svn: 175884
 2013-02-22 10:01:33 +00:00
Jakob Stoklund Olesen
de21509dcd Also set addrmode6 alignment when align==size. 
Previously, we were only setting the alignment bits on over-aligned
loads and stores.

llvm-svn: 143160
 2011-10-27 22:39:16 +00:00
Jakob Stoklund Olesen
16f11212fc Teach LiveInterval::isZeroLength about null SlotIndexes. 
When instructions are deleted, they leave tombstone SlotIndex entries.
The isZeroLength method should ignore these null indexes.

This causes RABasic to sometimes spill a callee-saved register in the
abi-isel.ll test, so don't run that test with -regalloc=basic.  Prioritizing
register allocation according to spill weight can cause more registers to be
used.

llvm-svn: 131436
 2011-05-16 23:50:05 +00:00
Jakob Stoklund Olesen
4755a27704 Fix a bunch of ARM tests to be register allocation independent. 
llvm-svn: 130800
 2011-05-03 22:31:21 +00:00
Evan Cheng
56c151cba9 Do not lose mem_operands while lowering VLD / VST intrinsics. 
llvm-svn: 129738
 2011-04-19 00:04:03 +00:00
Jakob Stoklund Olesen
33f01d005c Fix ARM tests to be register allocator independent. 
llvm-svn: 128680
 2011-03-31 22:14:03 +00:00
Bob Wilson
65f4a70b82 Add codegen support for using post-increment NEON load/store instructions. 
The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using
post-increment versions, but all the rest of the NEON load/store instructions
should be handled now.

llvm-svn: 125014
 2011-02-07 17:43:21 +00:00
Bob Wilson
e06f6eabe7 Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation. 
Radar 8776599

llvm-svn: 122018
 2010-12-17 01:21:12 +00:00
Bob Wilson
d30768fe3e Add float patterns for Neon vld1-lane/dup and vst1-lane operations. 
llvm-svn: 121583
 2010-12-10 22:13:32 +00:00
Bob Wilson
5ff13f9d5c Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions. 
Alignments smaller than the total size of the memory being loaded or stored,
unless the alignment is 8 bytes, are not allowed.  Add tests for this, too.

llvm-svn: 121506
 2010-12-10 19:37:42 +00:00
Bob Wilson
f44e708279 Add codegen patterns for VST1-lane instructions. Radar 8599955. 
llvm-svn: 118176
 2010-11-03 16:24:53 +00:00
Bob Wilson
411b511ac0 Add support for alignment operands on VLD1-lane instructions. 
This is another part of the fix for Radar 8599955.

llvm-svn: 117976
 2010-11-01 23:40:51 +00:00
Bob Wilson
8f0cf81f09 Add VLD1-lane testcases for quad-register types. 
llvm-svn: 117975
 2010-11-01 23:40:46 +00:00
Bob Wilson
b6bc135df8 Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 117964
 2010-11-01 22:04:05 +00:00
Bob Wilson
c3fb4427f4 Support alignment for NEON vld-lane and vst-lane instructions. 
llvm-svn: 116776
 2010-10-19 00:16:32 +00:00
Bob Wilson
c01101e76c Add alignment arguments to all the NEON load/store intrinsics. 
Update all the tests using those intrinsics and add support for
auto-upgrading bitcode files with the old versions of the intrinsics.

llvm-svn: 112271
 2010-08-27 17:13:24 +00:00
Dan Gohman
c024fd43c9 Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul, 
when the type is floating-point.

llvm-svn: 102969
 2010-05-03 22:36:46 +00:00
Bob Wilson
2e6cd50a50 Fix tests for Neon load/store intrinsics to match the i8* types expected by 
the intrinsics.  The reason for those i8* types is that the intrinsics are
overloaded on the vector type and we don't have a way to declare an intrinsic
where one argument is an overloaded vector type and another argument is a
pointer to the vector element type.  The bitcasts added here will match what
the frontend will typically generate when these intrinsics are used.

llvm-svn: 101840
 2010-04-20 00:17:16 +00:00
Bob Wilson
5b96a53ffe Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
 2009-10-08 22:53:57 +00:00
Bob Wilson
7209d78713 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
llvm-svn: 83585
 2009-10-08 22:27:33 +00:00
Bob Wilson
3a55fe2105 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
llvm-svn: 83568
 2009-10-08 18:56:10 +00:00
Bob Wilson
636d635cc1 Update NEON struct names to match llvm-gcc changes. 
(This is not required for correctness but might help with sanity.)

llvm-svn: 83415
 2009-10-06 21:16:19 +00:00
Dan Gohman
142428ce64 Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81293
 2009-09-09 00:09:15 +00:00
Bob Wilson
75b2b04e1e Fix incorrect declarations of intrinsics in this test. 
llvm-svn: 80705
 2009-09-01 18:50:43 +00:00
Bob Wilson
d638cc8869 Add test for vld{234}_lane instructions. 
llvm-svn: 80658
 2009-09-01 04:27:10 +00:00