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Commit Graph

211597 Commits

Author SHA1 Message Date
Heejin Ahn
430a6166c8 [WebAssembly] Misc. fixes in cfg-stackify-eh.ll
- Fix `preds` comments
- Delete nonexistent attributes in instructions (They used to exist in
  clang-generated files, but I removed most of them to make the tests
  tidy. We have only `nounwind` and `noreturn` left here.)
- Add missing `Function Attrs` comments in function declarations

 None of these affect test function semantics or test results for now.

Reviewed By: tlively

Differential Revision: https://reviews.llvm.org/D97179
2021-02-22 11:49:33 -08:00
Petr Hosek
f79977fb72 Revert "[InstrProfiling] Use ELF section groups for counters, data and values"
This reverts commits:
5ca21175e09fc7fb7dcaee9ebd6782d122a5688f
97184ab99c46e35ae94f828ee90f5d6af2c47e11

The instrprof-gc-sections.c is failing on AArch64 LLD bot.
2021-02-22 11:13:55 -08:00
Simon Pilgrim
4efe57ac5c [KnownBits] Pull out repeated getMinValue() calls from shift analysis. NFCI. 2021-02-22 18:41:01 +00:00
Leonard Chan
1cfc220073 [llvm][Bitcode] Add bitcode reader/writer for DSOLocalEquivalent
This is necessary for compilation with [thin]lto.

Differential Revision: https://reviews.llvm.org/D96170
2021-02-22 10:37:57 -08:00
Jessica Paquette
f6b58c5553 [AArch64][GlobalISel] Emit G_ASSERT_SEXT for SExt parameters in CallLowering
Similar to how we emit G_ASSERT_ZEXT when we have CCValAssign::LocInfo::ZExt.

This will allow us to combine away some redundant sign extends.

Example: https://godbolt.org/z/cTbKvr

Differential Revision: https://reviews.llvm.org/D96915
2021-02-22 10:14:43 -08:00
Florian Hahn
bedc3aff1d [ConstraintElimination] Use unsigned > 0 instead of != 0.
ICMP_NE predicates cannot be directly represented as constraint. But we
can use ICMP_UGT instead ICMP_NE for %x != 0.

See https://alive2.llvm.org/ce/z/XlLCsW
2021-02-22 17:54:36 +00:00
Craig Topper
88f3c50288 [RISCV] Custom isel the rest of the vector load/store intrinsics.
A previous patch moved the index versions. This moves the rest.
I also removed the custom lowering for VLEFF since we can now
do everything directly in the isel handling.

I had to update getLMUL to handle mask registers to index the
pseudo table correctly for VLE1/VSE1.

This is good for another 15K reduction in llc size.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97097
2021-02-22 09:53:46 -08:00
Nikita Popov
a86f098589 [MemCpyOpt] Fix handling of readnone byval arguments
If the call is readnone, then there may not be any MemoryAccess
associated with the call. Bail out in that case.

This fixes the issue reported at
https://reviews.llvm.org/D94376#2578312.
2021-02-22 18:48:31 +01:00
Nikita Popov
659da52985 [JumpThreading] Clone noalias.scope.decl when threading blocks
When cloning instructions during jump threading, also clone and
adapt any declared scopes. This is primarily important when
threading loop exits, because we'll end up with two dominating
scope declarations in that case (at least after additional loop
rotation). This addresses a loose thread from
https://reviews.llvm.org/rG2556b413a7b8#975012.

Differential Revision: https://reviews.llvm.org/D97154
2021-02-22 18:35:30 +01:00
Florian Hahn
917be2ab77 [ConstraintElimination] Add initial ICMP_NE test cases. 2021-02-22 17:11:04 +00:00
Simon Pilgrim
9b05a382fc [InstSimplify] Cleanup out-of-range shift amount handling.
Use APInt::uge() direct instead of getLimitedValue().

Use KnownBits::getMinValue() to make the bounds check more obvious.
2021-02-22 17:00:49 +00:00
Florian Hahn
31c1e8a6c3 [LV] Directly use incoming value for single VPBlendRecipes.
VPBlendRecipes with single incoming (value, mask) pair are no-ops. Use
the incoming value directly.
2021-02-22 16:10:08 +00:00
Sanjay Patel
d83af3b33a [LangRef] fix typo in assume bundle description; NFC 2021-02-22 09:30:49 -05:00
Simon Pilgrim
cbb40421c9 [InstCombine] Add PR45977 test coverage 2021-02-22 12:20:35 +00:00
Ryan Santhiraraja
47e298740e [AArch64] Adding SHA3 Intrinsics support
This patch adds the following SHA3 Intrinsics:
        vsha512hq_u64,
        vsha512h2q_u64,
        vsha512su0q_u64,
        vsha512su1q_u64
        veor3q_u8
        veor3q_u16
        veor3q_u32
        veor3q_u64
        veor3q_s8
        veor3q_s16
        veor3q_s32
        veor3q_s64
        vrax1q_u64
        vxarq_u64
        vbcaxq_u8
        vbcaxq_u16
        vbcaxq_u32
        vbcaxq_u64
        vbcaxq_s8
        vbcaxq_s16
        vbcaxq_s32
        vbcaxq_s64

    Note need to include +sha3 and +crypto when building from the front-end

Reviewed By: DavidSpickett

Differential Revision: https://reviews.llvm.org/D96381
2021-02-22 12:09:20 +00:00
Dmitry Preobrazhensky
d8fddd2027 [AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3
Enabled "bound_ctrl:1" and disabled "bound_ctrl:-1" syntax.
Corrected printer to output "bound_ctrl:1" instead of "bound_ctrl:0".
See bug 35397 for detailed issue description.

Differential Revision: https://reviews.llvm.org/D97048
2021-02-22 14:59:40 +03:00
LLVM GN Syncbot
156b27c96a [gn build] Port 7dc7f0c2ecc0 2021-02-22 11:35:19 +00:00
Nashe Mncube
78595a3c7a [llvm-link] fix IRMover returning wrong modified vector type
Modified scalable vector types weren't correctly returned at link-time.
The previous behaviour was a FixedVectorType was constructed
when expecting a ScalableVectorType. This commit has added a regression
test which re-creates the failure as well as a fix.

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D96953
2021-02-22 11:29:42 +00:00
LLVM GN Syncbot
d689ba9142 [gn build] Port 6e3071007b4c 2021-02-22 10:35:33 +00:00
Florian Hahn
fbfddf31c3 [VPlan] Skip VPWidenPHIRecipe in VPInterleavedACcessInfo.
Update unit tests that did not expect VPWidenPHIRecipes after
15a74b64dfa9.
2021-02-22 10:35:09 +00:00
Simon Pilgrim
da189b613b [InstCombine] Add smulo NumSignBits test from D97170 2021-02-22 10:25:13 +00:00
David Green
750cd1a3fb [ARM] Remove dead lowering code. NFC
Remove the unnecessary code from 21a4faab60c34b8a8c4d09, left over from
a different way of lowering.
2021-02-22 10:07:53 +00:00
Florian Hahn
4aa2677e39 [VPlan] Manage pairs of incoming (VPValue, VPBB) in VPWidenPHIRecipe.
This patch extends VPWidenPHIRecipe to manage pairs of incoming
(VPValue, VPBasicBlock) in the VPlan native path. This is made possible
because we now directly manage defined VPValues for recipes.

By keeping both the incoming value and block in the recipe directly,
code-generation in the VPlan native path becomes independent of the
predecessor ordering when fixing up non-induction phis, which currently
can cause crashes in the VPlan native path.

This fixes PR45958.

Reviewed By: sguggill

Differential Revision: https://reviews.llvm.org/D96773
2021-02-22 09:44:25 +00:00
David Green
f7bf0cce57 [ARM] Move double vector insert patterns using vins to DAG combine
This removes the existing patterns for inserting two lanes into an
f16/i16 vector register using VINS, instead using a DAG combine to
pattern match the same code sequences. The tablegen patterns were
already on the large side (foreach LANE = [0, 2, 4, 6]) and were not
handling all the cases they could. Moving that to a DAG combine, whilst
not less code, allows us to better control and expand the selection of
VINSs. Additionally this allows us to remove the AddedComplexity on
VCVTT.

The extra trick that this has learned in the process is to move two
adjacent lanes using a single f32 vmov, allowing some extra
inefficiencies to be removed.

Differenial Revision: https://reviews.llvm.org/D96876
2021-02-22 09:29:47 +00:00
Andy Wingo
4c62f39d2f [WebAssembly] call_indirect issues table number relocs
If the reference-types feature is enabled, call_indirect will explicitly
reference its corresponding function table via `TABLE_NUMBER`
relocations against a table symbol.

Also, as before, address-taken functions can also cause the function
table to be created, only with reference-types they additionally cause a
symbol table entry to be emitted.

We abuse the used-in-reloc flag on symbols to indicate which tables
should end up in the symbol table.  We do this because unfortunately
older wasm-ld will carp if it see a table symbol.

Differential Revision: https://reviews.llvm.org/D90948
2021-02-22 10:13:36 +01:00
Djordje Todorovic
e2f803118c [NFC][llvm-dwarfdump] Don't calculate unnecessary stats
Small optimization of the code -- No need to calculate any stats
for NULL nodes, and also no need to call the collectStatsForDie()
if it is the CU itself.

Differential Revision: https://reviews.llvm.org/D96871
2021-02-22 00:31:29 -08:00
Amara Emerson
584c3e72c8 [AArch64][GlobalISel] Fix <16 x s8> G_DUP regbankselect to assign source to gpr.
We can only select this type if the source is on GPR, not FPR.
2021-02-21 21:17:29 -08:00
Kazu Hirata
38cc9ea5cc [CodeGen] Use range-based for loops (NFC) 2021-02-21 19:58:07 -08:00
Kazu Hirata
64140f094e [llvm] Fix header guards (NFC)
Identified with llvm-header-guard.
2021-02-21 19:58:05 -08:00
Kazu Hirata
83ddc1026f [Analysis] Use ListSeparator (NFC) 2021-02-21 19:58:04 -08:00
Petr Hosek
0968fe7374 [InstrProfiling] Use ELF section groups for counters, data and values
__start_/__stop_ references retain C identifier name sections such as
__llvm_prf_*. Putting these into a section group disables this logic.

The ELF section group semantics ensures that group members are retained
or discarded as a unit. When a function symbol is discarded, this allows
allows linker to discard counters, data and values associated with that
function symbol as well.

Note that `noduplicates` COMDAT is lowered to zero-flag section group in
ELF. We only set this for functions that aren't already in a COMDAT and
for those that don't have available_externally linkage since we already
use regular COMDAT groups for those.

Differential Revision: https://reviews.llvm.org/D96757
2021-02-21 16:13:06 -08:00
Craig Topper
eeb855b166 [KnownBits][RISCV] Improve known bits for srem.
The result must be less than or equal to the LHS side, so any
leading zeros in the left hand side must also exist in the result.
This is stronger than the previous behavior where we only considered
the sign bit being 0.

The affected test case used the sign bit being known 0 to change
a sign extend to a zero extend pre type legalization. After type
legalization the types were promoted to i64, but we no longer
knew bit 31 was zero. This shifts are are the equivalent of an
AND with 0xffffffff or zext_inreg X, i32. This patch allows us to
see that bit 31 is zero and remove the shifts.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97124
2021-02-21 14:48:29 -08:00
Simon Pilgrim
0606b4495b [X86] Add vector support to sub(C1, xor(X, C2)) -> add(xor(X, ~C2), C1+1) fold. 2021-02-21 21:51:27 +00:00
Simon Pilgrim
b7c3719b71 [X86] Replace explicit constant handling in sub(C1, xor(X, C2)) -> add(xor(X, ~C2), C1+1) fold. NFCI.
NFC cleanup before adding vector support - rely on the SelectionDAG to handle everything for us.
2021-02-21 21:40:32 +00:00
Simon Pilgrim
69e2e277dc [X86] Regenerate sub.ll test 2021-02-21 21:25:26 +00:00
Simon Pilgrim
72833ddc08 [X86] Add 'sub C1, (xor X, C1) -> add (xor X, ~C2), C1+1' tests
This is also in sub.ll but that's for a specific i686 pattern - this adds x86_64 and vector tests
2021-02-21 21:19:39 +00:00
Simon Pilgrim
14c2353c18 [X86] Add common CHECK check-prefix to sub combine tests 2021-02-21 21:10:52 +00:00
Craig Topper
43d920b6bd [SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM.
This also removes a pattern from RISCV that is no longer needed
since the sexti32 on the LHS of the srem in the pattern implies
the result is sign extended so the sign_extend_inreg should be
removed in DAG combine now.

Reviewed By: luismarques, RKSimon

Differential Revision: https://reviews.llvm.org/D97133
2021-02-21 11:13:36 -08:00
Simon Pilgrim
19966fb2bc [X86][AVX] canonicalizeLaneShuffleWithRepeatedOps - remove unnecessary BITCASTs.
In conjunction with the 'vperm2x128(bitcast(x),bitcast(y),c) -> bitcast(vperm2x128(x,y,c))' fold in combineTargetShuffle, this should remove any unnecessary bitcasts around vperm2x128 lane shuffles.
2021-02-21 18:40:32 +00:00
madhur13490
c582e6ee1c [NFC] Remove redundant word in comment
Differential Revision: https://reviews.llvm.org/D97157
2021-02-21 18:04:20 +00:00
Nikita Popov
ce78a3156f [Loads] Add optimized FindAvailableLoadedValue() overload (NFCI)
FindAvailableLoadedValue() accepts an iterator by reference. If no
available value is found, then the iterator will either be left
at a clobbering instruction or the beginning of the basic block.
This allows using FindAvailableLoadedValue() across multiple blocks.

If this functionality is not needed, as is the case in InstCombine,
then we can use a much more efficient implementation: First try
to find an available value, and only perform clobber checks if
we actually found one. As this function only looks at a very small
number of instructions (6 by default) and usually doesn't find an
available value, this saves many expensive alias analysis queries.
2021-02-21 18:42:56 +01:00
Sanjay Patel
3d791c7666 [IR] restrict vector reduction intrinsic types
The arguments in all cases should be vectors of exactly one of integer or FP.

All of the tests currently pass the verifier because we check for any vector
type regardless of the type of reduction.
This obviously can't work if we mix up integer and FP, and based on current
LangRef text it was not intended to work for pointers either.

The pointer case from https://llvm.org/PR49215 is what led me here. That
example was avoided with 5b250a27ec.

Differential Revision: https://reviews.llvm.org/D96904
2021-02-21 12:37:00 -05:00
Nikita Popov
80c50652f7 [Loads] Extract helper frunction for available load/store (NFC)
This contains the logic for extracting an available load/store
from a given instruction, to be reused in a following patch.
2021-02-21 18:24:58 +01:00
Kristina Bessonova
84eff7b913 [ThinLTO] Fix import of multiply defined global variables
Currently, if there is a module that contains a strong definition of
a global variable and a module that has both a weak definition for
the same global and a reference to it, it may result in an undefined symbol error
while linking with ThinLTO.

It happens because:
* the strong definition become internal because it is read-only and can be imported;
* the weak definition gets replaced by a declaration because it's non-prevailing;
* the strong definition failed to be imported because the destination module
  already contains another definition of the global yet this def is non-prevailing.

The patch adds a check to computeImportForReferencedGlobals() that allows
considering a global variable for being imported even if the module contains
a definition of it in the case this def has an interposable linkage type.

Note that currently the check is based only on the linkage type
(and this seems to be enough at the moment), but it might be worth to account
the information whether the def is prevailing or not.

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D95943
2021-02-21 18:34:12 +02:00
Simon Pilgrim
b2f83027f4 [DAG] Match USUBSAT patterns through zext/trunc
This patch handles usubsat patterns hidden through zext/trunc and uses the getTruncatedUSUBSAT helper to determine if the USUBSAT can be correctly performed in the truncated form:

zext(x) >= y ? x - trunc(y) : 0 --> usubsat(x,trunc(umin(y,SatLimit)))
zext(x) >  y ? x - trunc(y) : 0 --> usubsat(x,trunc(umin(y,SatLimit)))

Based on original examples:

void foo(unsigned short *p, int max, int n) {
    int i;
    unsigned m;
    for (i = 0; i < n; i++) {
        m = *--p;
        *p = (unsigned short)(m >= max ? m-max : 0);
    }
}

Differential Revision: https://reviews.llvm.org/D25987
2021-02-21 15:26:54 +00:00
Simon Pilgrim
dd799f16a2 [X86][AVX] Fold concat(extract_subvector(v0,c0), extract_subvector(v1,c1)) -> vperm2x128
Fixes regression exposed by removing bitcasts across logic-ops in D96206.

Differential Revision: https://reviews.llvm.org/D96206
2021-02-21 14:50:43 +00:00
Simon Pilgrim
1640de7ef3 [X86] Fold bitcast(logic(bitcast(X), Y)) --> logic'(X, bitcast(Y)) for int-int bitcasts
Extend the existing combine that handles bitcasting for fp-logic ops to also help remove logic ops across bitcasts to/from the same integer types.

This helps improve AVX512 predicate handling for D/Q logic ops and also allows DAGCombine's scalarizeExtractedBinop to remove some annoying gpr->simd->gpr transfers.

The concat_vectors regression in pr40891.ll will be addressed in a followup commit on this patch.

Differential Revision: https://reviews.llvm.org/D96206
2021-02-21 14:40:54 +00:00
Craig Topper
f5a3ff6669 [RISCV] Add test cases for add/sub/mul overflow intrinsics. NFC
Largely copied from AArch64/arm64-xaluo.ll
2021-02-21 00:21:20 -08:00
Kazu Hirata
5d6ed75196 [CodeGen] Use range-based for loops (NFC) 2021-02-20 21:46:02 -08:00
Kazu Hirata
ad69418507 [TableGen] Use ListSeparator (NFC) 2021-02-20 21:46:01 -08:00