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19254 Commits

Author SHA1 Message Date
Jim Grosbach
44047da675 ARM Darwin default relocation model is PIC. 
This matches clang, so default options in llc and friends are now closer to
clang's defaults.

llvm-svn: 140863
 2011-09-30 17:41:35 +00:00
Akira Hatanaka
6f3cfcdb95 isCommutable should be 0 for DSUBu. 
llvm-svn: 140862
 2011-09-30 17:26:36 +00:00
Jim Grosbach
5b31ef50f5 ARM Fixup valus for movt/movw are for the whole value. 
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.

rdar://9653509

llvm-svn: 140861
 2011-09-30 17:23:05 +00:00
Justin Holewinski
f088db2687 PTX: Various stylistic and code readability changes recommended by Jim Grosbach. 
llvm-svn: 140855
 2011-09-30 14:36:36 +00:00
Justin Holewinski
2a5786383a PTX: Add programmable rounding mode specifier for int <-> fp conversion instrs. 
Also take this opportunity to clean up the rounding mode pass.

llvm-svn: 140854
 2011-09-30 13:46:52 +00:00
Justin Holewinski
f86bf451e4 PTX: Attempt to cleanup/unify the handling of FP rounding modes. This requires 
us to manually provide Pat<> definitions for all FP instruction patterns.

llvm-svn: 140849
 2011-09-30 12:54:43 +00:00
Akira Hatanaka
dcd69c2e07 Mips64 shift instructions. 
llvm-svn: 140841
 2011-09-30 03:18:46 +00:00
Akira Hatanaka
4bdb4b1958 Mips64 arithmetic and logical instructions with one source register and 
immediate.

llvm-svn: 140839
 2011-09-30 02:08:54 +00:00
Jim Grosbach
d94ffffc87 ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834
 2011-09-30 00:50:06 +00:00
Akira Hatanaka
50a4f6d570 Fill delay slot with useful instructions. Modified from Sparc's version of delay 
slot filler.

Patch by Reed Kotler at Mips Technologies.

llvm-svn: 140825
 2011-09-29 23:52:13 +00:00
Bill Wendling
ee48218f94 Create a machine basic block in the constant pool and retrieve the symbol for an MBB. 
llvm-svn: 140824
 2011-09-29 23:50:42 +00:00
Bill Wendling
de36760902 Support creating a constant pool value for a machine basic block. 
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.

llvm-svn: 140823
 2011-09-29 23:48:44 +00:00
Akira Hatanaka
70be05d5d0 Mips64 arithmetic and logical instructions with two source registers. 
llvm-svn: 140806
 2011-09-29 20:37:56 +00:00
Eli Friedman
ac33381aa1 Clean up uses of switch instructions so they are not dependent on the operand ordering. Patch by Stepan Dyatkovskiy. 
llvm-svn: 140803
 2011-09-29 20:21:17 +00:00
Justin Holewinski
e429b56306 PTX: Fix broken shared library build 
llvm-svn: 140783
 2011-09-29 14:25:48 +00:00
Jakob Stoklund Olesen
76da38e8e8 Expand the x86 V_SET0* pseudos right after register allocation. 
This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.

llvm-svn: 140776
 2011-09-29 05:10:54 +00:00
NAKAMURA Takumi
f82662e1f6 Target/ARM: Unbreak! CMake! Build! 
llvm-svn: 140774
 2011-09-29 03:32:49 +00:00
Jakob Stoklund Olesen
a2a0ba4d56 Delete NEONMoveFix, now unused. 
llvm-svn: 140773
 2011-09-29 02:56:45 +00:00
Jakob Stoklund Olesen
cfd5280df5 Use ExecutionDepsFix instead of NEONMoveFix. 
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.

llvm-svn: 140772
 2011-09-29 02:48:41 +00:00
Bill Wendling
cc7e50a465 Move to ISelLowering. 
llvm-svn: 140754
 2011-09-29 01:13:55 +00:00
Justin Holewinski
4966d44b44 PTX: Add new patterns for bitconvert and any_extend 
llvm-svn: 140753
 2011-09-29 01:13:12 +00:00
Jakob Stoklund Olesen
6cb1647b24 Revert r140731, "Define classes for unary and binary FP instructions and use them to define" 
It broke the unit tests.  Please reapply with tests fixed.

llvm-svn: 140735
 2011-09-28 23:59:28 +00:00
Evan Cheng
1e53900b70 Tighten a ARM dag combine condition to avoid an identity transformation, which 
ends up introducing a cycle in the DAG.

rdar://10196296

llvm-svn: 140733
 2011-09-28 23:16:31 +00:00
Akira Hatanaka
be2c5236ec Define classes for unary and binary FP instructions and use them to define 
multiclasses.

llvm-svn: 140731
 2011-09-28 21:58:01 +00:00
Eli Friedman
81fc13efd2 PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them. 
llvm-svn: 140723
 2011-09-28 21:00:25 +00:00
Bill Wendling
2400aacfb7 Perform the lowering only if there are invokes. 
llvm-svn: 140719
 2011-09-28 20:29:45 +00:00
Bill Wendling
37088b0660 Ahem...actually *add* the ARMSjLjLowering pass to the pass manager. 
llvm-svn: 140718
 2011-09-28 20:29:28 +00:00
Justin Holewinski
f88506ac8d PTX: Fix alignment logic 
llvm-svn: 140709
 2011-09-28 18:24:58 +00:00
Akira Hatanaka
0510b9d75b Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit. 
llvm-svn: 140705
 2011-09-28 18:11:19 +00:00
Akira Hatanaka
fa83d9ff16 Remove definitions of branch-on-FP-likely instructions. They are deprecated. 
llvm-svn: 140704
 2011-09-28 17:56:55 +00:00
Akira Hatanaka
2d08a7fd85 Mips64 predicate definitions. Patch by Liu. 
llvm-svn: 140703
 2011-09-28 17:50:27 +00:00
Justin Holewinski
a68272b38f PTX: MC-ize the PTX backend (patch 2 of N) 
Get rid of some of the no-longer-needed parts of PTXAsmPrinter.

llvm-svn: 140698
 2011-09-28 14:32:06 +00:00
Justin Holewinski
2f96de340f PTX: MC-ize the PTX back-end (patch 1 of N) 
Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.

llvm-svn: 140697
 2011-09-28 14:32:04 +00:00
James Molloy
c4fcff419c Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696
 2011-09-28 14:21:38 +00:00
Benjamin Kramer
418d47fb38 PTX: Simplify code. No functionality change. 
llvm-svn: 140680
 2011-09-28 04:32:36 +00:00
Benjamin Kramer
e48bcfc038 PTX: Pass param name strings per const reference. 
The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++)

llvm-svn: 140679
 2011-09-28 04:08:02 +00:00
Jakob Stoklund Olesen
bbe41f6be8 Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix. 
I'll clean up the source in the next commit.

llvm-svn: 140663
 2011-09-28 00:01:54 +00:00
Akira Hatanaka
ea4d87c3e8 Remove MipsFPRound. Mips1 is no longer supported. 
llvm-svn: 140661
 2011-09-27 23:55:37 +00:00
Jakob Stoklund Olesen
2bf243f464 Remove X86-dependent stuff from SSEDomainFix. 
This also enables domain swizzling for AVX code which required a few
trivial test changes.

The pass will be moved to lib/CodeGen shortly.

llvm-svn: 140659
 2011-09-27 23:50:46 +00:00
Ted Kremenek
d233d7b066 Unbreak CMake build. 
llvm-svn: 140655
 2011-09-27 23:29:59 +00:00
Jakob Stoklund Olesen
2fc08f4eeb Implement TII::get/setExecutionDomain() for ARM. 
llvm-svn: 140653
 2011-09-27 22:57:21 +00:00
Jakob Stoklund Olesen
b843221bf0 Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo. 
I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass.  They are essentially doing the same
thing.

llvm-svn: 140652
 2011-09-27 22:57:18 +00:00
Jim Grosbach
b503a2183e ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w. 
Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799

llvm-svn: 140647
 2011-09-27 22:18:54 +00:00
Bill Wendling
c63b31e1ec This is the start of the new SjLj EH preparation pass, which will replace the 
current IR-level pass.

The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).

Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.

llvm-svn: 140646
 2011-09-27 22:14:12 +00:00
Akira Hatanaka
d44d75eccf Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside 
of the instruction definitions using Pat<>.

llvm-svn: 140644
 2011-09-27 22:01:01 +00:00
Jim Grosbach
e883e939a3 Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId(). 
Naming conventions consistency. No functional change.

llvm-svn: 140636
 2011-09-27 20:59:33 +00:00
Justin Holewinski
c74cdce7e0 PTX: Fix case where printed alignment could be 0 
llvm-svn: 140624
 2011-09-27 19:25:49 +00:00
Justin Holewinski
d7f59a21a7 PTX: Use external symbols to keep track of params and locals. This also fixes 
a couple of outstanding issues with frame objects occuring as instruction
operands.

llvm-svn: 140616
 2011-09-27 18:12:55 +00:00
Jakob Stoklund Olesen
08b5751146 Use existing function. 
llvm-svn: 140615
 2011-09-27 17:55:08 +00:00
Akira Hatanaka
33908261c2 Fix function MipsRegisterInfo::getRegisterNumbering. 
Return numbers of 64-bit registers.

llvm-svn: 140609
 2011-09-27 17:15:27 +00:00