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19254 Commits

Author SHA1 Message Date
Duncan Sands
1da590b589 Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from 
floating point add/sub of appropriate shuffle vectors.  Does not
synthesize the 256 bit AVX versions because they work differently.

llvm-svn: 140332
 2011-09-22 20:15:48 +00:00
Akira Hatanaka
82aaeed7f4 Print parentheses in next line. 
llvm-svn: 140325
 2011-09-22 18:29:29 +00:00
Akira Hatanaka
7bba6afecf Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment. 
llvm-svn: 140324
 2011-09-22 18:24:21 +00:00
Akira Hatanaka
eaf1e32694 Define a new sub-register index sub_32 for accessing the 32-bit sub-register of 
a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.

llvm-svn: 140319
 2011-09-22 17:57:32 +00:00
Akira Hatanaka
329b07db41 Print three closing parentheses when Kind is either VK_Mips_GPOFF_HI or 
VK_Mips_GPOFF_LO.

llvm-svn: 140316
 2011-09-22 17:44:37 +00:00
Akira Hatanaka
96122b7f72 Add F31 to the set of callee-saved registers. 
llvm-svn: 140315
 2011-09-22 17:35:03 +00:00
Akira Hatanaka
6b99d9b0f3 Fix typo. 
llvm-svn: 140313
 2011-09-22 17:26:58 +00:00
Justin Holewinski
a43c9dc50c PTX: Remove physical register defs 
llvm-svn: 140310
 2011-09-22 16:45:48 +00:00
Justin Holewinski
04f4046d9f PTX: Use .param space for device function return values on SM 2.0+, and attempt 
to fix up parameter passing on SM < 2.0

llvm-svn: 140309
 2011-09-22 16:45:46 +00:00
Justin Holewinski
987b8f7a69 PTX: Fix style issues 
llvm-svn: 140308
 2011-09-22 16:45:43 +00:00
Justin Holewinski
815227205d PTX: Fixup codegen to handle emission of virtual registers. 
llvm-svn: 140307
 2011-09-22 16:45:40 +00:00
Justin Holewinski
1dd4cf37f8 PTX: Customize codegen passes in backend 
llvm-svn: 140306
 2011-09-22 16:45:37 +00:00
Justin Holewinski
fee8e64e4d PTX: Add new PTX-specific register allocator that keeps virtual registers 
instead of allocating physical registers.

This is part of a work-in-progress overhaul of the PTX register allocation scheme.

llvm-svn: 140305
 2011-09-22 16:45:33 +00:00
Craig Topper
95f048d1ff Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960 
llvm-svn: 140299
 2011-09-22 07:01:50 +00:00
Akira Hatanaka
12218a1192 Add definition of 64-bit floating registers used for Mips64. 
llvm-svn: 140297
 2011-09-22 03:48:47 +00:00
Benjamin Kramer
978ef840ac The SSE version differences for fmin/fmax are more involved than I thought. 
- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)

llvm-svn: 140296
 2011-09-22 03:27:22 +00:00
Akira Hatanaka
d34925f313 Add enums and functions for symbols Mips64 uses. 
llvm-svn: 140295
 2011-09-22 03:09:07 +00:00
Benjamin Kramer
5844bacf0a X86: Don't form min/max nodes if the target is missing SSE. 
llvm-svn: 140294
 2011-09-22 03:01:42 +00:00
Akira Hatanaka
65c0724c19 Mips64 aligns stack on 16-byte boundary. 
llvm-svn: 140292
 2011-09-22 02:53:37 +00:00
Akira Hatanaka
60cd2b0c2f Remove unnecessary condition check. 
llvm-svn: 140291
 2011-09-22 02:41:29 +00:00
Owen Anderson
22ab29756b Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused. 
llvm-svn: 140284
 2011-09-21 23:53:44 +00:00
Owen Anderson
7b134fe54c Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. 
llvm-svn: 140283
 2011-09-21 23:44:46 +00:00
Benjamin Kramer
8b12bfc4ec X86Disassembler: if verbose logging is going to nulls(), disable logging completely. 
Otherwise we'll spend a ridiculous amount of time pretty printing debug output and then discarding it.

llvm-svn: 140276
 2011-09-21 21:47:35 +00:00
Wesley Peck
10002dcc07 Fix some simple copy-paste errors in MBlaze ASM Parser and Makefile. 
patch contributed by Jia Liu!

llvm-svn: 140273
 2011-09-21 19:23:46 +00:00
Owen Anderson
220db2953c These do not need to be conditional on the presence of CommentStream, as they have a fallback path now. 
llvm-svn: 140267
 2011-09-21 17:58:45 +00:00
Akira Hatanaka
8c3fbb9a71 Undo a change made in r140254. 
MipsArchVersion needs to be initialized to Mips32.

llvm-svn: 140261
 2011-09-21 17:31:45 +00:00
Nadav Rotem
71bd67ac2e fix comment 
llvm-svn: 140258
 2011-09-21 17:14:40 +00:00
Akira Hatanaka
c9f510b4e9 MipsArchVersion does not need to be in the initialization list and MipsABI 
should be initialized to UnknownABI.

llvm-svn: 140254
 2011-09-21 16:41:43 +00:00
Nadav Rotem
8fc9d777a3 Insert a sanity check on the combining of x86 truncing-store nodes. This comes to replace the problematic check that was removed in r139995. 
llvm-svn: 140246
 2011-09-21 08:45:10 +00:00
Richard Trieu
a675de9fac Change: 
assert(!"error message");

To:

  assert(0 && "error message");

which is more consistant across the code base.

llvm-svn: 140234
 2011-09-21 03:09:09 +00:00
Akira Hatanaka
88ce0f7440 Add a base class for Mips TargetMachines and add Mips64 TargetMachines. 
llvm-svn: 140233
 2011-09-21 03:00:58 +00:00
Akira Hatanaka
a936c212fa Set ABI if it hasn't been set on the command line. 
Check if architecture & ABI combination is valid.

llvm-svn: 140230
 2011-09-21 02:45:29 +00:00
Akira Hatanaka
31b9daf57e Fix typo. 
llvm-svn: 140229
 2011-09-21 02:24:25 +00:00
Andrew Trick
c94573ded6 Lower ARM adds/subs to add/sub after adding optional CPSR operand. 
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.

llvm-svn: 140228
 2011-09-21 02:20:46 +00:00
Andrew Trick
5b514628ed whitespace 
llvm-svn: 140227
 2011-09-21 02:17:37 +00:00
Owen Anderson
fbec62c99e In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on. 
llvm-svn: 140217
 2011-09-21 00:25:23 +00:00
Akira Hatanaka
eb3e16d39f Change the names of functions isMips* to hasMips*. 
llvm-svn: 140214
 2011-09-20 23:53:09 +00:00
Bruno Cardoso Lopes
629e7c2410 Revert r140097, working on a better approach 
llvm-svn: 140203
 2011-09-20 23:19:29 +00:00
Bruno Cardoso Lopes
035414367a Simplify max/minp[s|d] dagcombine matching 
llvm-svn: 140199
 2011-09-20 22:34:45 +00:00
Bruno Cardoso Lopes
b3eab8c22d Tidy up a bit more, fix tab and remove trailing whitespaces 
llvm-svn: 140186
 2011-09-20 21:45:26 +00:00
Bruno Cardoso Lopes
906f64c461 The wrong relocation was being emitted for several SSSE3 instructions. 
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.

llvm-svn: 140184
 2011-09-20 21:39:21 +00:00
Bruno Cardoso Lopes
dab989502d Tidy up code! 
llvm-svn: 140183
 2011-09-20 21:39:06 +00:00
Evan Cheng
ead45e2ba6 Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911. 
llvm-svn: 140181
 2011-09-20 21:38:18 +00:00
Akira Hatanaka
4dfc257283 Initial Mips64 support. Patch by Liu with some modifications. 
llvm-svn: 140178
 2011-09-20 20:28:08 +00:00
Andrew Trick
bfac89c238 Restore hasPostISelHook tblgen flag. 
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.

llvm-svn: 140160
 2011-09-20 18:22:31 +00:00
Craig Topper
df17f1cc99 Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd. 
llvm-svn: 140140
 2011-09-20 07:38:59 +00:00
Andrew Trick
53aeb9f663 ARM isel bug fix for adds/subs operands. 
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile

llvm-svn: 140134
 2011-09-20 03:17:40 +00:00
Andrew Trick
43ccb48fb2 whitespace 
llvm-svn: 140133
 2011-09-20 03:06:13 +00:00
Jim Grosbach
e936bdc286 Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH. 
llvm-svn: 140125
 2011-09-20 00:46:54 +00:00
Jim Grosbach
5ca3bddd26 Thumb2 assembly parsing and encoding for USAX. 
llvm-svn: 140119
 2011-09-20 00:30:45 +00:00
Jim Grosbach
882f1ec6d5 Remove incorrect comments. These are not disassmebly only patterns. 
llvm-svn: 140116
 2011-09-20 00:26:34 +00:00
Jim Grosbach
18a65f1fe6 Thumb2 assembly parsing and encoding for UQASX/UQSAX. 
llvm-svn: 140111
 2011-09-20 00:18:52 +00:00
Jim Grosbach
3de5351645 Thumb1 convenience aliases for disassembler round-trip testing. CPS instruction. 
llvm-svn: 140108
 2011-09-20 00:10:37 +00:00
Jim Grosbach
dd395f87df Thumb CPS definition is not disassembler only. 
llvm-svn: 140106
 2011-09-20 00:00:06 +00:00
Jim Grosbach
794028c0e0 Thumb2 range check on CPS mode immediate. 
llvm-svn: 140105
 2011-09-19 23:58:31 +00:00
Owen Anderson
791a17f64a tMOVSr is not allowed in an IT block either. 
llvm-svn: 140104
 2011-09-19 23:57:20 +00:00
Owen Anderson
3920c43055 CPS instructions are UNPREDICTABLE inside IT blocks. 
llvm-svn: 140102
 2011-09-19 23:47:10 +00:00
Jim Grosbach
011bd172ea Tidy up comments. 
llvm-svn: 140099
 2011-09-19 23:38:34 +00:00
Bruno Cardoso Lopes
de0dc10d6d Fix PR10949. Fix the encoding of VMOVPQIto64rr. 
llvm-svn: 140098
 2011-09-19 23:36:59 +00:00
Bruno Cardoso Lopes
7cf7f02c3d Based on the small opt Zvi's patch was trying to achieve, eliminate 
128-bit undef subvector insertion into a 256-bit vector

llvm-svn: 140097
 2011-09-19 23:36:50 +00:00
Jim Grosbach
2341e082fc Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL. 
llvm-svn: 140095
 2011-09-19 23:31:02 +00:00
Jim Grosbach
dd8d66f3aa Thumb2 assembly parsing and encoding for UHASX/UHSAX. 
llvm-svn: 140088
 2011-09-19 23:13:25 +00:00
Jim Grosbach
a5a28c45e5 Thumb2 assembly parsing and encoding for UASX. 
llvm-svn: 140085
 2011-09-19 23:05:22 +00:00
Owen Anderson
25138827ef Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle. 
llvm-svn: 140079
 2011-09-19 22:34:23 +00:00
Jim Grosbach
6da9e6b23d Thumb2 assembly parsing and encoding for TBB/TBH. 
llvm-svn: 140078
 2011-09-19 22:21:13 +00:00
Bruno Cardoso Lopes
9e5ef44daf Match X86ISD::FSETCCsd and X86ISD::FSETCCss while in AVX mode. This fix 
PR10955 and PR10948.

llvm-svn: 140069
 2011-09-19 21:29:24 +00:00
Jim Grosbach
207a337a60 Tidy up a bit. 
llvm-svn: 140050
 2011-09-19 20:31:59 +00:00
Jim Grosbach
c7fa5f0c00 Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH. 
llvm-svn: 140047
 2011-09-19 20:29:33 +00:00
Akira Hatanaka
6731be3175 Make changes to avoid creating nested CALLSEQ_START/END constructs, which aren't 
yet legal according to comments in LegalizeDAG.cpp:227. 

Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.

The two failing tests reported in PR10876 pass after applying this patch.  

llvm-svn: 140046
 2011-09-19 20:26:02 +00:00
Owen Anderson
4bf9e290e9 Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding. 
llvm-svn: 140041
 2011-09-19 20:00:02 +00:00
Jim Grosbach
57328aa902 ARM asm parsing should handle pre-indexed writeback w/o immediate. 
For example, 'ldrb r9, [sp]!' is odd, but valid.

llvm-svn: 140035
 2011-09-19 18:42:21 +00:00
Owen Anderson
b843f3625d Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. 
llvm-svn: 140032
 2011-09-19 18:07:10 +00:00
Jim Grosbach
c677995374 Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH. 
llvm-svn: 140029
 2011-09-19 17:56:37 +00:00
Nadav Rotem
a6af03c6fb Fix typos in my prev commit, found by Tobi. 
llvm-svn: 140003
 2011-09-18 19:00:23 +00:00
Nadav Rotem
1cfdc59e94 setOperationAction should be done on the return value of the type, not the operands. 
llvm-svn: 140001
 2011-09-18 14:57:03 +00:00
Nadav Rotem
cfc77bc719 When promoting integer vectors we often create ext-loads. This patch adds a 
dag-combine optimization to implement the ext-load efficiently (using shuffles).

For example the type <4 x i8> is stored in memory as i32, but it needs to
find its way into a <4 x i32> register. Previously we scalarized the memory
access, now we use shuffles.

llvm-svn: 139995
 2011-09-18 10:39:32 +00:00
Craig Topper
c5a97d12bb Fix typo by changing Lower256IntVETCC to Lower256IntVSETCC. 
llvm-svn: 139993
 2011-09-18 08:03:58 +00:00
Duncan Sands
4149334f09 Synthesize x86 max/min instructions also for vectors (i.e. produce 
maxps and maxpd).  This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it.  Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.

llvm-svn: 139986
 2011-09-17 16:49:39 +00:00
Bruno Cardoso Lopes
f611f6c371 Describe more AVX 128-bit convert instructions without patterns to have 
mayLoad = 1

llvm-svn: 139973
 2011-09-16 23:41:29 +00:00
Owen Anderson
c1f638997d Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB. 
llvm-svn: 139972
 2011-09-16 23:30:01 +00:00
Owen Anderson
aec67a3ea1 Fix bitfield decoding based on Eli's feedback. 
llvm-svn: 139969
 2011-09-16 23:04:48 +00:00
Jim Grosbach
95242bff08 Thumb2 assembly parsing and encoding for SUB(immediate). 
llvm-svn: 139966
 2011-09-16 22:58:42 +00:00
Owen Anderson
5d23e1e5b4 Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. 
llvm-svn: 139965
 2011-09-16 22:42:36 +00:00
Owen Anderson
eae0eee720 Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). 
llvm-svn: 139964
 2011-09-16 22:29:48 +00:00
Owen Anderson
3a487c8c9b Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's. 
llvm-svn: 139958
 2011-09-16 22:17:02 +00:00
Bruno Cardoso Lopes
396b8136bf Add mayLoad attribute to AVX convert instructions, since non of them 
are declared with load patterns. This fix the crash in PR10941. No testcases,
since a fold is triggered and then converted back to the register form
afterwards.

llvm-svn: 139953
 2011-09-16 22:02:14 +00:00
Jim Grosbach
d521731d40 Thumb2 assembly parsing and encoding for STR. 
More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).

llvm-svn: 139949
 2011-09-16 21:55:56 +00:00
Jim Grosbach
371c88528b Tidy up. 80 columns. 
llvm-svn: 139944
 2011-09-16 21:09:00 +00:00
Owen Anderson
5804085f26 Fix disassembly of Thumb2 LDRSH with a #-0 offset. 
llvm-svn: 139943
 2011-09-16 21:08:33 +00:00
Jim Grosbach
916a6c71aa Thumb2 assembly parsing and encoding for STR(immediate). 
Add aliases for STRB/STRH while there. Tests forthcoming for those.

llvm-svn: 139942
 2011-09-16 21:06:12 +00:00
Bruno Cardoso Lopes
a60e62ad02 Fix PR10884. 
This PR basically reports a problem where a crash in generated code
happened due to %rbp being clobbered:

  pushq %rbp
  movq  %rsp, %rbp
  ....
  vmovmskps %ymm12, %ebp
  ....
  movq  %rbp, %rsp
  popq  %rbp
  ret

Since Eric's r123367 commit, the default stack alignment for x86 32-bit
has changed to be 16-bytes. Since then, the MaxStackAlignmentHeuristicPass
hasn't been really used, but with AVX it becomes useful again, since per
ABI compliance we don't always align the stack to 256-bit, but only when
there are 256-bit incoming arguments.

ReserveFP was only used by this pass, but there's no RA target hook that
uses getReserveFP() to check for the presence of FP (since nothing was
triggering the pass to run, the uses of getReserveFP() were removed
through time without being noticed). Change this pass to use
setForceFramePointer, which is properly called by MachineFunction
hasFP method.

The testcase is very big and dependent on RA, not sure if it's worth
adding to test/CodeGen/X86.

llvm-svn: 139939
 2011-09-16 20:58:28 +00:00
Jim Grosbach
13af7198d5 Thumb2 assembly parsing and encoding for STMIA. 
llvm-svn: 139938
 2011-09-16 20:50:13 +00:00
Jim Grosbach
47ff106753 Thumb2 assembly parsing and encoding for SSAX. 
llvm-svn: 139929
 2011-09-16 18:37:10 +00:00
Jim Grosbach
6f6453f64b Thumb2 assembly parsing and encoding for SSAT. 
llvm-svn: 139926
 2011-09-16 18:32:30 +00:00
Jim Grosbach
5a8b63fe51 Thumb2 assembly parsing and encoding for SRS. 
llvm-svn: 139925
 2011-09-16 18:25:22 +00:00
Jim Grosbach
0f1615c381 Thumb2 assembly parsing and encoding for SMMULL. 
llvm-svn: 139921
 2011-09-16 18:05:48 +00:00
Jim Grosbach
3c3a9393ab Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX. 
llvm-svn: 139909
 2011-09-16 17:10:44 +00:00
Jim Grosbach
9e471afd9c Thumb2 assembly parsing and encoding for SMLALD/SMLALDX. 
llvm-svn: 139906
 2011-09-16 16:58:03 +00:00
Jim Grosbach
f41c168102 Kill some dead code. 
llvm-svn: 139904
 2011-09-16 16:45:40 +00:00
Jim Grosbach
94fec9618a Tidy up a bit. 
llvm-svn: 139903
 2011-09-16 16:39:25 +00:00
Jim Grosbach
d382581509 Thumb2 assembly parsing and encoding for SMLAL. 
llvm-svn: 139902
 2011-09-16 16:38:00 +00:00
Jim Grosbach
27a086b1d0 Remove incorrect comments. 
llvm-svn: 139877
 2011-09-15 23:45:50 +00:00
Owen Anderson
e54c4beb5a Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. 
llvm-svn: 139876
 2011-09-15 23:38:46 +00:00
Bruno Cardoso Lopes
1465f4d334 Add a fixme note! 
llvm-svn: 139872
 2011-09-15 23:04:24 +00:00
Jim Grosbach
423aae30b2 Thumb2 assembly parsing and encoding for SHASX/SHSAX. 
llvm-svn: 139870
 2011-09-15 22:34:29 +00:00
Eli Friedman
0e654e52d9 Minor cleanup. 
llvm-svn: 139869
 2011-09-15 22:26:18 +00:00
Eli Friedman
1df4766bda Use a more efficient lowering for Unordered/Monotonic atomic load/store on Thumb1. 
llvm-svn: 139865
 2011-09-15 22:18:49 +00:00
Bruno Cardoso Lopes
7ad9ea026a Add the remaining AVX versions of instructions to X86InstrInfo, this 
time for describing high latency ones and for recognizting loads
from the same base pointer

llvm-svn: 139864
 2011-09-15 22:15:52 +00:00
Bruno Cardoso Lopes
901f6ff218 Factor out partial register update checks for some SSE instructions. 
Also add the AVX versions and add comments!

llvm-svn: 139854
 2011-09-15 21:42:23 +00:00
Jim Grosbach
1ac9dd8a72 Thumb2 assembly parsing and encoding for SASX. 
llvm-svn: 139843
 2011-09-15 21:01:23 +00:00
Jim Grosbach
553692fcce Thumb2 assembly parsing and encoding for RSB. 
llvm-svn: 139839
 2011-09-15 20:54:14 +00:00
Jim Grosbach
50ee930e9a Thumb2 assembly parsing and encoding for REV16/REVSH. 
llvm-svn: 139828
 2011-09-15 19:46:13 +00:00
Owen Anderson
84d4e5d0e2 Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out. Enhance the ARM and X86 InstPrinter's to do so in verbose mode. 
llvm-svn: 139820
 2011-09-15 18:36:29 +00:00
Bruno Cardoso Lopes
8e702bba63 Change all checks regarding the presence of any SSE level to always 
take into consideration the presence of AVX. This change, together with
the SSEDomainFix enabled for AVX, makes AVX codegen to always (hopefully)
emit the same code as SSE for 128-bit vector ops. I don't
have a testcase for this, but AVX now beats SSE in performance for
128-bit ops in the majority of programas in the llvm testsuite

llvm-svn: 139817
 2011-09-15 18:27:36 +00:00
Bruno Cardoso Lopes
0fa8b71a55 Enable SSEDomainFix pass for AVX mode. 
llvm-svn: 139816
 2011-09-15 18:27:32 +00:00
Jim Grosbach
9d7aa9bcbc Thumb2 assembly parsing and encoding for REV. 
llvm-svn: 139813
 2011-09-15 18:13:30 +00:00
Jim Grosbach
69ddec5ff7 ARM support the pre-UAL mnemonic 'qsubaddx' for 'qsax.' 
llvm-svn: 139796
 2011-09-15 16:16:50 +00:00
Jim Grosbach
d428c970e3 Thumb2 push/pop mnemonic recognition. 
llvm-svn: 139794
 2011-09-15 15:55:04 +00:00
Eli Friedman
7cb90dcbce Fix the code creating VZEXT_LOAD so that it creates the right memoperand. Issue spotted in -debug output. I can't think of any practical effects at the moment, but it might matter if we start doing more aggressive alias analysis in CodeGen. 
llvm-svn: 139758
 2011-09-14 23:42:45 +00:00
Jim Grosbach
669e269758 Thumb2 assembly parsing and encoding for PKH. 
llvm-svn: 139754
 2011-09-14 23:16:41 +00:00
Jim Grosbach
c1475b0f3f ARMv7a has the PKH instructions. 
llvm-svn: 139753
 2011-09-14 23:16:34 +00:00
Jim Grosbach
1a4f264f52 ARM tighten up the register classes for the PKH instructions. 
llvm-svn: 139748
 2011-09-14 22:52:14 +00:00
Owen Anderson
86f1fb2955 Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs. 
llvm-svn: 139747
 2011-09-14 22:46:14 +00:00
Jim Grosbach
e841adae12 Thumb2 assembly parsing and encoding for MVN. 
llvm-svn: 139739
 2011-09-14 21:24:41 +00:00
Owen Anderson
04d8803035 Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. 
llvm-svn: 139736
 2011-09-14 21:06:21 +00:00
Jim Grosbach
585e3c779f Thumb2 assembly parsing and encoding for MUL. 
llvm-svn: 139735
 2011-09-14 21:00:40 +00:00
Jim Grosbach
b1c70aab3e Thumb2 assembly parsing and encoding for MSR/MRS. 
Fix a bug in handling default flags for both ARM and Thumb encodings.

llvm-svn: 139721
 2011-09-14 20:03:46 +00:00
Jim Grosbach
932d409524 Thumb2 assembly parsing for MOV in IT block. 
Select the right 16 vs. 32 bit encoding in an IT block.

llvm-svn: 139714
 2011-09-14 19:12:11 +00:00
Jim Grosbach
41c8bdfdd9 ARM fix assembly parser handling of ranges in register lists. 
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.

rdar://8883573

llvm-svn: 139707
 2011-09-14 18:08:35 +00:00
Akira Hatanaka
e74b377e20 Add comment. 
llvm-svn: 139699
 2011-09-14 17:22:51 +00:00
Craig Topper
60719c7bfb Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler. 
llvm-svn: 139691
 2011-09-14 06:41:26 +00:00
Craig Topper
25e81ae604 Make disassembling of VBLEND* print immediate as a XMM/YMM register name. Fixes PR10917. 
llvm-svn: 139690
 2011-09-14 05:55:28 +00:00
Bruno Cardoso Lopes
33c057e094 One more patch towards JIT support for Mips. 
- Add TSFlags for the instruction formats. The idea here is to use
  as much encoding as possible from getBinaryCodeForInstr, and having
  TSFLags formats for that would make it easier to encode most part
  of the instructions (since Mips encodings are pretty straightforward)
- Improve the mips mechanism for compilation callback
- Add Mips specific code for invalidating the instruction cache
- Next patch will address wrong tablegen encoding

Commit msg added by my own but the patch is from Sasa Stankovic.

llvm-svn: 139688
 2011-09-14 03:00:41 +00:00
Bruno Cardoso Lopes
27a7ace4b4 Teach the foldable tables about 128-bit AVX instructions and make the 
alignment check for 256-bit classes more strict. There're no testcases
but we catch more folding cases for AVX while running single and multi
sources in the llvm testsuite.

Since some 128-bit AVX instructions have different number of operands
than their SSE counterparts, they are placed in different tables.

256-bit AVX instructions should also be added in the table soon. And
there a few more 128-bit versions to handled, which should come in
the following commits.

llvm-svn: 139687
 2011-09-14 02:36:58 +00:00
Bruno Cardoso Lopes
3e6b9661d1 Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "movss". 
llvm-svn: 139686
 2011-09-14 02:36:14 +00:00
Jim Grosbach
b2ddf62001 Remove unnecessary scope resolution operator. 
llvm-svn: 139656
 2011-09-13 22:56:44 +00:00
Owen Anderson
d0121fe635 Correct disassembly printing of Thumb2 post-incremented LDRD and STRD. 
llvm-svn: 139639
 2011-09-13 20:46:26 +00:00
Jim Grosbach
90b78a6f1f There's only 16 regs legal in a register list. 
llvm-svn: 139637
 2011-09-13 20:35:57 +00:00
Jim Grosbach
74f96e7f3c Tidy up a few 80 column violations. 
llvm-svn: 139636
 2011-09-13 20:30:37 +00:00
Jim Grosbach
a04c99bca5 Tidy up a bit. 
llvm-svn: 139635
 2011-09-13 20:27:44 +00:00
Akira Hatanaka
44c745931f Add pattern used to match MipsLo, which is needed when the instruction selector 
tries to match a dead MipsLo node (explanation in the link below).

http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead

llvm-svn: 139634
 2011-09-13 20:13:58 +00:00
Nadav Rotem
f1730712f7 swap vselect operand order - pr10907 
llvm-svn: 139630
 2011-09-13 19:56:38 +00:00
Bruno Cardoso Lopes
f02589db47 Add versions 256-bit versions of alignedstore and alignedload, to be 
more strict about the alignment checking. This was found by inspection
and I don't have any testcases so far, although the llvm testsuite runs
without any problem.

llvm-svn: 139625
 2011-09-13 19:33:03 +00:00
Bruno Cardoso Lopes
6f299a4937 Revert the remaining part of r139528. According to PR10907 the bug seems 
to be in the VSELECT operands order, so I'll leave the fix for Nadav.

llvm-svn: 139624
 2011-09-13 19:33:00 +00:00
Nadav Rotem
60df99b809 Add vselect target support for targets that do not support blend but do support 
xor/and/or (For example SSE2).

llvm-svn: 139623
 2011-09-13 19:17:42 +00:00
Akira Hatanaka
052c83e7a2 Support for PSP is gone too. 
llvm-svn: 139622
 2011-09-13 18:55:33 +00:00
Owen Anderson
b4ed08c465 Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally. 
llvm-svn: 139610
 2011-09-13 17:59:19 +00:00
Akira Hatanaka
4cdd5fca36 It is not necessary to search for mipsallegrex in target triple string. 
llvm-svn: 139607
 2011-09-13 17:35:28 +00:00
Owen Anderson
5982d4d51b Fix encoding of Thumb2 shifted register operands with RRX shifts. 
llvm-svn: 139606
 2011-09-13 17:34:32 +00:00
Craig Topper
0f36afb30c Only disassembler instructions with vvvv != 1111 if the instruction actually uses the vvvv field to encode an operand. Fixes PR10851. 
llvm-svn: 139591
 2011-09-13 07:37:44 +00:00