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Author SHA1 Message Date
Bill Wendling
44e1f00275 s/Raw/getBitMask/g to be more in line with current naming conventions. This method won't be sticking around. 
llvm-svn: 171244
 2012-12-30 01:05:42 +00:00
NAKAMURA Takumi
77a7dbf266 llvm/test/Transforms/GVN/null-aliases-nothing.ll: Fix a RUN line not to emit ModuleID. 
Larry Evans reported it fails if source tree contains "load", like "download".

llvm-svn: 171243
 2012-12-30 00:33:26 +00:00
Craig Topper
175e8218c5 Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those. 
llvm-svn: 171237
 2012-12-29 18:18:20 +00:00
Craig Topper
84898044c9 Merge similar functionality using a nested switch. 
llvm-svn: 171229
 2012-12-29 17:19:06 +00:00
Craig Topper
93fdde7fff Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled. 
llvm-svn: 171227
 2012-12-29 16:44:25 +00:00
Jakub Staszak
f9fc85f71d Simplify code, no functionality change. 
llvm-svn: 171226
 2012-12-29 15:57:26 +00:00
Jakub Staszak
3588dcff13 Delete executive bit on ./lib/Target/Hexagon/HexagonAsmPrinter.h. 
llvm-svn: 171225
 2012-12-29 15:23:06 +00:00
Bill Wendling
284a1ee5ba Use a 'Constant' object instead of a bit field to store the attribute data. 
llvm-svn: 171221
 2012-12-29 12:29:38 +00:00
Bill Wendling
7721e04b74 Use the accessor method instead of the raw ivar to get the bits. 
llvm-svn: 171220
 2012-12-29 12:10:46 +00:00
Chandler Carruth
afc2a0c669 Nuke some dead code that snuck in some how. I thought I had already 
deleted this, but apparantly not. Charmingly, Clang didn't warn on it
but GCC did.

llvm-svn: 171197
 2012-12-28 14:50:51 +00:00
Chandler Carruth
f3295eafa5 Fix a stunning oversight in the inline cost analysis. It was never 
propagating one of the values it simplified to a constant across
a myriad of instructions. Notably, ptrtoint instructions when we had
a constant pointer (say, 0) didn't propagate that, blocking a massive
number of down-stream optimizations.

This was uncovered when investigating why we fail to inline and delete
the boilerplate in:

  void f() {
    std::vector<int> v;
    v.push_back(1);
  }

It turns out most of the efforts I've made thus far to improve the
analysis weren't making it far purely because of this. After this is
fixed, the store-to-load forwarding patch enables LLVM to optimize the
above to an empty function. We still can't nuke a second push_back, but
for different reasons.

There is a very real chance this will cause somewhat noticable changes
in inlining behavior, so please let me know if you see regressions (or
improvements!) because of this patch.

llvm-svn: 171196
 2012-12-28 14:43:42 +00:00
Chandler Carruth
8f719ce3e5 Teach the inline cost analysis about calls that can be simplified and 
how to propagate constants through insert and extract value
instructions.

With the recent improvements to instsimplify, this allows inline cost
analysis to constant fold through intrinsic functions, including notably
the with.overflow intrinsic math routines which often show up inside of
STL abstractions. This is yet another piece in the puzzle of breaking
down the code for:

  void f() {
    std::vector<int> v;
    v.push_back(1);
  }

But it still isn't enough. There are a pile of bugs in inline cost still
blocking this.

llvm-svn: 171195
 2012-12-28 14:23:32 +00:00
Chandler Carruth
93a470549b Teach instsimplify to use the constant folder where appropriate for 
constant folding calls. Add the initial tests for this which show that
now instsimplify can simplify blindingly obvious code patterns expressed
with both intrinsics and library calls.

llvm-svn: 171194
 2012-12-28 14:23:29 +00:00
Chandler Carruth
b113216136 Add entry points to instsimplify for simplifying calls. The entry points 
are nice and decomposed so that we can simplify synthesized calls as
easily as actually call instructions. The internal utility still has the
same behavior, it just now operates on a more generic interface so that
I can extend the set of call simplifications that instsimplify knows
about.

llvm-svn: 171189
 2012-12-28 11:30:55 +00:00
Alexey Samsonov
3a437b2e64 Add proper support for -fsanitize-blacklist= flag for TSan and MSan. LLVM part. 
llvm-svn: 171183
 2012-12-28 09:30:44 +00:00
Nadav Rotem
c8ec143f05 CostModel: initial checkin for code that estimates the cost of special shuffles. 
llvm-svn: 171180
 2012-12-28 08:19:03 +00:00
Nadav Rotem
d5216d7ac7 wrap 80-col lines. 
llvm-svn: 171179
 2012-12-28 07:28:43 +00:00
Nadav Rotem
8f2be23305 AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend. 
llvm-svn: 171178
 2012-12-28 05:45:24 +00:00
Nadav Rotem
6850870c3f Reverse the 'if' condition and reduce the indentation. 
llvm-svn: 171172
 2012-12-27 23:08:05 +00:00
Craig Topper
e2fd2d2c63 Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses. 
llvm-svn: 171171
 2012-12-27 22:53:47 +00:00
Nadav Rotem
051a0524a1 AVX/AVX2: Move the SEXT lowering code from a target specific DAGco to a lowering function. 
llvm-svn: 171170
 2012-12-27 22:47:16 +00:00
Craig Topper
179835e645 Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses. 
llvm-svn: 171166
 2012-12-27 18:51:50 +00:00
Chandler Carruth
e20bfe3a35 Add support to BasicBlocks for iterating backwards over the 
instructions. This just exposes the already present reverse iterators of
the instruction ilist.

llvm-svn: 171159
 2012-12-27 12:00:56 +00:00
Chandler Carruth
3f86485d73 Provide a common half-open interval map info implementation, and just 
re-use that for SlotIndexes. This way other users who want half-open
semantics can share the implementation.

llvm-svn: 171158
 2012-12-27 11:29:17 +00:00
Chandler Carruth
e396ef7f05 Make this parameter be named consistently with most other 
getAnalysisUsage implementations.

llvm-svn: 171157
 2012-12-27 11:17:15 +00:00
Sean Silva
ffbd8c6222 docs: Add FAQ about "storing to a virtual register". 
This came up for the N+1'st time today in IRC.

llvm-svn: 171155
 2012-12-27 10:23:04 +00:00
Sean Silva
32965d0b6e docs: Move link to the new "external tutorials" area. 
llvm-svn: 171154
 2012-12-27 08:57:08 +00:00
Alexey Samsonov
b3bcf27f5a [ASan] Fix lifetime intrinsics handling. Now for each intrinsic we check if it describes one of 'interesting' allocas. Assume that allocas can go through casts and phi-nodes before apperaring as llvm.lifetime arguments 
llvm-svn: 171153
 2012-12-27 08:50:58 +00:00
Nadav Rotem
fcfd42040b DAGCombinerInformation: add a getter that exposes the dagcombine level. 
llvm-svn: 171152
 2012-12-27 08:44:35 +00:00
Alexey Samsonov
319ccd0fdb Fix new[]/delete mismatch in FullDependence spotted by AddressSanitizer 
llvm-svn: 171150
 2012-12-27 08:40:37 +00:00
Nadav Rotem
017cc9b165 docs: Update the benchmark with updated perf numbers. 
llvm-svn: 171149
 2012-12-27 08:32:44 +00:00
Nadav Rotem
2f6e04c7be On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized 
register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.

PR14657.

llvm-svn: 171148
 2012-12-27 08:15:45 +00:00
Nadav Rotem
76034b9bb4 AVX/AVX2: Move the code that lowers vector-trunc from a DAGCo-hook to custom lowering hook. 
The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.

llvm-svn: 171146
 2012-12-27 07:45:10 +00:00
Craig Topper
f3cf4daada Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT. 
llvm-svn: 171143
 2012-12-27 07:16:08 +00:00
Nadav Rotem
55c5987673 Refactor DAGCombinerInfo. Change the different booleans that indicate if we are before or after different runs of DAGCo, with the CombineLevel enum. 
Also, added a new API for checking if we are running before or after the LegalizeVectorOps phase. 

llvm-svn: 171142
 2012-12-27 06:47:41 +00:00
Craig Topper
a44c63c7b9 Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again. 
llvm-svn: 171141
 2012-12-27 06:34:54 +00:00
Craig Topper
56ee68554d Update tablegen parser to allow defm names to start with #NAME. 
llvm-svn: 171140
 2012-12-27 06:32:52 +00:00
Craig Topper
10e18bc2f3 Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation. 
llvm-svn: 171137
 2012-12-27 03:35:44 +00:00
Craig Topper
8411715f87 Mark the divide instructions as hasSideEffects=0. 
llvm-svn: 171136
 2012-12-27 03:01:18 +00:00
Eric Christopher
7096eb5a5c For the dwarf5 split debug info code split out the string section 
per compile unit/skeleton compile unit. Update tests accordingly.

llvm-svn: 171133
 2012-12-27 02:14:01 +00:00
Eric Christopher
eb6482f385 FileCheck-ize. 
llvm-svn: 171132
 2012-12-27 02:13:58 +00:00
Eric Christopher
4786ae2a5f FileCheck-ize. 
llvm-svn: 171131
 2012-12-27 02:13:55 +00:00
Craig Topper
4c075a815b Add hasSideEffects=0 to CMP*rr_REV. 
llvm-svn: 171130
 2012-12-27 02:08:46 +00:00
Nadav Rotem
798533821a whitespace 
llvm-svn: 171129
 2012-12-27 02:04:12 +00:00
Craig Topper
5650ea25b7 Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. 
llvm-svn: 171128
 2012-12-27 02:01:33 +00:00
Eric Christopher
c6fa1e95a2 Right now all of the relocations are 32-bit dwarf, and the relocation 
information doesn't return an addend for Rel relocations. Go ahead
and use this information to fix relocation handling inside dwarfdump
for 32-bit ELF REL.

llvm-svn: 171126
 2012-12-27 01:07:07 +00:00
Nadav Rotem
4cad811734 If all of the write objects are identified then we can vectorize the loop even if the read objects are unidentified. 
PR14719.

llvm-svn: 171124
 2012-12-26 23:30:53 +00:00
Craig Topper
9e3cb122f1 Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem. 
llvm-svn: 171123
 2012-12-26 23:27:57 +00:00
Craig Topper
fe4506dc6c Add hasSideEffects=0 to some atomic instructions. 
llvm-svn: 171122
 2012-12-26 23:08:12 +00:00
Craig Topper
c4205e1d63 Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects. 
llvm-svn: 171121
 2012-12-26 22:19:23 +00:00