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Commit Graph

93672 Commits

Author SHA1 Message Date
Michel Danzer
47a9f6685b R600/SI: Add intrinsics for texture sampling with user derivatives
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186008
2013-07-10 16:36:36 +00:00
Argyrios Kyrtzidis
5944d3cfb3 Remove llvm/ADT/NullablePtr.h, there are no uses of it in-tree.
llvm-svn: 186006
2013-07-10 15:33:20 +00:00
Hal Finkel
b6802c0a3e PPC: Add a better comment about the i64 FI fixup
In discussing this change with Bill Schmidt, it was decided that the original
comment about negative FIs was incorrect. We'll still exclude them for now, but
now with a more-accurate explanation.

llvm-svn: 186005
2013-07-10 15:29:01 +00:00
Vladimir Medic
cbe40f5bcd Reverting commit r185999 due to buildboot failure.
llvm-svn: 186001
2013-07-10 12:27:25 +00:00
Vladimir Medic
d4a8ab4928 Reverting commit r185999 due to buildboot failure.
llvm-svn: 186000
2013-07-10 12:26:26 +00:00
Vladimir Medic
408af148a4 Add support for Mips break and syscall insructions. The corresponding test cases are added.
llvm-svn: 185999
2013-07-10 10:18:10 +00:00
Stephen Lin
bba095310d Fix typo
llvm-svn: 185995
2013-07-10 01:57:39 +00:00
Stephen Lin
af86770cd4 Explicitly define ARMISelLowering::isFMAFasterThanFMulAndFAdd. No functionality change.
Currently ARM is the only backend that supports FMA instructions (for at least some subtargets) but does not implement this virtual, so FMAs are never generated except from explicit fma intrinsic calls. Apparently this is due to the fact that it supports both fused (one rounding step) and unfused (two rounding step) multiply + add instructions. This patch clarifies that this the case without changing behavior by implementing the virtual function to simply return false, as the default TargetLoweringBase version does.

It is possible that some cpus perform the fused version faster than the unfused version and vice-versa, so the function implementation should be revisited if hard data is found.

llvm-svn: 185994
2013-07-10 01:54:24 +00:00
Adrian Prantl
99aa5bc65a Un-break the buildbot by tweaking the indirection flag.
Pulled in a testcase from the debuginfo-test suite.

llvm-svn: 185993
2013-07-10 01:53:37 +00:00
Adrian Prantl
e80db7fe3b Document a known limitation of the status quo.
llvm-svn: 185992
2013-07-10 01:53:30 +00:00
Duncan Sands
16f270afdf Correct comment.
llvm-svn: 185987
2013-07-10 00:52:41 +00:00
Eric Christopher
6e1bb5f12d Fix comment.
llvm-svn: 185984
2013-07-09 23:48:45 +00:00
Jim Grosbach
d6be90a2b8 ARM: Fix incorrect pack pattern for thumb2
Propagate the fix from r185712 to Thumb2 codegen as well. Original
commit message applies here as well:

A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and
packs them in the bottom half of "x". An arithmetic and logic shift are
only equivalent in this context if the shift amount is 16. We would be
shifting in ones into the bottom 16bits instead of zeros if "y" is
negative.

rdar://14338767

llvm-svn: 185982
2013-07-09 22:59:22 +00:00
Peter Collingbourne
16d8086f72 Implement categories for special case lists.
A special case list can now specify categories for specific globals,
which can be used to instruct an instrumentation pass to treat certain
functions or global variables in a specific way, such as by omitting
certain aspects of instrumentation while keeping others, or informing
the instrumentation pass that a specific uninstrumentable function
has certain semantics, thus allowing the pass to instrument callers
according to those semantics.

For example, AddressSanitizer now uses the "init" category instead of
global-init prefixes for globals whose initializers should not be
instrumented, but which in all other respects should be instrumented.

The motivating use case is DataFlowSanitizer, which will have a
number of different categories for uninstrumentable functions, such
as "functional" which specifies that a function has pure functional
semantics, or "discard" which indicates that a function's return
value should not be labelled.

Differential Revision: http://llvm-reviews.chandlerc.com/D1092

llvm-svn: 185978
2013-07-09 22:03:17 +00:00
Peter Collingbourne
87165fe6e5 Add some SpecialCaseList unit tests.
Differential Revision: http://llvm-reviews.chandlerc.com/D1091

llvm-svn: 185977
2013-07-09 22:03:12 +00:00
Peter Collingbourne
1d4db968ba Introduce a SpecialCaseList ctor which takes a MemoryBuffer to make
it more unit testable, and fix memory leak in the other ctor.

Differential Revision: http://llvm-reviews.chandlerc.com/D1090

llvm-svn: 185976
2013-07-09 22:03:09 +00:00
Peter Collingbourne
2321a4030c Rename BlackList class to SpecialCaseList and move it to Transforms/Utils.
Differential Revision: http://llvm-reviews.chandlerc.com/D1089

llvm-svn: 185975
2013-07-09 22:02:49 +00:00
David Majnemer
0a8d4ca7e9 InstSimplify: X >> X -> 0
llvm-svn: 185973
2013-07-09 22:01:22 +00:00
Adrian Prantl
52d9227e1d move test into the appropriate subdir.
llvm-svn: 185972
2013-07-09 21:44:11 +00:00
Adrian Prantl
ed4b284841 Typo.
llvm-svn: 185971
2013-07-09 21:44:06 +00:00
Nadav Rotem
417c1a3150 Fix PR16571, which is a bug in the code that checks that all of the types in the bundle are uniform.
llvm-svn: 185970
2013-07-09 21:38:08 +00:00
Adrian Prantl
a295f68201 Reapply an improved version of r180816/180817.
Change the informal convention of DBG_VALUE machine instructions so that
we can express a register-indirect address with an offset of 0.
The old convention was that a DBG_VALUE is a register-indirect value if
the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE
is register-indirect if the first operand is a register and the second
operand is an immediate. For plain register values the combination reg,
reg is used. MachineInstrBuilder::BuildMI knows how to build the new
DBG_VALUES.

rdar://problem/13658587

llvm-svn: 185966
2013-07-09 20:28:37 +00:00
Michael Gottesman
fa360444cb Fixed up the comments in FastISel.h so that they conform to the LLVM style guide.
llvm-svn: 185964
2013-07-09 20:08:46 +00:00
Michael Gottesman
23be560da3 Added "mode: c++" to FastISel.h header.
llvm-svn: 185963
2013-07-09 20:00:25 +00:00
Stephen Lin
fb9d247b9c Appease buildbots after r185956: just set -mcpu explicitly, as it should have been from the beginning.
llvm-svn: 185962
2013-07-09 19:27:10 +00:00
Stephen Lin
ec7f16225b Appease Atom buildbot after r185956 (explicitly turn on AVX)
llvm-svn: 185961
2013-07-09 18:55:52 +00:00
Hal Finkel
560c3b2ad4 WidenVecRes_BUILD_VECTOR must use the first operand's type
Because integer BUILD_VECTOR operands may have a larger type than the result's
vector element type, and all operands must have the same type, when widening a
BUILD_VECTOR node by adding UNDEFs, we cannot use the vector element type, but
rather must use the type of the existing operands.

Another bug found by llvm-stress.

llvm-svn: 185960
2013-07-09 18:55:10 +00:00
Bill Schmidt
2499045a19 [PowerPC] Better fix for PR16556.
A more complete example of the bug in PR16556 was recently provided,
showing that the previous fix was not sufficient.  The previous fix is
reverted herein.

The real problem is that ReplaceNodeResults() uses LowerFP_TO_INT as
custom lowering for FP_TO_SINT during type legalization, without
checking whether the input type is handled by that routine.
LowerFP_TO_INT requires the input to be f32 or f64, so we fail when
the input is ppcf128.

I'm leaving the test case from the initial fix (r185821) in place, and
adding the new test as another crash-only check.

llvm-svn: 185959
2013-07-09 18:50:20 +00:00
Stephen Lin
59ba368813 Attempt to appease buildbot after r185956 by explicitly turning setting -fma,-fma4 attrs (I'm assuming they're set because the bot is running on machine that has one or the other.)
llvm-svn: 185958
2013-07-09 18:41:43 +00:00
Stephen Lin
30b326010c AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and all
in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in
order to resolve the following issues with fmuladd (i.e. optional FMA)
intrinsics:

1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd
intrinsics even if the subtarget does not support FMA instructions, leading
to laughably bad code generation in some situations.

2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128,
resulting in a call to a software fp128 FMA implementation.

3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types
like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize,
etc. to types that support hardware FMAs.

The function has also been slightly renamed for consistency and to force a
merge/build conflict for any out-of-tree target implementing it. To resolve,
see comments and fixed in-tree examples.

llvm-svn: 185956
2013-07-09 18:16:56 +00:00
Hal Finkel
9cb3ba300f Don't crash in SE dealing with ashr x, -1
ScalarEvolution::getSignedRange uses ComputeNumSignBits from ValueTracking on
ashr instructions. ComputeNumSignBits can return zero, but this case was not
handled correctly by the code in getSignedRange which was calling:
  APInt::getSignedMinValue(BitWidth).ashr(NS - 1)
with NS = 0, resulting in an assertion failure in APInt::ashr.

Now, we just return the conservative result (as with NS == 1).

Another bug found by llvm-stress.

llvm-svn: 185955
2013-07-09 18:16:16 +00:00
David Majnemer
a36d20b589 ValueTracking: Fix bugs in isKnownToBeAPowerOfTwo
(add nsw x, (and x, y)) isn't a power of two if x is zero, it's zero
(add nsw x, (xor x, y)) isn't a power of two if y has bits set that aren't set in x

llvm-svn: 185954
2013-07-09 18:11:10 +00:00
Nadav Rotem
07b212b07b Set the default insert point to the first instruction, and not to end()
llvm-svn: 185953
2013-07-09 17:55:36 +00:00
Nadav Rotem
3276e11bb5 IRBuilder: add an assertion that checks if we try to get a debug loc from ->end();
llvm-svn: 185952
2013-07-09 17:54:22 +00:00
Hal Finkel
984c244d8d DAGCombine tryFoldToZero cannot create illegal types after type legalization
When folding sub x, x (and other similar constructs), where x is a vector, the
result is a vector of zeros. After type legalization, make sure that the input
zero elements have a legal type. This type may be larger than the result's
vector element type.

This was another bug found by llvm-stress.

llvm-svn: 185949
2013-07-09 17:02:45 +00:00
Ulrich Weigand
b664c03f18 [PowerPC] Revert r185476 and fix up TLS variant kinds
In the commit message to r185476 I wrote:

>The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD
>correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD.
>This causes some confusion with the asm parser, since VK_PPC_TLSGD
>is output as @tlsgd, which is then read back in as VK_TLSGD.
>
>To avoid this confusion, this patch removes the PowerPC-specific
>modifiers and uses the generic modifiers throughout.  (The only
>drawback is that the generic modifiers are printed in upper case
>while the usual convention on PowerPC is to use lower-case modifiers.
>But this is just a cosmetic issue.)

This was unfortunately incorrect, there is is fact another,
serious drawback to using the default VK_TLSLD/VK_TLSGD
variant kinds: using these causes ELFObjectWriter::RelocNeedsGOT
to return true, which in turn causes the ELFObjectWriter to emit
an undefined reference to _GLOBAL_OFFSET_TABLE_.

This is a problem on powerpc64, because it uses the TOC instead
of the GOT, and the linker does not provide _GLOBAL_OFFSET_TABLE_,
so the symbol remains undefined.  This means shared libraries
using TLS built with the integrated assembler are currently
broken.

While the whole RelocNeedsGOT / _GLOBAL_OFFSET_TABLE_ situation
probably ought to be properly fixed at some point, for now I'm
simply reverting the r185476 commit.  Now this in turn exposes
the breakage of handling @tlsgd/@tlsld in the asm parser that
this check-in was originally intended to fix.

To avoid this regression, I'm also adding a different fix for
this problem: while common code now parses @tlsgd as VK_TLSGD,
a special hack in the asm parser translates this code to the
platform-specific VK_PPC_TLSGD that the back-end now expects.
While this is not really pretty, it's self-contained and
shouldn't hurt anything else for now.  One the underlying
problem is fixed, this hack can be reverted again.

llvm-svn: 185945
2013-07-09 16:41:09 +00:00
Vincent Lejeune
5517f57c42 R600: Do not predicated basic block with multiple alu clause
Test is not included as it is several 1000 lines long.
To test this functionnality, a test case must generate at least 2 ALU clauses,
where an ALU clause is ~110 instructions long.

NOTE: This is a candidate for the stable branch.
llvm-svn: 185943
2013-07-09 15:03:33 +00:00
Vincent Lejeune
0c1224c533 R600: Fix a rare bug where swizzle optimization returns wrong values
llvm-svn: 185942
2013-07-09 15:03:25 +00:00
Vincent Lejeune
48ea85c102 R600: Fix wrong export reswizzling
llvm-svn: 185941
2013-07-09 15:03:19 +00:00
Vincent Lejeune
d29844ad2e R600: Use DAG lowering pass to handle fcos/fsin
NOTE: This is a candidate for the stable branch.
llvm-svn: 185940
2013-07-09 15:03:11 +00:00
Vincent Lejeune
4c202a6875 R600: Print Export Swizzle
llvm-svn: 185939
2013-07-09 15:03:03 +00:00
Rafael Espindola
f574b25abe Add missing getters. They will be used in llvm-ar.
llvm-svn: 185937
2013-07-09 12:49:24 +00:00
Rafael Espindola
a60439b0f2 Archive members cannot be larger than 4GB. Return a uint32_t.
llvm-svn: 185936
2013-07-09 12:45:11 +00:00
Rafael Espindola
2a3541dfc1 We never compare iterators from two archives. Assert that.
llvm-svn: 185934
2013-07-09 12:30:10 +00:00
Rafael Espindola
852db8570d Add getHeader helper and move ToHeader to the cpp file.
llvm-svn: 185933
2013-07-09 12:22:05 +00:00
Joey Gouly
1bf5e0fbf1 Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.
llvm-svn: 185929
2013-07-09 11:26:18 +00:00
Joey Gouly
9995bf31f9 Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP.
llvm-svn: 185926
2013-07-09 11:03:21 +00:00
Alexey Samsonov
ce8937f226 Document LLVM_USE_SANITIZER CMake option
llvm-svn: 185925
2013-07-09 10:56:13 +00:00
Ulrich Weigand
bf2db94897 [PowerPC] Support ".machine any"
The PowerPC assembler is supposed to provide a directive .machine
that allows switching the supported CPU instruction set on the fly.
Since we do not yet check CPU feature sets at all and always accept
any available instruction, this is not really useful at this point.

However, it makes sense to accept (and ignore) ".machine any" to
avoid spuriously rejecting existing assembler files that use this.

llvm-svn: 185924
2013-07-09 10:00:34 +00:00
Alexander Potapenko
9c55668f5b Revert r185872 - "Stop emitting weak symbols into the "coal" sections"
This patch broke `make check-asan` on Mac, causing ld warnings like the following one:

ld: warning: direct access in __GLOBAL__I_a to global weak symbol
___asan_mapping_scale means the weak symbol cannot be overridden at
runtime. This was likely caused by different translation units being
compiled with different visibility settings.

The resulting test binaries crashed with incorrect ASan warnings.

llvm-svn: 185923
2013-07-09 10:00:16 +00:00