Owen Anderson
11e2000c8c
Fix broken encodings for the Thumb2 LDRD/STRD instructions.
...
llvm-svn: 136942
2011-08-04 23:18:05 +00:00
Jim Grosbach
767e9d16e6
ARM refactoring assembly parsing of memory address operands.
...
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
llvm-svn: 136845
2011-08-03 23:50:40 +00:00
Owen Anderson
cc4c746c65
Split am2offset into register addend and immediate addend forms, necessary for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE.
...
llvm-svn: 136141
2011-07-26 20:54:26 +00:00
Jim Grosbach
4681ef2468
ARM fix for LDREX source register encoding.
...
rdar://9842203
llvm-svn: 136102
2011-07-26 17:44:46 +00:00
Jim Grosbach
6fbee17fef
ARM assembly parsing and encoding for SWP[B] instructions.
...
llvm-svn: 136098
2011-07-26 17:15:11 +00:00
Jim Grosbach
3cd3217e6c
Clean up the ARM asm parser a bit.
...
No intendeded functional change. Just cleaning up a bit to make things more
self-consistent in layout and style.
llvm-svn: 136095
2011-07-26 17:10:22 +00:00
Jim Grosbach
07bb1d91c0
More simple cleanup of ARM asm operand definitions.
...
llvm-svn: 135958
2011-07-25 20:38:18 +00:00
Jim Grosbach
f45795436a
Make assembly parser method names more consistent.
...
llvm-svn: 135950
2011-07-25 20:14:50 +00:00
Jim Grosbach
0fe45ec0ed
ARM assembly parsing and encoding for SETEND instruction.
...
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
llvm-svn: 135776
2011-07-22 17:44:50 +00:00
Owen Anderson
e34471d064
Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn necessitates a lot of changes to related bits.
...
llvm-svn: 135722
2011-07-21 23:38:37 +00:00
Jim Grosbach
5a0277bab7
ARM assembly parsing and encoding for PKHBT and PKHTB instructions.
...
llvm-svn: 135682
2011-07-21 17:23:04 +00:00
Jim Grosbach
572868e146
ARM PKH shift ammount operand printing tweaks.
...
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0 " and prepares for correct asm parsing of these
operands.
llvm-svn: 135626
2011-07-20 21:40:26 +00:00
Jim Grosbach
fbaaa3ae98
Tidy up a bit.
...
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.
llvm-svn: 135617
2011-07-20 20:49:03 +00:00
Jim Grosbach
94a88152c9
ARM: Tidy up representation of PKH instruction.
...
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.
llvm-svn: 135616
2011-07-20 20:32:09 +00:00
Owen Anderson
ad0f17c102
Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM.
...
llvm-svn: 135524
2011-07-19 21:06:00 +00:00
Owen Anderson
c68f12ff30
Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
...
llvm-svn: 135106
2011-07-13 23:22:26 +00:00
Jim Grosbach
385d9a3e57
Parameterize away the ARM T1Cop class.
...
llvm-svn: 135082
2011-07-13 21:17:59 +00:00
Jim Grosbach
d3b15141b8
Fix predicates for Thumb co-processor instructions.
...
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.
llvm-svn: 135081
2011-07-13 21:14:23 +00:00
Jim Grosbach
5dd61ef1e9
Use TableGen'erated pseudo lowering for ARM.
...
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.
More conversions to come.
llvm-svn: 134705
2011-07-08 17:40:42 +00:00
Jim Grosbach
9863be57e0
Mark ARM pseudo-instructions as isPseudo.
...
This allows us to remove the (bogus and unneeded) encoding information from
the pseudo-instruction class definitions. All of the pseudos that haven't
been converted yet and still need encoding information instance from the normal
instruction classes and explicitly set isCodeGenOnly, and so are distinct
from this change.
llvm-svn: 134540
2011-07-06 21:35:46 +00:00
Eric Christopher
0e12efbed1
Make the branch encoding for tBcc more obvious that it's a 4-byte opcode
...
followed by a conditional and imm8.
llvm-svn: 132179
2011-05-27 03:50:53 +00:00
Jim Grosbach
db1450056a
80 columns.
...
llvm-svn: 131649
2011-05-19 17:34:53 +00:00
Bruno Cardoso Lopes
9dd575e4a9
Add a few ARM coprocessor intrinsics. Testcases included
...
llvm-svn: 130763
2011-05-03 17:29:22 +00:00
Johnny Chen
b3130a03a7
Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.
...
Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
llvm-svn: 129015
2011-04-06 18:27:46 +00:00
Bruno Cardoso Lopes
74363376e4
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
...
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
index mode to print.
- Testcases.
llvm-svn: 128832
2011-04-04 17:18:19 +00:00
Bruno Cardoso Lopes
d285a7f27e
Apply again changes to support ARM memory asm parsing. I removed
...
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
llvm-svn: 128689
2011-03-31 23:26:08 +00:00
Bruno Cardoso Lopes
392dbfd384
Revert r128632 again, until I figure out what break the tests
...
llvm-svn: 128635
2011-03-31 15:54:36 +00:00
Bruno Cardoso Lopes
3b2f5421ac
Reapply r128585 without generating a lib depedency cycle. An updated log:
...
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
addrmode2.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
llvm-svn: 128632
2011-03-31 14:52:28 +00:00
Matt Beaumont-Gay
325e16f668
Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"
...
This revision introduced a dependency cycle, as nlewycky mentioned by email.
llvm-svn: 128597
2011-03-31 00:39:16 +00:00
Owen Anderson
d4e1a2f2b6
Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler.
...
llvm-svn: 128587
2011-03-30 23:45:29 +00:00
Bruno Cardoso Lopes
cebbf7fe68
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
...
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser
llvm-svn: 128585
2011-03-30 23:32:32 +00:00
Bruno Cardoso Lopes
a5de5df6d8
Add asm parsing support w/ testcases for strex/ldrex family of instructions
...
llvm-svn: 128236
2011-03-24 21:04:58 +00:00
Jim Grosbach
6ee5aef028
Remove some dead patterns.
...
llvm-svn: 127601
2011-03-14 18:34:35 +00:00
Jim Grosbach
db549a7f6c
Pseudo-instructions are codegenonly by definition.
...
llvm-svn: 127420
2011-03-10 19:06:39 +00:00
Bill Wendling
958e854f40
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
...
expand the testing of the narrowing shift right instructions.
No functionality change.
llvm-svn: 127193
2011-03-07 23:38:41 +00:00
Bill Wendling
304dda7810
Narrow right shifts need to encode their immediates differently from a normal
...
shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
llvm-svn: 126723
2011-03-01 01:00:59 +00:00
Evan Cheng
98e040ea71
Change VFPNeonA8 definition to make the code easier to read.
...
llvm-svn: 126298
2011-02-23 02:35:33 +00:00
Evan Cheng
f540b0e0f6
VFP single precision arith instructions can go down to NEON pipeline, but on Cortex-A8 only.
...
llvm-svn: 126238
2011-02-22 19:53:14 +00:00
Bruno Cardoso Lopes
ad05904e0b
Add assembly parsing support for "msr" and also fix its encoding. Also add
...
testcases for the disassembler to make sure it still works for "msr".
llvm-svn: 125948
2011-02-18 19:45:59 +00:00
Evan Cheng
d3928a2c3a
Some single precision VFP instructions may be executed on NEON pipeline, but not double precision ones.
...
llvm-svn: 125624
2011-02-16 00:35:02 +00:00
Bruno Cardoso Lopes
e65a98b127
Fix encoding and add parsing support for the arm/thumb CPS instruction:
...
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
llvm-svn: 125489
2011-02-14 13:09:44 +00:00
Jim Grosbach
c359122d78
AsmMatcher custom operand parser failure enhancements.
...
Teach the AsmMatcher handling to distinguish between an error custom-parsing
an operand and a failure to match. The former should propogate the error
upwards, while the latter should continue attempting to parse with
alternative matchers.
Update the ARM asm parser accordingly.
llvm-svn: 125426
2011-02-12 01:34:40 +00:00
Bruno Cardoso Lopes
0ce5b0f4a8
Add support for parsing dmb/dsb instructions
...
llvm-svn: 125055
2011-02-07 22:09:15 +00:00
Bruno Cardoso Lopes
75712e8a7a
Add mcr*2 and mr*c2 support to thumb2 targets
...
llvm-svn: 123919
2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes
f377d1721e
Add mcr* and mr*c support to thumb targets
...
llvm-svn: 123917
2011-01-20 16:35:57 +00:00
Jim Grosbach
6de3a4f76f
Add a FIXME.
...
llvm-svn: 123769
2011-01-18 19:59:19 +00:00
Jim Grosbach
8278d5692a
The new t2LEApcrel* pseudo instructions need the size specified.
...
rdar://8768390
llvm-svn: 121876
2010-12-15 18:48:45 +00:00
Owen Anderson
e85fabac75
Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and friends.
...
llvm-svn: 121585
2010-12-10 22:32:08 +00:00
Jim Grosbach
5696d964ca
Tidy up.
...
llvm-svn: 121522
2010-12-10 20:51:35 +00:00
Jim Grosbach
401391235f
Trailing whitespace.
...
llvm-svn: 121521
2010-12-10 20:47:29 +00:00
Owen Anderson
a23e10f29d
Fix Thumb2 encoding of the S bit.
...
llvm-svn: 121182
2010-12-07 20:50:15 +00:00
Jim Grosbach
c79c6290ee
The ARM AsmMatcher needs to know that the CCOut operand is a register value,
...
not an immediate. It stores either ARM::CPSR or reg0.
llvm-svn: 121018
2010-12-06 18:21:12 +00:00
Bill Wendling
d85ff071c0
Add a post encoder method to the VFP instructions to convert them to the Thumb2
...
encoding if we're in that mode.
llvm-svn: 120608
2010-12-01 21:54:50 +00:00
Owen Anderson
8802c68592
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
...
llvm-svn: 120589
2010-12-01 19:18:46 +00:00
Bill Wendling
4fc1c4ee84
General cleanups of comments.
...
llvm-svn: 120536
2010-12-01 02:42:55 +00:00
Bill Wendling
ccfea264ff
s/T1pIEncode/T1pILdStEncode/g
...
s/T1pIEncodeImm/T1pILdStEncodeImm/g
llvm-svn: 120524
2010-12-01 01:38:08 +00:00
Bill Wendling
517dd72f06
Renaming variables to coincide with documentation. No functionality change.
...
llvm-svn: 120522
2010-12-01 01:32:02 +00:00
Bill Wendling
6a48b15c80
Rename operands to match ARM documentation. No functionality change.
...
llvm-svn: 120500
2010-11-30 23:54:45 +00:00
Bill Wendling
745e2de9dc
Inline classes that were used in only one place.
...
llvm-svn: 120488
2010-11-30 23:16:25 +00:00
Bill Wendling
e85934f8a5
* Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as
...
t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
llvm-svn: 120482
2010-11-30 22:57:21 +00:00
Jim Grosbach
cb8193b99e
Pseudo-ize BX_CALL and friends. Remove dead instruction format classes.
...
rdar://8685712
llvm-svn: 120438
2010-11-30 18:30:19 +00:00
Owen Anderson
b6e1c56c79
Correct Thumb2 encodings for a much wider range of loads and stores.
...
llvm-svn: 120364
2010-11-30 00:14:31 +00:00
Jim Grosbach
b796df67e9
Parameterize ARMPseudoInst size property.
...
llvm-svn: 120353
2010-11-29 23:48:41 +00:00
Jim Grosbach
3e84f9d6cb
ARM Pseudo-ize tBR_JTr.
...
llvm-svn: 120310
2010-11-29 19:32:47 +00:00
Jim Grosbach
9e2ed21ad0
Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.
...
llvm-svn: 120303
2010-11-29 18:37:44 +00:00
Jim Grosbach
4d6c419ea2
trailing whitespace
...
llvm-svn: 119863
2010-11-19 22:42:55 +00:00
Jim Grosbach
a7213faf85
Add ARM encoding information for STRD.
...
llvm-svn: 119852
2010-11-19 22:14:31 +00:00
Jim Grosbach
33930ff560
Factor out operand encoding bits for ARM addressing mode 2 store instructions.
...
llvm-svn: 119846
2010-11-19 21:35:06 +00:00
Jim Grosbach
b58de2a8c7
Delete another dead class.
...
llvm-svn: 119844
2010-11-19 21:16:08 +00:00
Jim Grosbach
dc695e7de2
whitespace tweak.
...
llvm-svn: 119843
2010-11-19 21:14:37 +00:00
Jim Grosbach
edef95dc56
Refactor PICSTR* instructions to really be pseudos. Nuke dead classes.
...
llvm-svn: 119841
2010-11-19 21:14:02 +00:00
Jim Grosbach
a57ac3e282
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes.
...
llvm-svn: 119840
2010-11-19 21:07:51 +00:00
Jim Grosbach
9e50b14e34
Add ARM binary encoding information for the rest of the indexed loads.
...
llvm-svn: 119821
2010-11-19 19:41:26 +00:00
Jim Grosbach
7a92d84b46
Remove dead code.
...
llvm-svn: 119815
2010-11-19 18:18:37 +00:00
Jim Grosbach
c2ac477e54
ARM LDRD binary encoding.
...
llvm-svn: 119812
2010-11-19 18:16:46 +00:00
Jim Grosbach
0651dc456a
Add ARM encoding information for LDRH post-increment.
...
llvm-svn: 119743
2010-11-18 21:43:37 +00:00
Owen Anderson
eec8c82d32
Fill out the set of Thumb2 multiplication operator encodings.
...
llvm-svn: 119733
2010-11-18 20:32:18 +00:00
Jim Grosbach
fd0bab72a7
ARMPseudoInst instructions should default to being considered a single 4-byte
...
instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274
llvm-svn: 119713
2010-11-18 18:01:40 +00:00
Jim Grosbach
2f9a2efb3c
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
...
the operand to the pattern.
llvm-svn: 119607
2010-11-18 01:38:26 +00:00
Jim Grosbach
205e0345c1
Add FIXME.
...
llvm-svn: 119603
2010-11-18 01:20:48 +00:00
Jim Grosbach
a42e2b0fcb
Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not
...
just pretend to be.
llvm-svn: 119602
2010-11-18 01:15:56 +00:00
Jim Grosbach
42d103250b
Refactor a few ARM load instructions to better parameterize things and re-use
...
common encoding information.
llvm-svn: 119598
2010-11-18 00:46:58 +00:00
Jim Grosbach
b640b6a7b4
More ARM encoding bits. LDRH now encodes properly.
...
llvm-svn: 119529
2010-11-17 18:11:11 +00:00
Bill Wendling
0b16ba97fd
Add binary emission stuff for VLDM/VSTM. This reuses the
...
"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.
llvm-svn: 119435
2010-11-17 00:45:23 +00:00
Bill Wendling
2ac47f0959
- Remove dead patterns.
...
- Add encodings to the *LDMIA_RET instrs. Probably not needed...
llvm-svn: 119323
2010-11-16 02:08:45 +00:00
Jim Grosbach
7aabb8c5ee
ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
...
llvm-svn: 119180
2010-11-15 20:47:07 +00:00
Chris Lattner
b2daeac125
add fields to the .td files unconditionally, simplifying tblgen a bit.
...
Switch the ARM backend to use 'let' instead of 'set' with this change.
llvm-svn: 119120
2010-11-15 05:19:05 +00:00
Bill Wendling
aa9ca6fcca
Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
...
future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.
llvm-svn: 118995
2010-11-13 09:09:38 +00:00
Jim Grosbach
03eb1993ea
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
...
flag for the LDRT/STRT family instructions as a side effect.
llvm-svn: 118955
2010-11-13 00:35:48 +00:00
Jim Grosbach
eaaf8294a5
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
...
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
llvm-svn: 118925
2010-11-12 21:28:15 +00:00
Evan Cheng
b565d1acf9
Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.
...
llvm-svn: 118922
2010-11-12 20:32:20 +00:00
Jim Grosbach
160cc37f73
Kill more unused stuff.
...
llvm-svn: 118921
2010-11-12 19:27:45 +00:00
Jim Grosbach
8bb507dd6b
Remove unused class.
...
llvm-svn: 118919
2010-11-12 19:24:53 +00:00
Jim Grosbach
cbab1ea04e
Encoding for ARM LDRSB instructions.
...
llvm-svn: 118905
2010-11-12 17:52:59 +00:00
Owen Anderson
85cf1b8ff5
Fill out support for Thumb2 encodings of NEON instructions.
...
llvm-svn: 118854
2010-11-11 23:12:55 +00:00
Owen Anderson
0913dac245
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
...
llvm-svn: 118843
2010-11-11 21:36:43 +00:00
Owen Anderson
f43f09f6f6
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
...
More tests to come.
llvm-svn: 118819
2010-11-11 19:07:48 +00:00
Jim Grosbach
cfc32e3b5a
Encoding for ARM LDRSH_POST.
...
llvm-svn: 118794
2010-11-11 16:55:29 +00:00
Jim Grosbach
8cb10f8def
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
...
llvm-svn: 118767
2010-11-11 01:55:59 +00:00
Jim Grosbach
3b13f9013c
ARM STRH encoding information.
...
llvm-svn: 118757
2010-11-11 01:09:40 +00:00