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261 Commits

Author SHA1 Message Date
Bob Wilson
95064e348a Add ARM codegen for indirect branches. 
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577
 2009-10-30 05:45:42 +00:00
Bob Wilson
af37728221 Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the 
opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411
 2009-10-28 18:26:41 +00:00
Bob Wilson
b709aa6b3c Add an indirect branch pattern for ARM. Testcase will be coming soon. 
llvm-svn: 85355
 2009-10-28 00:37:03 +00:00
Johnny Chen
b746e248cd Similar to r85280, do not clear the "S" bit for RSBri and RSBrs. 
llvm-svn: 85299
 2009-10-27 20:51:49 +00:00
Johnny Chen
d63b06e0f6 Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between 
BL_pred and BLr9_pred.

llvm-svn: 85297
 2009-10-27 20:45:15 +00:00
Bob Wilson
5ca76e601f Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI" 
instruction format that already takes care of setting this.

llvm-svn: 85280
 2009-10-27 19:52:03 +00:00
Johnny Chen
528c66b30c Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10}) 
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.

llvm-svn: 85271
 2009-10-27 18:44:24 +00:00
Evan Cheng
a883c2ebb7 Change ARM asm strings to separate opcode from operands with a tab instead of a space. 
llvm-svn: 85178
 2009-10-26 23:45:59 +00:00
Bob Wilson
5a870f848e Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding 
bits.  Johnny, please review -- I do not have a good track record of getting
these right.

llvm-svn: 85173
 2009-10-26 22:59:12 +00:00
Bob Wilson
32ee4ee163 Add more ARM instruction encodings for 's' bit set and "rs" register encoding 
bits.  Patch by Johnny Chen.

llvm-svn: 85167
 2009-10-26 22:34:44 +00:00
Jim Grosbach
452de96b04 Improve handling of immediates by splitting 32-bit immediates into two 16-bit 
immediate operands when they will fit into the using instruction.

llvm-svn: 84778
 2009-10-21 20:44:34 +00:00
Evan Cheng
275a09e55d Match more patterns to movt. 
llvm-svn: 84751
 2009-10-21 08:15:52 +00:00
Chris Lattner
976978de4a implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :) 
llvm-svn: 84573
 2009-10-20 00:40:56 +00:00
Bob Wilson
c9b704f66c Set instruction encoding bits 4 and 7 for ARM register-register and 
register-shifted-register instructions.  Patch by Johnny Chen.

llvm-svn: 84124
 2009-10-14 19:00:24 +00:00
Sandeep Patel
1584038783 Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
llvm-svn: 84009
 2009-10-13 18:59:48 +00:00
Bob Wilson
747a6c0795 Add some ARM instruction encoding bits. 
Patch by Johnny Chen.

llvm-svn: 83983
 2009-10-13 17:35:30 +00:00
Bob Wilson
53fb652143 Fix a tab. Thanks to Johnny Chen for pointing it out. 
llvm-svn: 83973
 2009-10-13 15:27:23 +00:00
Dan Gohman
168ae2c7d5 Mark the LDR instruction with isReMaterializable, as it is rematerializable 
when loading from an invariant memory location.

llvm-svn: 83688
 2009-10-09 23:28:27 +00:00
Bob Wilson
21056e1c2e Fix a comment typo. 
Patch by Johnny Chen.

llvm-svn: 83407
 2009-10-06 20:18:46 +00:00
Evan Cheng
241092d89f Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, 
ld / st pairs, etc.

llvm-svn: 83197
 2009-10-01 08:22:27 +00:00
Evan Cheng
4dd7d7156e Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions. 
llvm-svn: 83191
 2009-10-01 01:33:39 +00:00
Jim Grosbach
2d057f09e8 Add "isBarrier = 1" to return instructions. 
Patch by Sylvere Teissier.

llvm-svn: 83135
 2009-09-30 01:35:11 +00:00
Evan Cheng
54a1a87862 Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo 
instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982
 2009-09-28 09:14:39 +00:00
Anton Korobeynikov
2e54b03741 Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument. 
Disable rematting of it for now.

llvm-svn: 82975
 2009-09-28 07:26:46 +00:00
Anton Korobeynikov
189ce11684 Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. 
This should be better than single load from constpool.

llvm-svn: 82948
 2009-09-27 23:52:58 +00:00
Evan Cheng
a0bf864b0e Fix arm jit encoding bug introduced by 75048. Some instructions', e.g. MOVi, bit 25 should be set. 
llvm-svn: 81310
 2009-09-09 01:47:07 +00:00
David Goodwin
0dd9e9edb4 Calls clobber FPSCR. 
llvm-svn: 80956
 2009-09-03 22:12:28 +00:00
David Goodwin
70557af33a RRX reads CPSR. 
llvm-svn: 80699
 2009-09-01 18:32:09 +00:00
Evan Cheng
d53546a6cd Print a nl before pic labels so they start at a new line. This makes assembly more readable. 
llvm-svn: 80350
 2009-08-28 06:59:37 +00:00
Misha Brukman
25e2b59ec6 STRD and LDRD require ARMv5TE, not just ARMv5T. 
See http://llvm.org/PR4687 for more info and links.

llvm-svn: 80244
 2009-08-27 14:14:21 +00:00
Bob Wilson
9482015a0a Rename ARM "lane_cst" operands to "nohash_imm" since they are used for 
several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676
 2009-08-21 21:58:55 +00:00
David Goodwin
d57f44783c Update Cortex-A8 instruction itineraries for integer instructions. 
llvm-svn: 79436
 2009-08-19 18:00:44 +00:00
Jim Grosbach
361b7db9bd Add missing defs of R2 and D1. 
llvm-svn: 78918
 2009-08-13 16:59:44 +00:00
David Goodwin
dd797db6bd Finalize itineraries for cortex-a8 integer multiply 
llvm-svn: 78908
 2009-08-13 15:51:13 +00:00
Jim Grosbach
6511e74282 Remove unnecessary newline 
llvm-svn: 78905
 2009-08-13 15:12:16 +00:00
Jim Grosbach
aba7f6b60b Correct comment wording 
llvm-svn: 78904
 2009-08-13 15:11:43 +00:00
David Goodwin
90e7f9873c Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one. 
llvm-svn: 78827
 2009-08-12 18:31:53 +00:00
Jim Grosbach
77d5653945 register naming cleanup (s/ip/r12/) 
llvm-svn: 78806
 2009-08-12 15:21:13 +00:00
Owen Anderson
48f2f0ae72 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
 2009-08-11 20:47:22 +00:00
Jim Grosbach
c9a1dd9291 SjLj based exception handling unwinding support. This patch is nasty, brutish 
and short. Well, it's kinda short. Definitely nasty and brutish.

The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.

Built on Darwin and verified no llvm-core "make check" regressions.

llvm-svn: 78625
 2009-08-11 00:09:57 +00:00
Owen Anderson
b4bce99769 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
llvm-svn: 78610
 2009-08-10 22:56:29 +00:00
Anton Korobeynikov
44fa9f179c Use subclassing to print lane-like immediates (w/o hash) eliminating 
'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514
 2009-08-08 23:10:41 +00:00
Anton Korobeynikov
ae22c37afb Use VLDM / VSTM to spill/reload 128-bit Neon registers 
llvm-svn: 78468
 2009-08-08 13:35:48 +00:00
David Goodwin
3aafcc1dd2 Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary. 
llvm-svn: 78321
 2009-08-06 16:52:47 +00:00
David Goodwin
99adffe5f2 Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. 
llvm-svn: 78081
 2009-08-04 17:53:06 +00:00
Evan Cheng
90a1ca6e17 Make sure Thumb2 uses the right call instructions. 
llvm-svn: 77507
 2009-07-29 21:26:42 +00:00
Evan Cheng
c8d3891c87 - Fix an obvious copy and paste error. 
- Darwin Thumb2 call clobbers r9.

llvm-svn: 77500
 2009-07-29 20:10:36 +00:00
Evan Cheng
fc846dd401 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
llvm-svn: 77422
 2009-07-29 02:18:14 +00:00
Evan Cheng
cf483eb0c0 In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
llvm-svn: 77364
 2009-07-28 20:53:24 +00:00
Evan Cheng
d615e606c4 Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024
 2009-07-25 00:33:29 +00:00