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26 Commits

Author SHA1 Message Date
Akira Hatanaka
c05b5c3dae [mips] Rename accumulator register classes and FP register operands. 
llvm-svn: 188020
 2013-08-08 21:54:26 +00:00
Akira Hatanaka
1290d365ec [mips] Rename register classes CPURegs and CPU64Regs. 
llvm-svn: 187832
 2013-08-06 23:08:38 +00:00
Akira Hatanaka
4c91ec2ed9 [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of 
instructions defined in MipsInstrInfo.td as codegen-only instructions.

llvm-svn: 187828
 2013-08-06 23:01:10 +00:00
Akira Hatanaka
d0c19bc118 [mips] Define instruction itineraries IIArith and IILogic. 
No functionality change.

llvm-svn: 187468
 2013-07-31 00:55:34 +00:00
Vladimir Medic
aafcb477fd This patch implements parsing of mips FCC register operands. The example instructions have been added to test files. 
llvm-svn: 187410
 2013-07-30 10:12:14 +00:00
Akira Hatanaka
689acaf88f [mips] Fix FP conditional move instructions to have explicit FP condition code 
register operands.

llvm-svn: 187242
 2013-07-26 20:51:20 +00:00
Akira Hatanaka
e6ef926882 [mips] Fix floating point branch, comparison, and conditional move instructions 
to have register FCC0 (the first floating point condition code register) in
their Uses/Defs list.

No intended functionality change.

llvm-svn: 187233
 2013-07-26 19:01:56 +00:00
Vladimir Medic
e3aeddca47 This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. 
llvm-svn: 186397
 2013-07-16 10:07:14 +00:00
Akira Hatanaka
d2f7ed089c [mips] Fix inefficient code generation. 
This patch eliminates the need to emit a constant move instruction when this
pattern is matched:

(select (setgt a, Constant), T, F)

The pattern above effectively turns into this:

(conditional-move (setlt a, Constant + 1), F, T)

llvm-svn: 176384
 2013-03-01 21:52:08 +00:00
Akira Hatanaka
a064b57260 Fix indentation. 
llvm-svn: 176380
 2013-03-01 21:22:21 +00:00
Akira Hatanaka
014ed59039 [mips] Refactor conditional move instructions. 
llvm-svn: 171511
 2013-01-04 19:16:38 +00:00
Akira Hatanaka
9b0bb584d7 [mips] Delete all floating point instruction classes that are no longer used. 
No functionality change.

llvm-svn: 170084
 2012-12-13 02:05:02 +00:00
Akira Hatanaka
8a20e0e5f7 [mips] Modify definitions of floating point conditional move instructions. 
No functionality change.

llvm-svn: 170080
 2012-12-13 01:41:15 +00:00
Akira Hatanaka
57161323ed [mips] Shorten predicate name. 
llvm-svn: 169579
 2012-12-07 03:06:09 +00:00
Akira Hatanaka
9894b24617 [mips] Remove unnecessary predicates. 
llvm-svn: 169577
 2012-12-07 03:01:24 +00:00
Akira Hatanaka
d1b2b96ed5 1. introduce MipsPat in place of Pat in order to exclude those from 
being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered

Patch by Reed Kotler.

llvm-svn: 158470
 2012-06-14 21:03:23 +00:00
Akira Hatanaka
2a600ff5f4 This patch adds a predicate to existing mips32 and mips64 so that those 
instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234
 2012-05-22 03:10:09 +00:00
Akira Hatanaka
574e68feec Add another peephole pattern for conditional moves. 
llvm-svn: 156460
 2012-05-09 02:29:29 +00:00
Akira Hatanaka
ecb1cd1ce4 Add disassembler to MIPS. 
Patch by Vladimir Medic. 

llvm-svn: 154935
 2012-04-17 18:03:21 +00:00
Akira Hatanaka
cecb440c11 Revert r153924. There were buildbot failures. 
llvm-svn: 153925
 2012-04-03 02:51:09 +00:00
Akira Hatanaka
058b0cfb55 MIPS disassembler support. 
Patch by Vladimir Medic.

llvm-svn: 153924
 2012-04-03 02:20:58 +00:00
Jia Liu
bdcd314be3 remove blanks, and some code format 
llvm-svn: 151625
 2012-02-28 07:46:26 +00:00
Jia Liu
ecc08b8cfe add Emacs tag and fix some comment error in file headers 
llvm-svn: 150775
 2012-02-17 01:23:50 +00:00
Bruno Cardoso Lopes
edc2e30d42 Final patch that completes old JIT support for Mips: 
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378
 2011-10-18 17:50:36 +00:00
Akira Hatanaka
4939842b5a Add definitions of conditional moves with 64-bit operands. Comment out code for 
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226
 2011-10-17 18:53:29 +00:00
Akira Hatanaka
e8cb50da87 Move class and instruction definitions for conditional moves to a seperate file. 
llvm-svn: 142220
 2011-10-17 18:43:19 +00:00