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51732 Commits

Author SHA1 Message Date
Francis Visoiu Mistrih
319b50aebd [AArch64] Keep track of MIFlags in the LoadStoreOptimizer
Merging:

* $x26, $x25 = frame-setup LDPXi $sp, 0
* $sp = frame-destroy ADDXri $sp, 64, 0

into an LDPXpost should preserve the flags from both instructions as
following:

* frame-setup frame-destroy LDPXpost

Differential Revision: https://reviews.llvm.org/D44446

llvm-svn: 327533
2018-03-14 17:10:58 +00:00
Craig Topper
d6a1996dad [X86] Teach X86TargetLowering::targetShrinkDemandedConstant to set non-demanded bits if it helps created an and mask that can be matched as a zero extend.
I had to modify the bswap recognition to allow unshrunk masks to make this work.

Fixes PR36689.

Differential Revision: https://reviews.llvm.org/D44442

llvm-svn: 327530
2018-03-14 16:55:15 +00:00
Simon Pilgrim
3488806962 [X86][AVX] Use WriteFShuffleLd for broadcast reg-mem instructions
They shouldn't be treated as pure loads.

Found while investigating D44428

llvm-svn: 327524
2018-03-14 15:47:08 +00:00
Arnold Schwaighofer
4a17b3df7a SjLjEHPrepare: Don't reg-to-mem swifterror values
swifterror llvm values model the swifterror register as memory at the
LLVM IR level. ISel will perform adhoc mem-to-reg on them. swifterror
values are constraint in how they can be used. Spilling them to memory
is not allowed.

SjLjEHPrepare tried to lower swifterror values to memory which is
unecessary since the back-end will spill and reload the register as
neccessary (as long as clobbering calls are marked as such which is the
case here) and further leads to invalid IR because swifterror values
can't be stored to memory.

rdar://38164004

llvm-svn: 327521
2018-03-14 15:44:07 +00:00
Alexander Ivchenko
4661c1b4e5 [GlobalIsel][X86] Support for G_SDIV instruction
Reviewed By: igorb

Differential Revision: https://reviews.llvm.org/D44430

llvm-svn: 327520
2018-03-14 15:41:11 +00:00
Petar Jovanovic
0510f66dad [mips] Add support for CRC ASE
This includes

  Instructions: crc32b, crc32h, crc32w, crc32d,
                crc32cb, crc32ch, crc32cw, crc32cd

  Assembler directives: .set crc, .set nocrc, .module crc, .module nocrc

  Attribute: crc

  .MIPS.abiflags: CRC (0x8000)

Patch by Vladimir Stefanovic.

Differential Revision: https://reviews.llvm.org/D44176

llvm-svn: 327511
2018-03-14 14:13:31 +00:00
Simon Pilgrim
2dcfe7cbde [X86][Btver2] Fix YMM shuffle, permute and permutevar scheduler costs
Account for ymm double pumping and add proper pshufb/permutevar support

llvm-svn: 327510
2018-03-14 14:05:19 +00:00
Teresa Johnson
1ab7e0a34c [LTO/gold] Support --wrap
Summary:
(Restores r327459 with handling for old plugin-api.h)
Utilize new gold plugin api interface for obtaining --wrap option
arguments, and LTO API handling (added for --wrap support in lld LTO),
to mark symbols so that LTO does not optimize them inappropriately.

Note the test cases will be in a new gold test subdirectory that
is dependent on the next release of gold which will contain the new
interfaces.

Reviewers: pcc, tmsriram

Subscribers: mehdi_amini, llvm-commits, inglorion

Differential Revision: https://reviews.llvm.org/D44235

llvm-svn: 327506
2018-03-14 13:26:18 +00:00
Simon Pilgrim
b11ab1c3fb [X86][SSE] Use WriteFShuffleLd for MOVDDUP/MOVSHDUP/MOVSLDUP reg-mem instructions
They shouldn't be treated as pure loads.

Found while investigating D44428

llvm-svn: 327505
2018-03-14 13:22:56 +00:00
Martin Storsjo
ee100c3673 [AArch64] Don't produce R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
Support for this relocation is missing in both LLD and GNU binutils
at the moment.

This reverts the ELF parts of SVN r327316.

llvm-svn: 327503
2018-03-14 13:09:10 +00:00
Alexander Ivchenko
1e41ef36f6 [GlobalISel][X86] Support G_LSHR/G_ASHR/G_SHL
Support G_LSHR/G_ASHR/G_SHL. We have 3 variance for
shift instructions : shift gpr, shift imm, shift 1.
Currently GlobalIsel TableGen generate patterns for
shift imm and shift 1, but with shiftCount i8.
In G_LSHR/G_ASHR/G_SHL like LLVM-IR both arguments
has the same type, so for now only shift i8 can use
auto generated TableGen patterns.

The support of G_SHL/G_ASHR enables tryCombineSExt
from LegalizationArtifactCombiner.h to hit, which
results in different legalization for the following tests:
    LLVM :: CodeGen/X86/GlobalISel/ext-x86-64.ll
    LLVM :: CodeGen/X86/GlobalISel/gep.ll
    LLVM :: CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir

-; X64-NEXT:    movsbl %dil, %eax
+; X64-NEXT:    movl $24, %ecx
+; X64-NEXT:    # kill: def $cl killed $ecx
+; X64-NEXT:    shll %cl, %edi
+; X64-NEXT:    movl $24, %ecx
+; X64-NEXT:    # kill: def $cl killed $ecx
+; X64-NEXT:    sarl %cl, %edi
+; X64-NEXT:    movl %edi, %eax

..which is not optimal and should be addressed later.

Rework of the patch by igorb

Reviewed By: igorb

Differential Revision: https://reviews.llvm.org/D44395

llvm-svn: 327499
2018-03-14 11:23:57 +00:00
Nicolai Haehnle
2079f988a9 TableGen: Add !ne, !le, !lt, !ge, and !gt comparisons
Change-Id: I8e2ece677268972d578a787467f7ef52a1f33a71

Differential revision: https://reviews.llvm.org/D44114

llvm-svn: 327496
2018-03-14 11:00:57 +00:00
Nicolai Haehnle
1faf7228d7 TableGen: Allow dag operators to be resolved late
Change-Id: I51bb80fd5c48c8ac441ab11e43d43c1b91b4b590

Differential revision: https://reviews.llvm.org/D44113

llvm-svn: 327495
2018-03-14 11:00:48 +00:00
Nicolai Haehnle
5962b8bbf7 TableGen: Type-check BinOps
Additionally, allow more than two operands to !con, !add, !and, !or
in the same way as is already allowed for !listconcat and !strconcat.

Change-Id: I9659411f554201b90cd8ed7c7e004d381a66fa93

Differential revision: https://reviews.llvm.org/D44112

llvm-svn: 327494
2018-03-14 11:00:43 +00:00
Nicolai Haehnle
bf9d16116d TableGen: Allow ? in lists
This makes using !dag more convenient in some cases.

Change-Id: I0a8c35e15ccd1ecec778fd1c8d64eee38d74517c

Differential revision: https://reviews.llvm.org/D44111

llvm-svn: 327493
2018-03-14 11:00:33 +00:00
Nicolai Haehnle
fb41efa751 TableGen: Add !dag function for construction
This allows constructing DAG nodes with programmatically determined
names, and can simplify constructing DAG nodes in other cases as
well.

Also, add documentation and some very simple tests for the already
existing !con.

Change-Id: Ida61cd82e99752548d7109ce8da34d29da56a5f7

Differential revision: https://reviews.llvm.org/D44110

llvm-svn: 327492
2018-03-14 11:00:26 +00:00
Jonas Devlieghere
035fa32ff2 [dsymutil] Print architecture in warning
Make the architecture part of the warning in the DebugMapParser. This
makes things consistent with the Apple's internal version of dsymutil.

llvm-svn: 327485
2018-03-14 09:34:54 +00:00
Alexander Ivchenko
41242736b0 [GlobalIsel][X86] Support for G_ZEXT instruction
Reviewed By: igorb

Differential Revision: https://reviews.llvm.org/D44378

llvm-svn: 327482
2018-03-14 09:11:23 +00:00
Robert Widmann
da759a6ef9 [LLVM-C] Redo unnamed_address attribute bindings
Summary:
The old bindings should have used an enum instead of a boolean.  This
deprecates LLVMHasUnnamedAddr and LLVMSetUnnamedAddr , replacing them
with LLVMGetUnnamedAddress and LLVMSetUnnamedAddress respectively that do.
Though it is unlikely LLVM will gain more supported global value linker
hints, the new API can scale to accommodate this.

Reviewers: deadalnix, whitequark

Reviewed By: whitequark

Subscribers: llvm-commits, harlanhaskins

Differential Revision: https://reviews.llvm.org/D43448

llvm-svn: 327479
2018-03-14 06:45:51 +00:00
Eugene Zemtsov
6447a124e2 Disable test debuglineinfo-path on powerpc
llvm-svn: 327472
2018-03-14 02:10:07 +00:00
Eugene Zemtsov
4136000e60 grep for global functions only
llvm-svn: 327469
2018-03-14 01:07:18 +00:00
Eugene Zemtsov
b0122fe5cd Add extra output/check to debug clang-ppc64be-linux test failure
llvm-svn: 327466
2018-03-14 00:15:16 +00:00
Teresa Johnson
276b2fd403 Revert "[LTO/gold] Support --wrap"
This reverts commit r327459. The new gold plugin interface is not
available with older gold installations, leading to compile failures:
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/9109/steps/build-stage2-LLVMgold.so/logs/stdio

llvm-svn: 327465
2018-03-13 23:55:34 +00:00
Craig Topper
12eb022c45 [X86] Re-generate test to get proper capitalization of its CHECK lines. NFC
llvm-svn: 327462
2018-03-13 23:31:48 +00:00
Teresa Johnson
334153c613 [LTO/gold] Support --wrap
Summary:
Utilize new gold plugin api interface for obtaining --wrap option
arguments, and LTO API handling (added for --wrap support in lld LTO),
to mark symbols so that LTO does not optimize them inappropriately.

Note the test cases will be in a new gold test subdirectory that
is dependent on the next release of gold which will contain the new
interfaces.

Reviewers: pcc, tmsriram

Subscribers: mehdi_amini, llvm-commits, inglorion

Differential Revision: https://reviews.llvm.org/D44235

llvm-svn: 327459
2018-03-13 23:06:19 +00:00
Eugene Zemtsov
dc58ce2b0f Disable optimizations in debuglineinfo-path test
llvm-svn: 327458
2018-03-13 22:48:39 +00:00
Craig Topper
7d30a6f179 [X86] Rewrite LowerAVXCONCAT_VECTORS similar to how we handle vXi1 concats.
This better able to detect undef and zeros pieces in the concat. Or cases when only one subvector is non-zero. This allows us to avoid silly things like double inserts into progressively larger undefs.

This still builds 512 bit concats of 128 bits by building up through 256 bits first. But I don't know if that's best.

We probably want to merge this with the vXi1 concat code since they are very similar.

llvm-svn: 327454
2018-03-13 22:05:25 +00:00
Zachary Turner
75bccf43de Disable PDB injected sources test temporarily.
llvm-svn: 327451
2018-03-13 21:18:00 +00:00
Hiroshi Yamauchi
cc95710395 Simplify more cases of logical ops of masked icmps.
Summary:
For example,

((X & 255) != 0) && ((X & 15) == 8) -> ((X & 15) == 8).
((X & 7) != 0) && ((X & 15) == 8) -> false.

Reviewers: davidxl

Reviewed By: davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D43835

llvm-svn: 327450
2018-03-13 21:13:18 +00:00
Eugene Zemtsov
d954d86343 Remove explicit triple and data layout from the test
llvm-svn: 327449
2018-03-13 21:10:15 +00:00
Craig Topper
29e180a28d [DAGCombiner] Allow visitEXTRACT_SUBVECTOR to combine with BUILD_VECTORS between LegalizeVectorOps and LegalizeDAG.
BUILD_VECTORs aren't themselves legalized until LegalizeDAG so we should still be able to create an "illegal" one before that. This helps combine with BUILD_VECTORS that are introduced during LegalizeVectorOps due to unrolling.

llvm-svn: 327446
2018-03-13 20:36:28 +00:00
Eugene Zemtsov
abc24eb09c Fix debuglineinfo-path.ll
This fix is based on an assumption that some build bots are missing 'echo
-n'

llvm-svn: 327443
2018-03-13 20:06:33 +00:00
Francis Visoiu Mistrih
391493fd6e [MIR] Allow frame-setup and frame-destroy on the same instruction
Nothing prevents us from having both frame-setup and frame-destroy on
the same instruction.

When merging:
* frame-setup OPCODE1
* frame-destroy OPCODE2
into
* frame-setup frame-destroy OPCODE3

we want to be able to print and parse both flags.

llvm-svn: 327442
2018-03-13 19:53:16 +00:00
Eugene Zemtsov
1c5842b814 Temporary disable debuglineinfo-path.ll to fix build
llvm-svn: 327441
2018-03-13 19:48:31 +00:00
Sanjay Patel
9151f75422 [x86] add test for WriteZero sched class instructions; NFC
Nops should have zero latency because there is no result.
Idioms like 'xorps xmm0, xmm0' may have zero latency because 
they are handled without using an execution unit.

llvm-svn: 327435
2018-03-13 19:20:01 +00:00
Brian M. Rzycki
409c4a1d03 [LazyValueInfo] PR33357 prevent infinite recursion on BinaryOperator
Summary:
It is possible for LVI to encounter instructions that are not in valid
SSA form and reference themselves. One example is the following:
  %tmp4 = and i1 %tmp4, undef
Before this patch LVI would recurse until running out of stack memory
and crashed.  This patch marks these self-referential instructions as
Overdefined and aborts analysis on the instruction.

Fixes https://bugs.llvm.org/show_bug.cgi?id=33357

Reviewers: craig.topper, anna, efriedma, dberlin, sebpop, kuhar

Reviewed by: dberlin

Subscribers: uabelho, spatel, a.elovikov, fhahn, eli.friedman, mzolotukhin, spop, evandro, davide, llvm-commits

Differential Revision: https://reviews.llvm.org/D34135

llvm-svn: 327432
2018-03-13 18:14:10 +00:00
Eugene Zemtsov
b0c558c896 Handle mixed-OS paths in DWARF reader
Make sure that DWARF line information generated by Windows can be properly read by Posix OS and vice versa.

Differential Revision: https://reviews.llvm.org/D44290

llvm-svn: 327430
2018-03-13 17:54:29 +00:00
Zachary Turner
1882229246 [PDB] Support dumping injected sources via the DIA reader.
Injected sources are basically a way to add actual source file content
to your PDB. Presumably you could use this for shipping your source code
with your debug information, but in practice I can only find this being
used for embedding natvis files inside of PDBs.

In order to effectively test LLVM's natvis file injection, we need a way
to dump the injected sources of a PDB in a way that is authoritative
(i.e. based on Microsoft's understanding of the PDB format, and not
LLVM's). To this end, I've added support for dumping injected sources
via DIA. I made a PDB file that used the /natvis option to generate a
test case.

Differential Revision: https://reviews.llvm.org/D44405

llvm-svn: 327428
2018-03-13 17:46:06 +00:00
Simon Dardis
30167650e0 Revert "[mips] Guard traps for microMIPS correctly"
This appears to have broken the expensive checks bot in
a strange fashion. Reverting until I can investigate.

This reverts r327409.

llvm-svn: 327427
2018-03-13 17:31:11 +00:00
Simon Pilgrim
aca99d05c2 [DAGCombine] visitREM - Don't assume that one divrem isn't driving another
Under some circumstances the divrems won't have been combined together before getting to this code.

So replace the assertion with a if() guard to not expand to X-((X/C)*C) to give the other combine chance to happen.

Reduced from OSS-Fuzz #6883
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=6883

llvm-svn: 327424
2018-03-13 17:17:15 +00:00
Brock Wyma
23d099ea06 Revert r327397 [CodeView] Omit forward references for unnamed structs and ...
This reverts commit r327397 to investigate a buildbot failure.

llvm-svn: 327414
2018-03-13 15:56:20 +00:00
Jonas Devlieghere
7aa3e9822f [dsymutil] Unify error handling outside DwarfLinker.
This is a follow-up to r327137 where we unified error handling for the
DwarfLinker. This replaces calls to errs() and outs() with the
appropriate ostream wrapper everywhere in dsymutil.

llvm-svn: 327411
2018-03-13 15:47:38 +00:00
Simon Dardis
1980e1749b [mips] Guard traps for microMIPS correctly
This is part of fixing the instruction predicates for MIPS.

Reviewers: atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D44212

llvm-svn: 327409
2018-03-13 15:46:58 +00:00
Rafael Espindola
0107e8f243 [ThinLTO] Clear dllimport when setting dso_local.
This is PR36686.

If a user of a library is LTOed with that library we take the
opportunity to set dso_local, but we don't clear dllimport, which
creates an invalid IR.

llvm-svn: 327408
2018-03-13 15:24:51 +00:00
Simon Pilgrim
8dd53cb24b [X86][Btver2] Split i8/i16/i32/i64 div/idiv costs
We were assuming a mixture of 32/64 division costs.

llvm-svn: 327407
2018-03-13 15:22:24 +00:00
Sanjay Patel
7dd9e8e307 [InstCombine] fix fmul reassociation to avoid creating an extra fdiv
This was supposed to be an NFC refactoring that will eventually allow
eliminating the isFast() predicate, but there's a rare possibility
that we would pessimize the code as shown in the test case because
we failed to check 'hasOneUse()' properly. This version also removes
an inefficiency of the old code; we would look for: 
(X * C) * C1 --> X * (C * C1)
...but that pattern is always handled by 
SimplifyAssociativeOrCommutative().

llvm-svn: 327404
2018-03-13 14:46:32 +00:00
Simon Dardis
329bd7a71d [mips] Fix the definitions of the EVA instructions
Correct their availability to their respective ISAs.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D44209

llvm-svn: 327403
2018-03-13 14:39:44 +00:00
Jonas Devlieghere
42817263df [dsymutil] Perform analyzeContextInfo and CloneDIEs in parallel
This patch makes dsymutil perform analyzeContextInfo and CloneDIEs in
parallel. For the same object file, there is a dependency between the
two. However, we can do analyzeContextInfo for the next object file
while cloning DIEs for the current. This is exactly the approach taken
in this patch.

For WebCore, this leads to a performance improvement of 29% and for
clang we see similar results with at 32% improvement.

A big thanks to Pete Cooper who came up with the original idea and
the PoC.

Differential revision: https://reviews.llvm.org/D43945

llvm-svn: 327399
2018-03-13 14:27:15 +00:00
Daniel Neilson
e6d5325391 [SROA] Take advantage of separate alignments for memcpy source and destination
Summary:
This change is part of step five in the series of changes to remove alignment argument from
memcpy/memmove/memset in favour of alignment attributes. In particular, this changes the
SROA pass to cease using the old getAlignment() & setAlignment() APIs of MemoryIntrinsic in
favour of getting source & dest specific alignments through the new API. This allows us
to enhance visitMemTransferInst to be more aggressive setting the alignment in memcpy
calls that it creates, as well as to only change the alignment of a memcpy/memmove
argument that it replaces.

Steps:
Step 1) Remove alignment parameter and create alignment parameter attributes for
memcpy/memmove/memset. ( rL322965, rC322964, rL322963 )
Step 2) Expand the IRBuilder API to allow creation of memcpy/memmove with differing
source and dest alignments. ( rL323597 )
Step 3) Update Clang to use the new IRBuilder API. ( rC323617 )
Step 4) Update Polly to use the new IRBuilder API. ( rL323618 )
Step 5) Update LLVM passes that create memcpy/memmove calls to use the new IRBuilder API,
and those that use use MemIntrinsicInst::[get|set]Alignment() to use [get|set]DestAlignment()
and [get|set]SourceAlignment() instead. ( rL323886, rL323891, rL324148, rL324273, rL324278,
rL324384, rL324395, rL324402, rL324626, rL324642, rL324653, rL324654, rL324773, rL324774,
rL324781, rL324784, rL324955, rL324960, rL325816 )
Step 6) Remove the single-alignment IRBuilder API for memcpy/memmove, and the
MemIntrinsicInst::[get|set]Alignment() methods.

Reference
   http://lists.llvm.org/pipermail/llvm-dev/2015-August/089384.html
   http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20151109/312083.html

Reviewers: chandlerc, bollu, efriedma

Reviewed By: efriedma

Subscribers: efriedma, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D42974

llvm-svn: 327398
2018-03-13 14:25:33 +00:00
Brock Wyma
1b9cd38265 [CodeView] Omit forward references for unnamed structs and unions
Codeview references to unnamed structs and unions are expected to refer to the
complete type definition instead of a forward reference so Visual Studio can
resolve the type properly.

Differential Revision: https://reviews.llvm.org/D32498

llvm-svn: 327397
2018-03-13 14:14:16 +00:00