1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 03:23:01 +02:00
Commit Graph

175920 Commits

Author SHA1 Message Date
George Rimar
4f51fe0c01 [llvm-objcopy] - Remove dead code. NFCI.
DecompressedSection can only be created if --decompress-debug-sections is specified.
https://github.com/llvm-mirror/llvm/blob/master/tools/llvm-objcopy/ELF/ELFObjcopy.cpp#L492

If it is specified when !zlib::isAvailable(), we error out early when parsing the options:
https://github.com/llvm-mirror/llvm/blob/master/tools/llvm-objcopy/CopyConfig.cpp#L657

What means the code I am removing in this patch is dead.

Differential revision: https://reviews.llvm.org/D59017

llvm-svn: 355505
2019-03-06 14:12:18 +00:00
Pavel Labath
7400d52f48 Expose template parameters of endian specific types as class members
Summary:
This allows generic code to query these parameters, and is a common
practice in a lot of other template classes.

Reviewers: zturner, Bigcheese

Subscribers: kristina, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58969

llvm-svn: 355504
2019-03-06 14:09:02 +00:00
George Rimar
edd70802af [llvm-objcopy] - Remove an excessive zlib::isAvailable() check and dead code.
There are 2 places where llvm-objcopy creates CompressedSection:

For --compress-debug-sections. It might create the compressed section from
regular here:
https://github.com/llvm-mirror/llvm/blob/master/tools/llvm-objcopy/ELF/ELFObjcopy.cpp#L486

All initially compressed sections are created as CompressedSection during reading the sections
from an object:
https://github.com/llvm-mirror/llvm/blob/master/tools/llvm-objcopy/ELF/Object.cpp#L1118
Those have DebugCompressionType::None type and a different constructor.

Case 1 has the following code in its constructor:

if (!zlib::isAvailable()) {
  CompressionType = DebugCompressionType::None;
  return;
}
(https://github.com/llvm-mirror/llvm/blob/master/tools/llvm-objcopy/ELF/Object.cpp#L267)

We can never reach that code with because would report an error much earlier:
https://github.com/llvm-mirror/llvm/blob/master/tools/llvm-objcopy/CopyConfig.cpp#L480

So the code I am removing is dead. Landing this will address the issue mentioned in https://bugs.llvm.org/show_bug.cgi?id=40886.

Differential revision: https://reviews.llvm.org/D59019

llvm-svn: 355503
2019-03-06 14:08:27 +00:00
George Rimar
09f6aceae8 [llvm-objcopy] - Fix incorrect CompressedSection creation.
We should create CompressedSection only if the section has SHF_COMPRESSED flag
or it's name starts from '.zdebug'.
Currently, we create it if section's data starts from ZLIB signature.

Differential revision: https://reviews.llvm.org/D59018

llvm-svn: 355501
2019-03-06 14:01:54 +00:00
Simon Pilgrim
7cbf4148ed [llvm-mca][X86] Add ADC/SBB with zero test cases
Some targets have fast-path handling for these patterns that we should model.

llvm-svn: 355498
2019-03-06 12:51:16 +00:00
Roman Lebedev
573e621b3e [X86][NFC] Autogenerate check lines in cmovcmov.ll test
Investigating 8-bit cmov promotion, this test comes up.

llvm-svn: 355496
2019-03-06 11:47:43 +00:00
Simon Pilgrim
34433811ef [DAGCombiner] Enable SMULO/UMULO vector combine support (PR40442)
Differential Revision: https://reviews.llvm.org/D58968

llvm-svn: 355495
2019-03-06 11:04:21 +00:00
Simon Pilgrim
572f6fb49a [X86][SSE] VSELECT(XOR(Cond,-1), LHS, RHS) --> VSELECT(Cond, RHS, LHS)
As noticed on D58965

DAGCombiner::visitSELECT has something similar, so we should be able to move this to DAGCombiner and support VSELECT as well at some point.

Differential Revision: https://reviews.llvm.org/D58974

llvm-svn: 355494
2019-03-06 10:54:43 +00:00
Ayonam Ray
362af4b89b [CodeGen] Omit range checks from jump tables when lowering switches with unreachable default
During the lowering of a switch that would result in the generation of a
jump table, a range check is performed before indexing into the jump
table, for the switch value being outside the jump table range and a
conditional branch is inserted to jump to the default block. In case the
default block is unreachable, this conditional jump can be omitted. This
patch implements omitting this conditional branch for unreachable
defaults.

Differential Revision: https://reviews.llvm.org/D52002
Reviewers: Hans Wennborg, Eli Freidman, Roman Lebedev

llvm-svn: 355490
2019-03-06 10:01:02 +00:00
Ayonam Ray
cf951155ce Reversing the commit of revision 355483 since it is giving a regression on a newly added test.
llvm-svn: 355487
2019-03-06 07:51:28 +00:00
Craig Topper
f4b02bd14b [X86] Enable the add with 128 -> sub with -128 encoding trick with X86ISD::ADD when the carry flag isn't used.
This allows us to use an 8-bit sign extended immediate instead of a 16 or 32 bit immediate.

Also do similar for 0x80000000 with 64-bit adds to avoid having to use a movabsq.

llvm-svn: 355485
2019-03-06 07:36:38 +00:00
Craig Topper
6f5194b3c8 [X86] Suppress load folding for add/sub with 128 immediate.
128 won't fit in a sign extended 8-bit immediate, but we can negate it to -128 and use the other operation. This results in a shorter encoding since the move would have used 16 or 32 bits for the immediate.

llvm-svn: 355484
2019-03-06 07:36:36 +00:00
Ayonam Ray
8915d92df3 [CodeGen] Omit range checks from jump tables when lowering switches with unreachable default
During the lowering of a switch that would result in the generation of a
jump table, a range check is performed before indexing into the jump
table, for the switch value being outside the jump table range and a
conditional branch is inserted to jump to the default block. In case the
default block is unreachable, this conditional jump can be omitted. This
patch implements omitting this conditional branch for unreachable
defaults.

Differential Revision: https://reviews.llvm.org/D52002
Reviewers: Hans Wennborg, Eli Freidman, Roman Lebedev

llvm-svn: 355483
2019-03-06 07:27:45 +00:00
Peter Collingbourne
6fdb0f3c3f gn build: Merge r355439.
llvm-svn: 355480
2019-03-06 03:08:06 +00:00
QingShan Zhang
5a976df7f5 [NFC] Declare the member data of class PostGenericScheduler as "protected" instead of "private"
Some target might try to subclass the PostGenericScheduler to custom the scheduling strategy.
We need to declare the member data of PostGenericScheduler as "protected", which acts the same as "GenericScheduler".

Differential Revision: https://reviews.llvm.org/D58949

llvm-svn: 355475
2019-03-06 02:39:18 +00:00
Craig Topper
0a5690a5c2 [X86] Remove periods from the end of SubtargetFeature descriptions since the help printer adds a period.
Most features don't have periods already, but some did. When there is a period it causes llc -mattr=+help to print 2 periods.

llvm-svn: 355474
2019-03-06 02:36:48 +00:00
Heejin Ahn
a9bb9b2a49 [WebAssembly] Remove trailing whitespaces in tests (NFC)
Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58955

llvm-svn: 355472
2019-03-06 02:00:22 +00:00
Xing GUO
91f02ebcd5 [BinaryFormat] Add DT_USED tag into dynamic section.
Summary:
This tag is documented in https://docs.oracle.com/cd/E19253-01/817-1984/chapter6-42444/index.html 
Though I could not find some docs that describe it in detail, I found some code snippets.

1.
```
	/*
	 * Look up the string in the string table and get its offset. If
	 * this succeeds, then it is possible that there is a DT_NEEDED
	 * dynamic entry that references it.
	 */
	have_string = elfedit_sec_findstr(argstate->str.sec,
	    strpad_elt.dn_dyn.d_un.d_val, arg, &str_offset) != 0;
	if (have_string) {
		dyn = argstate->dynamic.data;
		for (ndx = 0; ndx < numdyn; dyn++, ndx++) {
			if (((dyn->d_tag == DT_NEEDED) ||
			    (dyn->d_tag == DT_USED)) &&
			    (dyn->d_un.d_val == str_offset))
				goto done;
		}
	}
```
80192cd83b/usr/src/cmd/sgs/elfedit/modules/common/syminfo.c (L512)

2.
```
    case DT_USED:
    case DT_INIT_ARRAY:
    case DT_FINI_ARRAY:
      if (do_dynamic)
        {
          if (entry->d_tag == DT_USED
          && VALID_DYNAMIC_NAME (entry->d_un.d_val))
        {
          char *name = GET_DYNAMIC_NAME (entry->d_un.d_val);

          if (*name)
            {
              printf (_("Not needed object: [%s]\n"), name);
              break;
            }
        }

          print_vma (entry->d_un.d_val, PREFIX_HEX);
          putchar ('\n');
        }
      break;
```
http://web.mit.edu/freebsd/head/contrib/binutils/binutils/readelf.c

3.
```
#define DT_USED     0x7ffffffe  /* ignored - same as needed */
```
https://github.com/switchbrew/switch-tools/blob/master/src/elf_common.h

Reviewers: jhenderson, grimar

Reviewed By: jhenderson, grimar

Subscribers: emaste, krytarowski, fedor.sergeev, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58762

llvm-svn: 355468
2019-03-06 01:28:40 +00:00
Peter Collingbourne
19196e678d gn build: Add 32-bit Linux support.
Differential Revision: https://reviews.llvm.org/D58839

llvm-svn: 355467
2019-03-06 01:28:32 +00:00
Mitch Phillips
f72f04eb27 Revert "[AtomicExpand] Allow libcall expansion for non-zero address spaces" for buildbot failures.
llvm-svn: 355461
2019-03-06 00:25:40 +00:00
Florian Hahn
5351cc7086 [ARM] Sink zext/sext operands for add and sub to enable vsubl generation.
This uses the infrastructure added in rL353152 to sink zext and sexts to
sub/add users, to enable vsubl/vaddl generation when NEON is available.

See https://bugs.llvm.org/show_bug.cgi?id=40025.

Reviewers: SjoerdMeijer, t.p.northover, samparker, efriedma

Reviewed By: samparker

Differential Revision: https://reviews.llvm.org/D58063

llvm-svn: 355460
2019-03-06 00:10:03 +00:00
Jonas Devlieghere
a554982ed6 [DWARFFormValue] Don't consider DW_FORM_data4/8 to be section offsets.
When dumping ToT clan's debug info with dwarfdump, we were seeing an
error saying that that the location list overflows the debug_loc
section. After reducing the testcase we figured out that we were
interpreting the DW_FORM_data4 as a section offset.

In DWARF3 DW_FORM_data4 and DW_FORM_data8 served also as a section
offset. Until now we didn't check check for the DWARF version, because
some producers (read old versions of clang) were still emitting this.
The relevant code/comment was added in 2013, and I believe it's now
reasonable to start checking the version.

The FormValue class is a little bit of a mess because it cashes the
DWARF unit and context when it extracted the value itself. Several
methods of the class rely on it being present, or return an Optional for
the code path that needs it. At the same time the FormValue class also
used in places where there's no DWARF unit.

For this patch I went with the least invasive change: checking the
version from the CU when it's available. If it's not (because the form
value was created from a value directly) we default to the old behavior.

Differential revision: https://reviews.llvm.org/D58698

llvm-svn: 355456
2019-03-05 23:47:22 +00:00
Florian Hahn
eafd27fedf [opt] Report if the provided architecture is invalid.
Partly addresses PR15026.

There are a few tests that passed in invalid architectures, which are fixed in: rL355349 and D58931

Reviewers: echristo, efriedma, rengolin, atrick

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D58933

llvm-svn: 355455
2019-03-05 23:10:28 +00:00
Philip Reames
6b439704dd [AtomicExpand] Allow libcall expansion for non-zero address spaces
Be consistent about how we treat atomics in non-zero address spaces.  If we get to the backend, we tend to lower them as if in address space 0.  Do the same if we need to insert a libcall instead.

Differential Revision: https://reviews.llvm.org/D58760

llvm-svn: 355453
2019-03-05 23:00:14 +00:00
Roman Lebedev
e3429e27ff [X86][NFC] Add proper test for promotion of i8 cmov's of trunc's
There was no proper test for that code in X86TargetLowering::LowerSELECT().
Noticed accidentally while trying to modify the last branch in that function.

llvm-svn: 355452
2019-03-05 22:43:53 +00:00
Heejin Ahn
ac320d3a64 [WebAssembly] Simplify iterator navigations (NFC)
Summary:
- Replaces some uses of `MachineFunction::iterator(MBB)` with
  `MBB->getIterator()` and `MachineBasicBlock::iterator(MI)` with
  `MI->getIterator()`, which are simpler.
- Replaces some uses of `std::prev` of `std::next` that takes a
  MachineFunction or MachineBasicBlock iterator with `getPrevNode` and
  `getNextNode`, which are also simpler.

Reviewers: sbc100

Subscribers: dschuff, sunfish, jgravelle-google, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58913

llvm-svn: 355444
2019-03-05 21:05:09 +00:00
Francis Visoiu Mistrih
116895ffdc [Remarks][NFC] Rename RemarkParser to YAMLRemarkParser
Rename it to reflect that it's parsing YAML remarks.

llvm-svn: 355441
2019-03-05 20:50:35 +00:00
Francis Visoiu Mistrih
7f77ac0406 [OptRemarks] Make OptRemarks more generic: rename OptRemarks to Remarks
Getting rid of the name "optimization remarks" for anything that
involves handling remarks on the client side.

It's safer to do this now, before we get stuck with that name in all the
APIs and public interfaces we decide to export to users in the future.

This renames llvm/tools/opt-remarks to llvm/tools/remarks-shlib, and now
generates `libRemarks.dylib` instead of `libOptRemarks.dylib`.

Differential Revision: https://reviews.llvm.org/D58535

llvm-svn: 355439
2019-03-05 20:45:17 +00:00
Heejin Ahn
b49f808db4 [WebAssembly] Disable MachineBlockPlacement pass
Summary:
This pass hurts code size for wasm and sometimes generates irreducible
control flow.
Context: https://github.com/emscripten-core/emscripten/pull/8233

Reviewers: kripken, dschuff

Subscribers: sunfish, sbc100, jgravelle-google, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58953

llvm-svn: 355437
2019-03-05 20:35:34 +00:00
Roman Lebedev
5945ae1c07 [NFC][CodeGen][X86][AArch64] Add tests for C++ std::midpoint() pattern (PR40965)
Tests only for integers, not floating point or pointers.

The scalar 8-bit case uses branch instead of CMOV,
because there is no no 8-bit CMOV.

Vector tests are for consistency, since it can be vectorized.

https://bugs.llvm.org/show_bug.cgi?id=40965

llvm-svn: 355436
2019-03-05 20:18:47 +00:00
Craig Topper
dde774575a Revert r355224 "[TableGen][SelectionDAG][X86] Add specific isel matchers for immAllZerosV/immAllOnesV. Remove bitcasts from X86 patterns that are no longer necessary."
This caused the first matcher in the isel table for many targets to Opc_Scope instead of Opc_SwitchOpcode. This leads to a significant increase in isel match failures.

llvm-svn: 355433
2019-03-05 19:18:16 +00:00
Craig Topper
69c69a340b [Subtarget] Merge ProcSched and ProcDesc arrays in MCSubtargetInfo into a single array.
These arrays are both keyed by CPU name and go into the same tablegenerated file. Merge them so we only need to store keys once.

This also removes a weird space saving quirk where we used the ProcDesc.size() to create to build an ArrayRef for ProcSched.

Differential Revision: https://reviews.llvm.org/D58939

llvm-svn: 355431
2019-03-05 18:54:38 +00:00
Guozhi Wei
8e8635f46f [X86] In X86DomainReassignment.cpp add enclosed registers to EnclosedEdges
The variable X86DomainReassignment::EnclosedEdges is used to store registers that have been enclosed in some closure, so those registers will be ignored when create new closures. But there is no registers has ever been put into this set, so a single register can be enclosed in multiple closures, it significantly increase compile time.

This patch adds a register into EnclosedEdges when it is enclosed into a closure.

Differential Revision: https://reviews.llvm.org/D58646

llvm-svn: 355430
2019-03-05 18:54:34 +00:00
Craig Topper
9cde3703c2 [Subtarget] Create a separate SubtargetSubtargetKV struct for ProcDesc to remove fields from the stack tables that aren't needed for CPUs
The description for CPUs was just the CPU name wrapped with "Select the " and " processor". We can just do that directly in the help printer instead of making a separate version in the binary for each CPU.

Also remove the Value field that isn't needed and was always 0.

Differential Revision: https://reviews.llvm.org/D58938

llvm-svn: 355429
2019-03-05 18:54:34 +00:00
Craig Topper
14fa6aa690 [Subtarget] Move SubtargetFeatureKV/SubtargetInfoKV from SubtargetFeature.h to MCSubtargetInfo.h. Move all code that operates on ProcFeatures and ProcDesc arrays to MCSubtargetInfo.
The SubtargetFeature class managed a list of features as strings. And it also had functions for setting bits in a FeatureBitset.

The methods that operated on the Feature list as strings are used in other parts of the backend. But the parts that operate on FeatureBitset are very tightly coupled to MCSubtargetInfo and requires passing in the arrays that MCSubtargetInfo owns. And the same struct type is used for ProcFeatures and ProcDesc.

This has led to MCSubtargetInfo having 2 arrays keyed by CPU name. One containing a mapping from a CPU name to its features. And one containing a mapping from CPU name to its scheduler model.

I would like to make a single CPU array containing all CPU information and remove some unneeded fields the ProcDesc array currently has. But I don't want to make SubtargetFeatures.h have to know about the scheduler model type and have to forward declare or pull in the header file.

Differential Revision: https://reviews.llvm.org/D58937

llvm-svn: 355428
2019-03-05 18:54:30 +00:00
Matt Arsenault
efd2ba88fc AMDGPU: Preserve undef flag when expanding SI_IF
Fixes undefined value verifier error.

llvm-svn: 355426
2019-03-05 18:38:00 +00:00
Craig Topper
13f2de03d3 [X86] Enable 8-bit SHL to convert to LEA
Differential Revision: https://reviews.llvm.org/D58870

llvm-svn: 355425
2019-03-05 18:37:41 +00:00
Craig Topper
29ce866ad1 [X86] Allow 8-bit INC/DEC to be converted to LEA.
We already do this for 16/32/64 as well as 8-bit add with register/immediate. Might as well do it for 8-bit INC/DEC too.

Differential Revision: https://reviews.llvm.org/D58869

llvm-svn: 355424
2019-03-05 18:37:37 +00:00
Craig Topper
2bcecae492 [X86] Enable 8-bit OR with disjoint bits to convert to LEA
We already support 8-bits adds in convertToThreeAddress. But we can also support 8-bit OR if the bits are disjoint. We already do this for 16/32/64.

Differential Revision: https://reviews.llvm.org/D58863

llvm-svn: 355423
2019-03-05 18:37:33 +00:00
Florian Hahn
b06b894c1f [SLP] Fix invalid triple in X86 tests
x86-64 is an invalid architecture in triples. Changing it to the correct
triple (x86_64) changes some tests, because SLP is not deemed profitable
any more.

Reviewers: ABataev, RKSimon, spatel

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D58931

llvm-svn: 355420
2019-03-05 17:56:35 +00:00
Javed Absar
d19970f650 TableGen: Allow lists to be concatenated through '#'
Currently one can concatenate strings using hash(#),
but not lists, although that would be a natural thing to do. 

This patch allows one to write something like:
def : A<!listconcat([1,2], [3,4])>;
simply as :
def : A<[1,2] # [3,4]>;

This was missing feature was highlighted by Nicolai
at FOSDEM talk.

Reviewed by: nhaehnle, hfinkel

Differential Revision: https://reviews.llvm.org/D58895

llvm-svn: 355414
2019-03-05 17:16:07 +00:00
Simon Pilgrim
dcde6a778e [X86][SSE] Regenerate vector zero tests
llvm-svn: 355412
2019-03-05 16:52:14 +00:00
Sanjay Patel
afd4ff2eee [SDAG] move FP constant folding to helper function; NFC
llvm-svn: 355411
2019-03-05 16:42:33 +00:00
Jessica Paquette
1b3a1b13fd Revert "[GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELT"
This broke test-suite::aarch64_neon_intrinsics.test

Reverting while I look into it.

Example failure:
http://lab.llvm.org:8011/builders/clang-cmake-aarch64-quick/builds/17740

llvm-svn: 355408
2019-03-05 15:47:00 +00:00
Simon Pilgrim
c09a0f009a [X86] Add SMULO/UMULO combine tests
Include scalar and vector test variants covering the folds in DAGCombiner (vector isn't currently supported - PR40442)

llvm-svn: 355407
2019-03-05 15:36:45 +00:00
Simon Pilgrim
c38f14aa87 Fix typo in constant vector
llvm-svn: 355405
2019-03-05 15:06:01 +00:00
Simon Pilgrim
6e9b6a15d2 [X86] Add SADDO/UADDO and SSUBO/USUBO combine tests
Include scalar and vector test variants covering the folds in DAGCombiner (vector isn't currently supported - PR40442)

llvm-svn: 355404
2019-03-05 14:52:42 +00:00
Simon Pilgrim
2542538e6e [X86] Add test cases for D58874
Add scalar and vector test cases for missing (add (add (xor a, -1), b), 1) -> (sub b, a) fold

llvm-svn: 355400
2019-03-05 13:52:09 +00:00
George Rimar
e24ba5947b [llvm-objcopy] - Simplify isCompressable and fix the issue relative.
When --compress-debug-sections is given, llvm-objcopy do not compress
sections that have "ZLIB" header in data. Normally this signature is used
in zlib-gnu compression format. But if zlib-gnu used then the name of the compressed
section should start from .z* (e.g .zdebug_info). If it does not, then it is not
a zlib-gnu format and section should be treated as a normal uncompressed section.

Differential revision: https://reviews.llvm.org/D58908

llvm-svn: 355399
2019-03-05 13:07:43 +00:00
Carl Ritson
c6a3af137e [AMDGPU] Fix DPP operand order in atomic optimizer
Summary:
Ensure order of operands in DPP atomic optimizer final WWM step is appropriate for sub instructions.

Change-Id: I631d050e1c00a3b4bc7c11a90437064403c4cf30

Reviewers: sheredom, tpr

Reviewed By: sheredom

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, t-tye, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58900

llvm-svn: 355394
2019-03-05 12:21:44 +00:00