Owen Anderson
b6e1c56c79
Correct Thumb2 encodings for a much wider range of loads and stores.
...
llvm-svn: 120364
2010-11-30 00:14:31 +00:00
Jim Grosbach
5f2a3880a8
Make a few more ARM pseudo instructions actually use the PseudoInst base class.
...
llvm-svn: 120362
2010-11-30 00:09:06 +00:00
Bill Wendling
9859e95ca2
Predicate encoding should be withing {}s. And general cleanup.
...
llvm-svn: 120361
2010-11-30 00:08:20 +00:00
Bill Wendling
6b680b11e8
Predicate encoding should be withing {}s.
...
llvm-svn: 120360
2010-11-30 00:05:25 +00:00
Bob Wilson
f5eece615c
Fix the encoding of VLD4-dup alignment.
...
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function. Use it
for all the VLD-dup instructions for the sake of consistency.
llvm-svn: 120358
2010-11-30 00:00:42 +00:00
Bob Wilson
1be989686c
Rename VLDnDUP instructions with double-spaced registers
...
in an attempt to make things a little more consistent.
llvm-svn: 120357
2010-11-30 00:00:38 +00:00
Bob Wilson
bd3d3d2937
Add support for NEON VLD3-dup instructions.
...
The encoding for alignment in VLD4-dup instructions is still a work in progress.
llvm-svn: 120356
2010-11-30 00:00:35 +00:00
Jim Grosbach
58e4c01d0d
Simplify definitions of the ARM eh.sjlj.*jmp pseudo instructions.
...
llvm-svn: 120354
2010-11-29 23:51:31 +00:00
Jim Grosbach
b796df67e9
Parameterize ARMPseudoInst size property.
...
llvm-svn: 120353
2010-11-29 23:48:41 +00:00
Jim Grosbach
81880e96fc
Add a few missing initializers.
...
llvm-svn: 120350
2010-11-29 23:41:10 +00:00
Jim Grosbach
4e37703b2c
Nuke trailing whitespace.
...
llvm-svn: 120344
2010-11-29 23:18:01 +00:00
Jim Grosbach
d92d1fa9e6
Nuke a FIXME. No need to be fancier here, as ARM handles constant pools
...
locations and formatting specially. rdar://7353441
llvm-svn: 120343
2010-11-29 23:09:20 +00:00
Owen Anderson
14abbb1a2e
Provide Thumb2 encodings for basic loads and stores.
...
llvm-svn: 120340
2010-11-29 22:44:32 +00:00
Evan Cheng
78baa6f30d
Mark Darwin call instructions as using "r7" to prevent the frame-register
...
assignment instructions from being moved below / above calls.
rdar://8690640
llvm-svn: 120339
2010-11-29 22:43:27 +00:00
Jim Grosbach
90cb1bbd23
Nuke dead isCodeGenOnly annotation and extraneous comment.
...
llvm-svn: 120338
2010-11-29 22:40:58 +00:00
Jim Grosbach
208782384a
tidy up.
...
llvm-svn: 120335
2010-11-29 22:38:48 +00:00
Bill Wendling
c2693dcc02
Thumb encodings for conditional moves.
...
llvm-svn: 120334
2010-11-29 22:37:46 +00:00
Jim Grosbach
89e90b7310
Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
...
instructions. This simplifies instruction printing and disassembly.
llvm-svn: 120333
2010-11-29 22:37:40 +00:00
Bill Wendling
15e68b7a35
Refactor some of the "disassembly-only" instructions into a base class. This
...
reduces some code duplication.
llvm-svn: 120326
2010-11-29 22:15:03 +00:00
Eric Christopher
625238ff3e
Update fastisel for the changes in r120272.
...
llvm-svn: 120324
2010-11-29 21:56:23 +00:00
Jim Grosbach
71042b51a1
Rename t2 TBB and TBH instructions to reference that they encode the jump table
...
data. Next up, pseudo-izing them.
llvm-svn: 120320
2010-11-29 21:28:32 +00:00
Owen Anderson
4b82810d8c
Improving the factoring of several instruction encodings.
...
llvm-svn: 120317
2010-11-29 20:38:48 +00:00
Bob Wilson
aa197b07e6
Add support for NEON VLD3-dup instructions.
...
llvm-svn: 120312
2010-11-29 19:35:29 +00:00
Bob Wilson
cb675664c4
Fix copy-and-paste errors in VLD2-dup scheduling itineraries.
...
llvm-svn: 120311
2010-11-29 19:35:23 +00:00
Jim Grosbach
3e84f9d6cb
ARM Pseudo-ize tBR_JTr.
...
llvm-svn: 120310
2010-11-29 19:32:47 +00:00
Owen Anderson
049177ff7f
Thumb2 encodings for MSR and MRS.
...
llvm-svn: 120309
2010-11-29 19:29:15 +00:00
Owen Anderson
78d84a1921
Thumb2 encodings for system instructions.
...
llvm-svn: 120307
2010-11-29 19:22:08 +00:00
Owen Anderson
b29182b60f
Thumb2 encodings for branches and IT blocks.
...
llvm-svn: 120306
2010-11-29 18:54:38 +00:00
Jim Grosbach
0d235c0c37
The ARM BR_JT* pseudos don't need to use the printer jtblock_operand node to
...
get the pretty-printer. That's handled explicityly by the MC lowering now.
llvm-svn: 120305
2010-11-29 18:53:24 +00:00
Michael J. Spencer
4a63404543
I swear I did a make clean and make before committing all this...
...
llvm-svn: 120304
2010-11-29 18:47:54 +00:00
Jim Grosbach
9e2ed21ad0
Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.
...
llvm-svn: 120303
2010-11-29 18:37:44 +00:00
Michael J. Spencer
d5ec932c3a
Merge System into Support.
...
llvm-svn: 120298
2010-11-29 18:16:10 +00:00
Kalle Raiskila
71dec6ff42
Handle lshr for i128 correctly on SPU also when
...
shiftamount > 7.
llvm-svn: 120288
2010-11-29 14:44:28 +00:00
Kalle Raiskila
45865e9165
Enable PostRA scheduling for SPU.
...
This speeds up selected test cases with up to
5% - no slowdowns observed.
llvm-svn: 120286
2010-11-29 10:30:25 +00:00
Kalle Raiskila
64f85ff7b3
Allow machine LICM to do its job on SPU.
...
-return a sensible value for register pressure
-add pattern to 'ila' instrucion
llvm-svn: 120285
2010-11-29 10:08:09 +00:00
Kalle Raiskila
46d01503cd
Add missing i128 case.
...
llvm-svn: 120284
2010-11-29 09:36:26 +00:00
Bill Wendling
c0055893db
Add more Thumb encodings.
...
llvm-svn: 120279
2010-11-29 01:07:48 +00:00
Bill Wendling
b54752da15
More Thumb encodings.
...
llvm-svn: 120278
2010-11-29 01:00:43 +00:00
Bill Wendling
8f0b624061
Add Thumb encodings for REV instructions.
...
llvm-svn: 120277
2010-11-29 00:42:50 +00:00
Bill Wendling
d233cab1eb
Add more Thumb encodings.
...
llvm-svn: 120272
2010-11-29 00:18:15 +00:00
Rafael Espindola
d5f118a011
Make EmitIntValue non virtual.
...
llvm-svn: 120271
2010-11-28 23:22:44 +00:00
Rafael Espindola
9287c4b38f
Move lowering of TLS_addr32 and TLS_addr64 to X86MCInstLower.
...
llvm-svn: 120263
2010-11-28 21:16:39 +00:00
Chris Lattner
a11c5c5c32
fix PR8686, accepting a 'b' suffix at the end of all the setcc
...
instructions. I choose to handle this with an asmparser hack,
though it could be handled by changing all the instruction definitions
to allow be "setneb" instead of "setne". The asm parser hack is
better in this case, because we want the disassembler to produce
setne, not setneb.
llvm-svn: 120260
2010-11-28 20:23:50 +00:00
Nicolas Geoffray
9705544e7c
When emitting a single function with cppgen=function, you don't want to emit
...
initializers of global variables used in the function.
Also make sure to emit the operands of a constant.
llvm-svn: 120253
2010-11-28 18:00:53 +00:00
Rafael Espindola
38c559954c
Move the PTXMCAsmStreamer class to the .cpp file.
...
llvm-svn: 120241
2010-11-28 14:48:34 +00:00
Rafael Espindola
f77005db2b
Define generic 1, 2 and 4 byte pc relative relocations. They are common
...
and at least the 4 byte one will be needed to implement the .cfi_* directives.
llvm-svn: 120240
2010-11-28 14:17:56 +00:00
Bob Wilson
3bb61d1932
Add support for NEON VLD2-dup instructions.
...
llvm-svn: 120236
2010-11-28 06:51:26 +00:00
Bob Wilson
f4df482b0d
Another minor refactoring for VLD1DUP instructions.
...
The op11_8 field is the same for all of them so put it in the instruction
classes instead of specifying it separately for each instruction.
llvm-svn: 120234
2010-11-28 06:51:15 +00:00
Bob Wilson
edf156f4af
Add entry in getTargetNodeName() for ARMISD::VBICIMM.
...
llvm-svn: 120233
2010-11-28 06:51:11 +00:00
Anton Korobeynikov
598465c605
Move more PEI-related hooks to TFI
...
llvm-svn: 120229
2010-11-27 23:05:25 +00:00
Anton Korobeynikov
c87f68e32e
Move callee-saved regs spills / reloads to TFI
...
llvm-svn: 120228
2010-11-27 23:05:03 +00:00
Rafael Espindola
45cd9713f2
Lower TLS_addr32 and TLS_addr64.
...
llvm-svn: 120225
2010-11-27 20:43:02 +00:00
Rafael Espindola
6f5680f4a0
Implement the data16 prefix.
...
llvm-svn: 120224
2010-11-27 20:29:45 +00:00
Bob Wilson
3e64f6b309
Refactor. Set alignment bit in VLD1-dup instruction classes.
...
llvm-svn: 120197
2010-11-27 07:12:02 +00:00
Bob Wilson
cbd6281807
Add NEON VLD1-dup instructions (load 1 element to all lanes).
...
llvm-svn: 120194
2010-11-27 06:35:16 +00:00
Bob Wilson
c66e4574f1
Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions.
...
I added these instructions recently but I have no idea where these "1"
values in the NextCycles field came from. As far as I can tell now,
these instruction stages are clearly intended to overlap.
llvm-svn: 120193
2010-11-27 06:35:09 +00:00
Daniel Dunbar
bcc15fb05d
MC/Mach-O: Switch to using MachOFormat.h.
...
- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another).
llvm-svn: 120187
2010-11-27 04:38:36 +00:00
Rafael Espindola
0641196380
Remove the unused TheTarget member.
...
llvm-svn: 120168
2010-11-26 04:24:21 +00:00
Rafael Espindola
e3dc1c951c
Use multiple 0x66 prefixes so that all nops up to 15 bytes are a single instruction.
...
llvm-svn: 120147
2010-11-25 17:14:16 +00:00
Benjamin Kramer
35b0f6e5a6
Namespacify.
...
llvm-svn: 120146
2010-11-25 16:42:51 +00:00
Wesley Peck
66641a7c04
Updating MBlaze .mask and .frame directives to match GCC's output and fixing regression introduced in 120095 by checking MCStreamer::hasRawTextSupport.
...
llvm-svn: 120097
2010-11-24 16:32:35 +00:00
Wesley Peck
0e324a205e
1. Fixing error where basic block labels were not being printed out when they need to be for the MBlaze backend because AsmPrinter::isBlockOnlyReachableByFallthrough does not take into account delay slots.
...
2. Re-adding .mask and .frame directives in printed assembly.
3. Adding .ent and .end directives in printed assembly.
4. Minor cleanups to MBlaze backend.
llvm-svn: 120095
2010-11-24 15:39:32 +00:00
Kalle Raiskila
edb28eb356
Use i8 as SETCC result type for i1 in SPU.
...
llvm-svn: 120092
2010-11-24 12:59:16 +00:00
Kalle Raiskila
b017eaea7b
Allow for 'fcmp ogt' in SPU.
...
Fix by Visa Putkinen!
llvm-svn: 120090
2010-11-24 11:42:17 +00:00
Benjamin Kramer
8d7096e8ca
The srem -> urem transform is not safe for any divisor that's not a power of two.
...
E.g. -5 % 5 is 0 with srem and 1 with urem.
Also addresses Frits van Bommel's comments.
llvm-svn: 120049
2010-11-23 20:33:57 +00:00
Jason W Kim
b1725a8110
Move the ARM reloc constants to Support/ELF.h
...
llvm-svn: 120035
2010-11-23 19:40:36 +00:00
Bob Wilson
ff0e6b1252
Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.
...
We need to check if the individual vector elements are sign/zero-extended
values. For now this only handles constants values. Radar 8687140.
llvm-svn: 120034
2010-11-23 19:38:38 +00:00
Benjamin Kramer
c8e6037e7d
InstCombine: Reduce "X shift (A srem B)" to "X shift (A urem B)" iff B is positive.
...
This allows to transform the rem in "1 << ((int)x % 8);" to an and.
llvm-svn: 120028
2010-11-23 18:52:42 +00:00
Kalle Raiskila
f71cc94c91
Division by pow-of-2 is not cheap on SPU, do it with
...
shifts.
llvm-svn: 120022
2010-11-23 13:27:59 +00:00
Rafael Espindola
72c8de703d
Implement the rex64 prefix.
...
llvm-svn: 120017
2010-11-23 11:23:24 +00:00
Rafael Espindola
6f069fc35f
Produce a relocation for pcrel absolute values. Based on a patch by David Meyer.
...
llvm-svn: 120006
2010-11-23 07:20:12 +00:00
Wesley Peck
d589353ad0
Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.
...
llvm-svn: 119990
2010-11-23 03:31:01 +00:00
Rafael Espindola
492580fa9a
Remove duplicated constants. Thanks to Jason for noticing it.
...
llvm-svn: 119985
2010-11-22 21:49:05 +00:00
Benjamin Kramer
b5a2a81094
InstCombine: Implement X - A*-B -> X + A*B.
...
llvm-svn: 119984
2010-11-22 20:31:27 +00:00
Evan Cheng
e6d55cd247
Fix epilogue codegen to avoid leaving the stack pointer in an invalid
...
state. Previously Thumb2 would restore sp from fp like this:
mov sp, r7
sub, sp, #4
If an interrupt is taken after the 'mov' but before the 'sub', callee-saved
registers might be clobbered by the interrupt handler. Instead, try
restoring directly from sp:
add sp, #4
Or, if necessary (with VLA, etc.) use a scratch register to compute sp and
then restore it:
sub.w r4, r7, #8
mov sp, r7
rdar://8465407
llvm-svn: 119977
2010-11-22 18:12:04 +00:00
Kalle Raiskila
8f1131e569
Fix a bug with extractelement on SPU.
...
In the attached testcase, the element was
never extracted (missing rotate).
llvm-svn: 119973
2010-11-22 16:28:26 +00:00
Benjamin Kramer
632a91cba5
Implement the "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" optimization.
...
This currently only catches the most basic case, a two-case switch, but can be
extended later.
llvm-svn: 119964
2010-11-22 09:45:38 +00:00
Duncan Sands
99ff019c87
Fix a compiler warning about Kind being used uninitialized
...
when assertions are disabled.
llvm-svn: 119962
2010-11-22 09:38:00 +00:00
Eric Christopher
662ad8ba93
Pseudos default to 4byte size, let the instruction size field notice
...
that branch tables are special.
llvm-svn: 119954
2010-11-21 23:38:19 +00:00
Wesley Peck
e25f241e37
Implement ELF object file writing support for the MBlaze backend. Its not perfect yet, but it works for many tests.
...
llvm-svn: 119952
2010-11-21 22:06:28 +00:00
Wesley Peck
911abf2bc0
Implement branch analysis in the MBlaze backend.
...
llvm-svn: 119951
2010-11-21 21:53:36 +00:00
Wesley Peck
470c56eef5
Make it a little bit more explicit that the MBlaze backend only supports upto
...
32-bit immediate values.
llvm-svn: 119950
2010-11-21 21:39:46 +00:00
Wesley Peck
d77425e427
Fix an error in the MBlaze delay slot filler where instructions that already
...
fill a delay slot are moved to fill a different delay slot.
llvm-svn: 119949
2010-11-21 21:36:12 +00:00
Chris Lattner
dd03f96698
apparently tailcalls are better on darwin/x86-64 than on linux?
...
llvm-svn: 119947
2010-11-21 18:59:20 +00:00
Bill Wendling
c5ab347eb6
More Thumb encodings.
...
llvm-svn: 119940
2010-11-21 11:49:36 +00:00
Bill Wendling
a472e7be70
Add encoding for ARM "trap" instruction.
...
llvm-svn: 119938
2010-11-21 11:05:29 +00:00
Bill Wendling
a017020098
The "trap" instruction is one of this which doesn't have a condition code. Hack
...
the code to not add a "condition code" if it's trap.
llvm-svn: 119937
2010-11-21 10:56:05 +00:00
Bill Wendling
3cce558ede
- Give "trap" the correct encoding, at least according to Darwin's assembler.
...
- Add comments saying where the encodings for other instructions came from.
llvm-svn: 119936
2010-11-21 10:55:23 +00:00
Chris Lattner
4aaa7fbb98
implement PR8524, apparently mainline gas accepts movq as an alias for movd
...
when transfering between i64 gprs and mmx regs.
llvm-svn: 119931
2010-11-21 08:18:57 +00:00
Chris Lattner
ed3b3d47f6
add some random notes.
...
llvm-svn: 119925
2010-11-21 07:05:31 +00:00
Owen Anderson
0ec4da72fc
Use by-name rather than by-order operand matching for some NEON encodings.
...
llvm-svn: 119923
2010-11-21 06:47:06 +00:00
Chris Lattner
908a01328c
optimize:
...
void a(int x) { if (((1<<x)&8)==0) b(); }
into "x != 3", which occurs over 100 times in 403.gcc but in no
other program in llvm-test.
llvm-svn: 119922
2010-11-21 06:44:42 +00:00
Chris Lattner
09bf382b8f
tail calls on x86 are implemented.
...
llvm-svn: 119920
2010-11-21 06:10:27 +00:00
Jim Grosbach
1476bfec1e
BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate.
...
llvm-svn: 119918
2010-11-21 01:26:01 +00:00
Bill Wendling
834a3bfb92
A few more thumb instruction MC encodings.
...
llvm-svn: 119913
2010-11-20 22:52:33 +00:00
Eric Christopher
38b8cfea6a
Rewrite address handling to use a structure with all the possible address
...
mode variables. Handle frame indexes in load/store and allocas again.
llvm-svn: 119912
2010-11-20 22:38:27 +00:00
Eric Christopher
5a99947b98
STRH only needs the additional operand, not t2STRH. Also invert conditional
...
to match the one from the load emitter above.
llvm-svn: 119911
2010-11-20 22:01:38 +00:00
Anton Korobeynikov
e88ba0f100
Make this compile on case-sensitive file systemsw
...
llvm-svn: 119905
2010-11-20 16:14:57 +00:00
Anton Korobeynikov
ff8c52bd51
Move some more hooks to TargetFrameInfo
...
llvm-svn: 119904
2010-11-20 15:59:32 +00:00
Duncan Sands
028cf0619e
On X86, MEMBARRIER, MFENCE, SFENCE, LFENCE are not target memory intrinsics,
...
so don't claim they are. They are allocated using DAG.getNode, so attempts
to access MemSDNode fields results in reading off the end of the allocated
memory. This fixes crashes with "llc -debug" due to debug code trying to
print MemSDNode fields for these barrier nodes (since the crashes are not
deterministic, use valgrind to see this). Add some nasty checking to try
to catch this kind of thing in the future.
llvm-svn: 119901
2010-11-20 11:25:00 +00:00
Bill Wendling
00481555e0
Add more Thumb add instruction encodings.
...
llvm-svn: 119883
2010-11-20 01:18:47 +00:00
Bill Wendling
4fb2131b0a
Add Thumb encodings for some add instructions.
...
llvm-svn: 119882
2010-11-20 01:00:29 +00:00
Bill Wendling
cd27d03d93
Add more encodings for Thumb instructions.
...
llvm-svn: 119881
2010-11-20 00:53:35 +00:00
Bill Wendling
2271583883
Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the same
...
value that the one in ARMMCCodeEmitter.cpp does.
llvm-svn: 119878
2010-11-20 00:26:37 +00:00
Jim Grosbach
b2b99c9b64
Fix ARM LDR* post-indexed operand encoding.
...
llvm-svn: 119869
2010-11-19 23:14:43 +00:00
Bill Wendling
c568ce5bda
Encodings for the compare instructions.
...
llvm-svn: 119868
2010-11-19 23:14:32 +00:00
Owen Anderson
023f096736
The Vm and Vn register fields must be the same for a register-register vmov.
...
llvm-svn: 119867
2010-11-19 23:12:43 +00:00
Evan Cheng
2b30babdcc
Fix a cut-n-paste-error.
...
llvm-svn: 119866
2010-11-19 23:01:16 +00:00
Jim Grosbach
7445ae1145
Operand names
...
llvm-svn: 119864
2010-11-19 22:43:08 +00:00
Jim Grosbach
4d6c419ea2
trailing whitespace
...
llvm-svn: 119863
2010-11-19 22:42:55 +00:00
Eric Christopher
322b045c95
Don't need to save piecemeal now.
...
llvm-svn: 119862
2010-11-19 22:39:56 +00:00
Eric Christopher
899d8247c8
Update comment.
...
llvm-svn: 119861
2010-11-19 22:37:58 +00:00
Bill Wendling
65402c3a76
Add encodings for some of the thumb ADD instructions. Tests will come once the
...
asm parser can handle them.
llvm-svn: 119860
2010-11-19 22:37:33 +00:00
Eric Christopher
716f891687
Update comment.
...
llvm-svn: 119859
2010-11-19 22:36:41 +00:00
Jim Grosbach
69cad2c8b0
Clarify operand names.
...
llvm-svn: 119858
2010-11-19 22:36:02 +00:00
Eric Christopher
563a0d8b6b
Refactor address mode handling into a single struct (ala x86), this
...
should give allow a wider range of addressing modes.
No functional change.
llvm-svn: 119856
2010-11-19 22:30:02 +00:00
Jim Grosbach
0a0b2ed163
Fix encoding for ARM MLS instruction.
...
llvm-svn: 119855
2010-11-19 22:22:37 +00:00
Jim Grosbach
a7213faf85
Add ARM encoding information for STRD.
...
llvm-svn: 119852
2010-11-19 22:14:31 +00:00
Jim Grosbach
bd80b3fe98
Shuffle things around a bit to keep like things together. Tidy up formatting.
...
llvm-svn: 119851
2010-11-19 22:06:57 +00:00
Bill Wendling
29f262163a
Revert accidental commit.
...
llvm-svn: 119850
2010-11-19 22:06:18 +00:00
Bill Wendling
e2f19dfde3
Change long binary encodings to use hex instead. It's more readable. Also
...
initialize missing bit.
llvm-svn: 119849
2010-11-19 22:02:18 +00:00
Jim Grosbach
33930ff560
Factor out operand encoding bits for ARM addressing mode 2 store instructions.
...
llvm-svn: 119846
2010-11-19 21:35:06 +00:00
Jim Grosbach
b58de2a8c7
Delete another dead class.
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llvm-svn: 119844
2010-11-19 21:16:08 +00:00
Jim Grosbach
dc695e7de2
whitespace tweak.
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llvm-svn: 119843
2010-11-19 21:14:37 +00:00
Jim Grosbach
edef95dc56
Refactor PICSTR* instructions to really be pseudos. Nuke dead classes.
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llvm-svn: 119841
2010-11-19 21:14:02 +00:00
Jim Grosbach
a57ac3e282
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes.
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llvm-svn: 119840
2010-11-19 21:07:51 +00:00
Jim Grosbach
9e50b14e34
Add ARM binary encoding information for the rest of the indexed loads.
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llvm-svn: 119821
2010-11-19 19:41:26 +00:00
Jim Grosbach
7a92d84b46
Remove dead code.
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llvm-svn: 119815
2010-11-19 18:18:37 +00:00
Jim Grosbach
c2ac477e54
ARM LDRD binary encoding.
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llvm-svn: 119812
2010-11-19 18:16:46 +00:00
Jim Grosbach
be61a90b99
Remove hard tabs.
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llvm-svn: 119810
2010-11-19 18:01:37 +00:00
Jim Grosbach
48531dd967
Remove trailing whitespace.
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llvm-svn: 119806
2010-11-19 17:11:02 +00:00
Benjamin Kramer
6807d1b8fa
Avoid release build warnings.
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llvm-svn: 119804
2010-11-19 16:36:02 +00:00
Owen Anderson
99c5ea71f7
Fix decoding ambiguities of stdrex and ldrex.
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llvm-svn: 119801
2010-11-19 13:11:50 +00:00
Evan Cheng
46ea6d0bf1
These instructions are thumb2 only.
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llvm-svn: 119793
2010-11-19 06:28:11 +00:00
Evan Cheng
4a88903266
Fix an obvious oversight.
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llvm-svn: 119792
2010-11-19 06:15:10 +00:00
Rafael Espindola
b33e5e07e1
Change some methods in MCDwarf.cpp to be able to handle an arbitrary
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MCStreamer instead of just MCObjectStreamer. Address changes cannot
be as efficient as we have to use DW_LNE_set_addres, but at least
most of the logic is shared.
This will be used so that, with CodeGen still using EmitDwarfLocDirective,
llvm-gcc is able to produce debug_line sections without needing an
assembler that supports .loc.
llvm-svn: 119777
2010-11-19 02:26:16 +00:00
Bill Wendling
50a1812023
Add MC encodings for some Thumb instructions. Test for a few of them. The "bx
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lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...
llvm-svn: 119774
2010-11-19 01:33:10 +00:00
Bill Wendling
48cce64ab5
Use array_pod_sort because the list is contiguous.
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llvm-svn: 119769
2010-11-19 00:38:19 +00:00
Owen Anderson
fa216abdd5
Provide Thumb2 encodings for strex and ldrex.
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llvm-svn: 119768
2010-11-19 00:28:38 +00:00
Jim Grosbach
941d812765
Minor cleanups to a few llvm_unreachable() calls.
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llvm-svn: 119767
2010-11-19 00:27:09 +00:00
Bill Wendling
f433d71069
An 'unreachable' shouldn't have a '0 &&' prefix.
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llvm-svn: 119762
2010-11-19 00:05:15 +00:00
Bill Wendling
ef43273c51
Add support for parsing the writeback ("!") token.
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llvm-svn: 119761
2010-11-18 23:43:05 +00:00
Jason W Kim
331b7407c8
Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
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Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.
llvm-svn: 119760
2010-11-18 23:37:15 +00:00
Owen Anderson
ca14474db4
Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2.
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llvm-svn: 119755
2010-11-18 23:29:56 +00:00
Anton Korobeynikov
ce676f96e1
Move getInitialFrameState() to TargetFrameInfo
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llvm-svn: 119754
2010-11-18 23:25:52 +00:00
Jim Grosbach
6d88154077
ARM Encoding information for UXTAH and friends.
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llvm-svn: 119753
2010-11-18 23:24:22 +00:00
Tanya Lattner
9cac0edef3
Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first).
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Added test case.
llvm-svn: 119749
2010-11-18 22:06:46 +00:00
Bill Wendling
510e600542
Don't allocate the SmallVector of Registers. It gets messy figuring out who
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should delete what when the object gets copied around. It's also making valgrind
upset.
llvm-svn: 119747
2010-11-18 21:50:54 +00:00
Owen Anderson
2f9d8861ac
Provide Thumb2 encodings for mov's that come from MOVCC SDNodes.
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llvm-svn: 119744
2010-11-18 21:46:31 +00:00
Jim Grosbach
0651dc456a
Add ARM encoding information for LDRH post-increment.
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llvm-svn: 119743
2010-11-18 21:43:37 +00:00