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446 Commits

Author SHA1 Message Date
Jim Grosbach
fb734dff3c ARM NEON VEXT aliases for data type suffices. 
llvm-svn: 145726
 2011-12-02 23:34:39 +00:00
Jim Grosbach
b15f862d86 ARM VEXT tighten up operand classes a bit. 
llvm-svn: 145722
 2011-12-02 22:57:57 +00:00
Jim Grosbach
3b245f9c39 ARM VST1 single lane assembly parsing. 
llvm-svn: 145718
 2011-12-02 22:34:51 +00:00
Jim Grosbach
82ae7f46ea ARM VLD1 single lane assembly parsing. 
llvm-svn: 145712
 2011-12-02 22:01:52 +00:00
Jim Grosbach
a568ef0db6 Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

llvm-svn: 145693
 2011-12-02 18:52:30 +00:00
Jim Grosbach
d5c0c63223 ARM start parsing VLD1 single lane instructions. 
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.

llvm-svn: 145655
 2011-12-02 00:35:16 +00:00
Jim Grosbach
6b2f6389cc ARM parsing for VLD1 all lanes, with writeback. 
llvm-svn: 145510
 2011-11-30 19:35:44 +00:00
Jim Grosbach
fa9f6ccd62 ARM parsing for VLD1 two register all lanes, no writeback. 
llvm-svn: 145504
 2011-11-30 18:21:25 +00:00
Jim Grosbach
693ce8291c ARM parsing aliases for VLD1 single register all lanes. 
llvm-svn: 145464
 2011-11-30 01:09:44 +00:00
Jim Grosbach
9adabf4dde Tidy up a bit. 
llvm-svn: 145458
 2011-11-29 23:51:09 +00:00
Jim Grosbach
ccc984051d Add comment. 
llvm-svn: 145456
 2011-11-29 23:33:40 +00:00
Jim Grosbach
29147b45a5 ARM parsing aliases for data-size suffices on VST1. 
llvm-svn: 145454
 2011-11-29 23:21:31 +00:00
Jim Grosbach
538759efa7 ARM assembly parsing and encoding for four-register VST1. 
llvm-svn: 145450
 2011-11-29 22:58:48 +00:00
Jim Grosbach
5418e87582 ARM assembly parsing and encoding for three-register VST1. 
llvm-svn: 145442
 2011-11-29 22:38:04 +00:00
Jim Grosbach
778bed02bb ARM assembly parsing for data type suffices on NEON VMOV aliases. 
llvm-svn: 144722
 2011-11-15 22:54:42 +00:00
Jim Grosbach
4d0ad5a4e0 ARM alternate size suffices for VTRN instructions. 
rdar://10435076

llvm-svn: 144694
 2011-11-15 20:49:46 +00:00
Owen Anderson
35f049f1fb Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. 
llvm-svn: 144683
 2011-11-15 19:55:00 +00:00
Jim Grosbach
61c3f1b35b ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions. 
rdar://10435076

llvm-svn: 144650
 2011-11-15 17:49:59 +00:00
Evan Cheng
47d8f8af84 Add vmov.f32 to materialize f32 immediate splats which cannot be handled by 
integer variants. rdar://10437054

llvm-svn: 144608
 2011-11-15 02:12:34 +00:00
Jim Grosbach
2ac98a24aa ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions. 
rdar://10435076

llvm-svn: 144606
 2011-11-15 01:46:57 +00:00
Jim Grosbach
6846540505 ARM parsing datatype suffix variants for non-writeback VST1 instructions. 
rdar://10435076

llvm-svn: 144593
 2011-11-14 23:43:46 +00:00
Jim Grosbach
a1a28df278 ARM parsing datatype suffix variants for non-writeback VLD1 instructions. 
rdar://10435076

llvm-svn: 144592
 2011-11-14 23:32:59 +00:00
Jim Grosbach
8ec84fbe99 Add explanatory comment. 
llvm-svn: 144589
 2011-11-14 23:21:09 +00:00
Jim Grosbach
00283a5c8e ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions. 
rdar://10435076

llvm-svn: 144587
 2011-11-14 23:11:19 +00:00
Jim Grosbach
312b583950 Re-apply 144430, this time with the associated isel and disassmbler bits. 
Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'

llvm-svn: 144437
 2011-11-12 00:31:53 +00:00
Jim Grosbach
7fccd540c9 Oops. Missed the isel half of this. revert while I sort that out. 
llvm-svn: 144431
 2011-11-11 23:51:31 +00:00
Jim Grosbach
13af5276a1 ARM assembly parsing for VST1 two-register encoding. 
llvm-svn: 144430
 2011-11-11 23:45:47 +00:00
Jim Grosbach
76dd8a9702 ARM VST1 w/ writeback assembly parsing and encoding. 
llvm-svn: 143369
 2011-10-31 21:50:31 +00:00
Owen Anderson
5fdb303642 Specify that the high bit of the alignment field is fixed to 0 on these instructions. 
llvm-svn: 143220
 2011-10-28 20:43:24 +00:00
Jim Grosbach
fabe0f2f0b ARM assembly parsing and encoding for VLD1 with writeback. 
Four entry register lists.

llvm-svn: 142882
 2011-10-25 00:14:01 +00:00
Jim Grosbach
e8a2edd71c Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction. 
llvm-svn: 142877
 2011-10-24 23:40:46 +00:00
Jim Grosbach
688186941f ARM assembly parsing and encoding for VLD1 w/ writeback. 
Three entry register list variation.

llvm-svn: 142876
 2011-10-24 23:26:05 +00:00
Jim Grosbach
cf4fba1dd0 ARM assembly parsing and encoding for VLD1 w/ writeback. 
One and two length register list variants.

llvm-svn: 142861
 2011-10-24 22:16:58 +00:00
Jim Grosbach
4a6508dd4e ARM refactor am6offset usage for VLD1. 
Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.

llvm-svn: 142853
 2011-10-24 21:45:13 +00:00
Jim Grosbach
d964cf8939 Assembly parsing for 4-register sequential variant of VLD2. 
llvm-svn: 142704
 2011-10-21 23:58:57 +00:00
Jim Grosbach
a6e536367e Assembly parsing for 2-register sequential variant of VLD2. 
llvm-svn: 142691
 2011-10-21 22:21:10 +00:00
Jim Grosbach
68dfc88f95 Assembly parsing for 4-register variant of VLD1. 
llvm-svn: 142682
 2011-10-21 20:35:01 +00:00
Jim Grosbach
2c1ca90ac9 Assembly parsing for 3-register variant of VLD1. 
llvm-svn: 142675
 2011-10-21 20:02:19 +00:00
Jim Grosbach
6bb38d0e97 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
 2011-10-21 18:54:25 +00:00
Jim Grosbach
501c72cdc5 Remove some outdated comments. 
llvm-svn: 142653
 2011-10-21 16:14:12 +00:00
Jim Grosbach
e9d1df8266 ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
llvm-svn: 142583
 2011-10-20 15:04:25 +00:00
Jim Grosbach
972f26d936 ARM VTBX (one register) assembly parsing and encoding. 
llvm-svn: 142581
 2011-10-20 14:48:50 +00:00
Jim Grosbach
6a932d6ad1 ARM VTBL (one register) assembly parsing and encoding. 
llvm-svn: 142441
 2011-10-18 23:02:30 +00:00
Jim Grosbach
d748cf251f Yet more ARM NEON assembly parsing for the lane index operand. 
llvm-svn: 142416
 2011-10-18 20:21:17 +00:00
Jim Grosbach
ff8c26a53f ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142413
 2011-10-18 20:14:56 +00:00
Jim Grosbach
ed5cb526e2 ARM vmov assembly parsing for the lane index operand. 
llvm-svn: 142412
 2011-10-18 20:10:47 +00:00
Jim Grosbach
988b8dd4ce ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142389
 2011-10-18 18:27:07 +00:00
Jim Grosbach
2752e0b869 ARM vqdmulh assembly parsing for the lane index operand. 
llvm-svn: 142386
 2011-10-18 18:12:09 +00:00
Jim Grosbach
b56577b650 ARM vmul assembly parsing for the lane index operand. 
llvm-svn: 142381
 2011-10-18 18:01:52 +00:00
Jim Grosbach
4a138cb8d9 ARM vqdmlal assembly parsing for the lane index operand. 
llvm-svn: 142365
 2011-10-18 17:16:30 +00:00
Jim Grosbach
031bb99231 ARM assembly parsing and encoding for VMOV.i64. 
llvm-svn: 142356
 2011-10-18 16:18:11 +00:00
Jim Grosbach
bcfb4ed53c ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
llvm-svn: 142321
 2011-10-18 00:22:00 +00:00
Jim Grosbach
1e994e76a7 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. 
llvm-svn: 142303
 2011-10-17 23:09:09 +00:00
Jim Grosbach
f3d495fbbd ARM NEON "vmov.i8" immediate assembly parsing and encoding. 
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.

llvm-svn: 142293
 2011-10-17 22:26:03 +00:00
Jim Grosbach
eeb05f7532 Tidy up organization. 
llvm-svn: 142248
 2011-10-17 21:00:11 +00:00
Jim Grosbach
94980a23e6 ARM NEON assembly parsing and encoding for VDUP(scalar). 
llvm-svn: 141446
 2011-10-07 23:56:00 +00:00
Chad Rosier
3c596dbe51 Remove the VMOVQQ pseudo instruction. 
llvm-svn: 138177
 2011-08-20 00:52:40 +00:00
Chad Rosier
0d49bb37fb Remove VMOVQQQQ pseudo instruction. 
llvm-svn: 138174
 2011-08-20 00:40:14 +00:00
Owen Anderson
2e722e7cd4 Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness. 
llvm-svn: 137686
 2011-08-15 23:38:54 +00:00
Owen Anderson
894585de33 Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
llvm-svn: 137635
 2011-08-15 18:44:44 +00:00
Owen Anderson
ffe1c55752 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
 2011-08-09 20:55:18 +00:00
Bob Wilson
e241d2cd04 Add missing register constraint for some VLD3/VLD4 pseudo instructions. 
<rdar://problem/9878189>

llvm-svn: 136962
 2011-08-05 07:24:09 +00:00
Owen Anderson
7a380bac06 Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler. 
llvm-svn: 135290
 2011-07-15 18:46:47 +00:00
Owen Anderson
4cf53f7ec4 Remove unnecessary duplicate instruction definitions that simply overloaded the type of VEXT. This can be achieved with a Pat definition, and is much more disassembler friendly. 
llvm-svn: 135283
 2011-07-15 17:48:05 +00:00
Jim Grosbach
eff8e5d153 Clean up a few 80 column violations. 
llvm-svn: 132946
 2011-06-13 22:54:22 +00:00
Tanya Lattner
aa1f6df650 Fix encoding for VEXTdf. 
llvm-svn: 132486
 2011-06-02 21:25:24 +00:00
Mon P Wang
08d3b69861 Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32 
llvm-svn: 131085
 2011-05-09 17:47:27 +00:00
Mon P Wang
9aa67ff50a Fixed encoding for VEXTqf 
llvm-svn: 129101
 2011-04-07 19:56:12 +00:00
Owen Anderson
d4e1a2f2b6 Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler. 
llvm-svn: 128587
 2011-03-30 23:45:29 +00:00
Cameron Zwarich
1b8f91d2c8 Add a ARM-specific SD node for VBSL so that forms with a constant first operand 
can be recognized. This fixes <rdar://problem/9183078>.

llvm-svn: 128584
 2011-03-30 23:01:21 +00:00
Owen Anderson
d73041e884 Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist. 
llvm-svn: 128461
 2011-03-29 16:45:53 +00:00
Jim Grosbach
ee6075cda5 ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same 
as for VDUP32d and VDUP32q, respectively.

llvm-svn: 127489
 2011-03-11 20:44:08 +00:00
Jim Grosbach
3329263352 ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q 
and VDUPLN32d, respectively.

llvm-svn: 127486
 2011-03-11 20:31:17 +00:00
Jim Grosbach
431682981d ARM VREV64df and VREV64qf can just be patterns. The instruction is the same 
as for VREV64d32 and VREV64q32, respectively.

llvm-svn: 127485
 2011-03-11 20:18:05 +00:00
Bill Wendling
68934338ab * Correct encoding for VSRI. 
* Add tests for VSRI and VSLI.

llvm-svn: 127297
 2011-03-09 00:33:17 +00:00
Bill Wendling
b790c462c0 Correct the encoding for VRSRA and VSRA instructions. 
llvm-svn: 127294
 2011-03-09 00:00:35 +00:00
Bill Wendling
ab9f04b6d8 * Fix VRSHR and VSHR to have the correct encoding for the immediate. 
* Update the NEON shift instruction test to expect what 'as' produces.

llvm-svn: 127293
 2011-03-08 23:48:09 +00:00
Bill Wendling
958e854f40 Rename the narrow shift right immediate operands to "shr_imm*" operands. Also 
expand the testing of the narrowing shift right instructions.

No functionality change.

llvm-svn: 127193
 2011-03-07 23:38:41 +00:00
Bill Wendling
304dda7810 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723
 2011-03-01 01:00:59 +00:00
Bob Wilson
6bbffe19e9 Add patterns to use post-increment addressing for Neon VST1-lane instructions. 
llvm-svn: 126477
 2011-02-25 06:42:42 +00:00
Bob Wilson
46b105c6a2 Change VLD3/4 and VST3/4 for quad registers to not update the address register. 
These operations are expanded to pairs of loads or stores, and the first one
uses the address register update to produce the address for the second one.
So far, the second load/store has also updated the address register, just
for convenience, since that output has never been used.  In anticipation of
actually supporting post-increment updates for these operations, this changes
the non-updating operations to use a non-updating load/store for the second
instruction.

llvm-svn: 125013
 2011-02-07 17:43:15 +00:00
Bob Wilson
cdda05b3cc Fix some NEON instruction itineraries. 
llvm-svn: 125012
 2011-02-07 17:43:12 +00:00
Bob Wilson
22f18a7e94 Add ARM patterns to match EXTRACT_SUBVECTOR nodes. 
Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle
vectors from being translated to EXTRACT_SUBVECTOR.
Patch by Tim Northover.

The test changes are needed to keep those spill-q tests from testing aligned
spills and restores.  If the only aligned stack objects are spill slots, we
no longer realign the stack frame.  Prior to this patch, an EXTRACT_SUBVECTOR
was legalized by loading from the stack, which created an aligned frame index.
Now, however, there is nothing except the spill slot in the stack frame, so
I added an aligned alloca.

llvm-svn: 122995
 2011-01-07 04:59:04 +00:00
Bob Wilson
5f9e78fe20 Rearrange some Neon multiclasses. No functional changes. 
llvm-svn: 122119
 2010-12-18 00:42:58 +00:00
Bob Wilson
776d3f73eb Fix result type of Neon floating-point comparisons against zero. 
The result vector elements are always integers.  Radar 8782191.

llvm-svn: 122112
 2010-12-18 00:04:33 +00:00
Bob Wilson
438a9a1367 Add Neon VCVT instructions for f32 <-> f16 conversions. 
Clang is now providing intrinsics for these and so we need to support them
in the backend.  Radar 8068427.

llvm-svn: 121902
 2010-12-15 22:14:12 +00:00
Bob Wilson
33e5e902b0 Remove the rest of the *_sfp Neon instruction patterns. 
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now.  It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior.  Since that isn't obviously wrong, I've just
changed the test file.  This completes the work for Radar 8711675.

llvm-svn: 121730
 2010-12-13 23:02:37 +00:00
Bob Wilson
b189b77d9b Simplify N2VSPat, removing some unnecessary type arguments. 
llvm-svn: 121729
 2010-12-13 23:02:31 +00:00
Bob Wilson
203303291f Delete a line that I forgot to revert previously. 
llvm-svn: 121719
 2010-12-13 22:05:55 +00:00
Bob Wilson
074095ddf2 Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns. 
Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns.  The pattern
gets pretty ugly but it seems to work well.  Partial fix for Radar 8711675.

llvm-svn: 121718
 2010-12-13 21:58:05 +00:00
Bob Wilson
56b41f8b81 Use pseudo instructions for 2-register Neon instructions for scalar FP. 
Partial fix for Radar 8711675.

llvm-svn: 121716
 2010-12-13 21:05:52 +00:00
Bob Wilson
9a6d75a499 Remove unused instruction class arguments. 
llvm-svn: 121715
 2010-12-13 21:05:44 +00:00
Bob Wilson
d30768fe3e Add float patterns for Neon vld1-lane/dup and vst1-lane operations. 
llvm-svn: 121583
 2010-12-10 22:13:32 +00:00
Bob Wilson
ae683e722f Remove unused arguments. 
llvm-svn: 121582
 2010-12-10 22:13:24 +00:00
Evan Cheng
fc78767730 Making use of VFP / NEON floating point multiply-accumulate / subtraction is 
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
   of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
   additional pipeline stall. So it's frequently better to single codegen
   vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
   stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
   vmla + vmla is very bad. But this isn't ideal either:
     vmul
     vadd
     vmla
   Instead, we want to expand the second vmla:
     vmla
     vmul
     vadd
   Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
   faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
   compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
   fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
   vmla / vmls will trigger one of the special hazards.

Work in progress, only A+B are enabled.

llvm-svn: 120960
 2010-12-05 22:04:16 +00:00
Jim Grosbach
78ef3199c8 Fix copy/pasto in vmin.f32 encoding. 
llvm-svn: 120709
 2010-12-02 16:30:58 +00:00
Owen Anderson
2299afbb49 Use by-name rather than by-order matching for NEON operands. 
llvm-svn: 120507
 2010-12-01 00:28:25 +00:00
Bob Wilson
f5eece615c Fix the encoding of VLD4-dup alignment. 
The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function.  Use it
for all the VLD-dup instructions for the sake of consistency.

llvm-svn: 120358
 2010-11-30 00:00:42 +00:00
Bob Wilson
1be989686c Rename VLDnDUP instructions with double-spaced registers 
in an attempt to make things a little more consistent.

llvm-svn: 120357
 2010-11-30 00:00:38 +00:00
Bob Wilson
bd3d3d2937 Add support for NEON VLD3-dup instructions. 
The encoding for alignment in VLD4-dup instructions is still a work in progress.

llvm-svn: 120356
 2010-11-30 00:00:35 +00:00