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Author SHA1 Message Date
Chris Lattner
557951b354 Add a method useful for decimating vectors. 
llvm-svn: 27269
 2006-03-31 00:28:23 +00:00
Chris Lattner
87d3a2e045 Add the rest of the vmul instructions and the vmulsum* instructions. 
llvm-svn: 27268
 2006-03-30 23:39:06 +00:00
Chris Lattner
e35e1db8c2 fix incorrect prototypes 
llvm-svn: 27267
 2006-03-30 23:32:58 +00:00
Chris Lattner
22b7e551f1 Use a new tblgen feature to significantly shrinkify instruction definitions that 
directly correspond to intrinsics.

llvm-svn: 27266
 2006-03-30 23:21:27 +00:00
Chris Lattner
6aca6013d2 Add a bunch of new instructions for intrinsics. 
llvm-svn: 27265
 2006-03-30 23:07:36 +00:00
Chris Lattner
8fd532e8a4 regenerate 
llvm-svn: 27264
 2006-03-30 22:51:12 +00:00
Chris Lattner
39d2d17cb3 Implement Regression/TableGen/DagDefSubst.ll 
llvm-svn: 27263
 2006-03-30 22:50:40 +00:00
Chris Lattner
0220aa8d3c Dag operator should be able to be template params. 
llvm-svn: 27262
 2006-03-30 22:49:59 +00:00
Chris Lattner
e57e873543 Fix Transforms/InstCombine/2006-03-30-ExtractElement.ll 
llvm-svn: 27261
 2006-03-30 22:02:40 +00:00
Chris Lattner
f56ee2961c new testcase that crashes instcombine 
llvm-svn: 27260
 2006-03-30 22:01:08 +00:00
Evan Cheng
d3c692650f Make sure all possible shuffles are matched. 
Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.

llvm-svn: 27259
 2006-03-30 19:54:57 +00:00
Chris Lattner
69148453d0 Add vector multiply, multiply sum, pack, unpack, and lvsl/lvsr intrinsics. 
llvm-svn: 27258
 2006-03-30 18:52:02 +00:00
Evan Cheng
4150ec59a3 More logical ops patterns 
llvm-svn: 27257
 2006-03-30 07:33:32 +00:00
Evan Cheng
57d481a78a Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics 
llvm-svn: 27256
 2006-03-30 06:21:22 +00:00
Evan Cheng
82d2a6910f Add 128-bit pmovmskb intrinsic support. 
llvm-svn: 27255
 2006-03-30 00:33:26 +00:00
Evan Cheng
9ebe75e915 Change SSE pack operation definitions to fit what the intrinsics expected. 
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.

llvm-svn: 27254
 2006-03-29 23:53:14 +00:00
Evan Cheng
1b19ed24d6 Add SSE2 integer pack with saturation intrinsics. 
llvm-svn: 27253
 2006-03-29 23:09:19 +00:00
Evan Cheng
7bc3bc8246 - Added some SSE2 128-bit packed integer ops. 
- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252
 2006-03-29 23:07:14 +00:00
Evan Cheng
e96f5af925 Add a pshufhw test case. 
llvm-svn: 27251
 2006-03-29 22:51:28 +00:00
Evan Cheng
d0d3eade59 Need to special case splat after all. Make the second operand of splat 
vector_shuffle undef.

llvm-svn: 27250
 2006-03-29 19:02:40 +00:00
Evan Cheng
0e323f1e49 Use unpcklpd for v2f64 splat. 
llvm-svn: 27249
 2006-03-29 18:59:48 +00:00
Evan Cheng
e7701928bb Floating point logical operation patterns should match bit_convert. Or else 
integer vector logical operations would match andp{s|d} instead of pand.

llvm-svn: 27248
 2006-03-29 18:47:40 +00:00
Evan Cheng
84c8b5bcd9 Add more SSE intrinsics 
llvm-svn: 27247
 2006-03-29 06:07:16 +00:00
Evan Cheng
02b5de9b3e - More shuffle related bug fixes. 
- Whenever possible use ops of the right packed types for vector shuffles /
  splats.

llvm-svn: 27246
 2006-03-29 03:04:49 +00:00
Evan Cheng
6e8b924416 Another entry about shuffles. 
llvm-svn: 27245
 2006-03-29 03:03:46 +00:00
Evan Cheng
5194a37602 - Only use pshufd for v4i32 vector shuffles. 
- Other shuffle related fixes.

llvm-svn: 27244
 2006-03-29 01:30:51 +00:00
Chris Lattner
1a773f8f18 add a note 
llvm-svn: 27243
 2006-03-29 00:24:13 +00:00
Chris Lattner
c8eb55d37d new testcase 
llvm-svn: 27242
 2006-03-29 00:12:08 +00:00
Chris Lattner
9a46d1605c Bug fixes: handle constantexpr insert/extract element operations 
Handle constantpacked vectors with constantexpr elements.

This fixes CodeGen/Generic/vector-constantexpr.ll

llvm-svn: 27241
 2006-03-29 00:11:43 +00:00
Evan Cheng
e7a50a5851 Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics. 
The source operands type are v4sf with upper bits passes through.
Added matching code for these.

llvm-svn: 27240
 2006-03-28 23:51:43 +00:00
Evan Cheng
178e36174a Fixing buggy code. 
llvm-svn: 27239
 2006-03-28 23:41:33 +00:00
Evan Cheng
86b5b7cf18 Don't sort the names before outputing the intrinsic name table. It causes a 
mismatch against the enum table.
This is a part of Sabre's master plan to drive me nuts with subtle bugs that
happens to only affect x86 be. :-)

llvm-svn: 27237
 2006-03-28 22:25:56 +00:00
Chris Lattner
95a8c4fb11 When building a VVECTOR_SHUFFLE node from extract_element operations, make 
sure to build it as SHUFFLE(X, undef, mask), not SHUFFLE(X, X, mask).

The later is not canonical form, and prevents the PPC splat pattern from
matching.  For a particular splat, we go from generating this:

	li r10, lo16(LCPI1_0)
	lis r11, ha16(LCPI1_0)
	lvx v3, r11, r10
	vperm v3, v2, v2, v3

to generating:

	vspltw v3, v2, 3

llvm-svn: 27236
 2006-03-28 22:19:47 +00:00
Chris Lattner
017e8f1798 Canonicalize VECTOR_SHUFFLE(X, X, Y) -> VECTOR_SHUFFLE(X,undef,Y') 
llvm-svn: 27235
 2006-03-28 22:11:53 +00:00
Chris Lattner
bd095fd427 new testcase 
llvm-svn: 27234
 2006-03-28 20:32:12 +00:00
Chris Lattner
a623f6f696 Turn a series of extract_element's feeding a build_vector into a 
vector_shuffle node.  For this:

void test(__m128 *res, __m128 *A, __m128 *B) {
  *res = _mm_unpacklo_ps(*A, *B);
}

we now produce this code:

_test:
        movl 8(%esp), %eax
        movaps (%eax), %xmm0
        movl 12(%esp), %eax
        unpcklps (%eax), %xmm0
        movl 4(%esp), %eax
        movaps %xmm0, (%eax)
        ret

instead of this:

_test:
        subl $76, %esp
        movl 88(%esp), %eax
        movaps (%eax), %xmm0
        movaps %xmm0, (%esp)
        movaps %xmm0, 32(%esp)
        movss 4(%esp), %xmm0
        movss 32(%esp), %xmm1
        unpcklps %xmm0, %xmm1
        movl 84(%esp), %eax
        movaps (%eax), %xmm0
        movaps %xmm0, 16(%esp)
        movaps %xmm0, 48(%esp)
        movss 20(%esp), %xmm0
        movss 48(%esp), %xmm2
        unpcklps %xmm0, %xmm2
        unpcklps %xmm1, %xmm2
        movl 80(%esp), %eax
        movaps %xmm2, (%eax)
        addl $76, %esp
        ret

GCC produces this (with -fomit-frame-pointer):

_test:
        subl    $12, %esp
        movl    20(%esp), %eax
        movaps  (%eax), %xmm0
        movl    24(%esp), %eax
        unpcklps        (%eax), %xmm0
        movl    16(%esp), %eax
        movaps  %xmm0, (%eax)
        addl    $12, %esp
        ret

llvm-svn: 27233
 2006-03-28 20:28:38 +00:00
Chris Lattner
c6e37432b5 Teach Legalize how to pack VVECTOR_SHUFFLE nodes into VECTOR_SHUFFLE nodes. 
llvm-svn: 27232
 2006-03-28 20:24:43 +00:00
Chris Lattner
5b8467460a new node 
llvm-svn: 27231
 2006-03-28 19:54:42 +00:00
Chris Lattner
83ec289ebf Add a new node 
llvm-svn: 27230
 2006-03-28 19:54:11 +00:00
Chris Lattner
cad173698d Don't crash on X^X if X is a vector. Instead, produce a vector of zeros. 
llvm-svn: 27229
 2006-03-28 19:11:05 +00:00
Chris Lattner
6af8c19e4f Add an assertion 
llvm-svn: 27228
 2006-03-28 19:04:49 +00:00
Chris Lattner
93559450b8 add a note 
llvm-svn: 27227
 2006-03-28 18:56:23 +00:00
Jim Laskey
4c2d4d1912 Refactor address attributes. Add base register to frame info. 
llvm-svn: 27226
 2006-03-28 14:58:32 +00:00
Jim Laskey
eb38a3e83a Expose base register for DwarfWriter. Refactor code accordingly. 
llvm-svn: 27225
 2006-03-28 13:48:33 +00:00
Jim Laskey
a9e74309d9 More bulletproofing of llvm.dbg.declare. 
llvm-svn: 27224
 2006-03-28 13:45:20 +00:00
Jim Laskey
fa6dfa9212 Added missing paren on behalf of Ramana Radhakrishnan. 
llvm-svn: 27223
 2006-03-28 10:17:11 +00:00
Evan Cheng
0305cec743 Missed X86::isUNPCKHMask 
llvm-svn: 27222
 2006-03-28 08:27:15 +00:00
Evan Cheng
7b7954f53f movlps and movlpd should be modeled as two address code. 
llvm-svn: 27221
 2006-03-28 07:01:28 +00:00
Evan Cheng
a96380ba3f Update 
llvm-svn: 27220
 2006-03-28 06:55:45 +00:00
Evan Cheng
9f0e244187 Typo 
llvm-svn: 27219
 2006-03-28 06:53:49 +00:00