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Commit Graph

3267 Commits

Author SHA1 Message Date
Bob Wilson
56555deb30 Generalize the pre-coalescing of extract_subregs feeding reg_sequences,
replacing the overly conservative checks that I had introduced recently to
deal with correctness issues.  This makes a pretty noticable difference
in our testcases where reg_sequences are used.  I've updated one test to
check that we no longer emit the unnecessary subreg moves.

llvm-svn: 105991
2010-06-15 05:56:31 +00:00
Chris Lattner
45c451acae apparently lots of dupes.
llvm-svn: 105956
2010-06-14 20:19:03 +00:00
Chris Lattner
3fd8e8a2f5 fix a nasty bug where we were not treating available_externally
symbols as declarations in the X86 backend.  This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:

symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression

This fixes PR7353.

llvm-svn: 105954
2010-06-14 20:11:56 +00:00
Chris Lattner
add4d84c77 remove old test.
llvm-svn: 105953
2010-06-14 20:07:43 +00:00
Chris Lattner
f2d0008dce rename test
llvm-svn: 105952
2010-06-14 20:07:34 +00:00
Bob Wilson
470551e0ef Add a missing bitcast. This code used to only handle conversions between
i64 and f64 types, but now it also handle Neon vector types, so the f64 result
of VMOVDRR may need to be converted to a Neon type.  Radar 8084742.

llvm-svn: 105845
2010-06-11 22:45:25 +00:00
Bill Wendling
0e4d704f16 Testcase for r105741.
llvm-svn: 105750
2010-06-09 20:30:22 +00:00
Jakob Stoklund Olesen
9611ad3317 Mark physregs defined by inline asm as implicit.
This is a bit of a hack to make inline asm look more like call instructions.
It would be better to produce correct dead flags during isel.

llvm-svn: 105749
2010-06-09 20:05:00 +00:00
Kalle Raiskila
392de86bb5 Fix SPU to cope with vector insertelement to an undef position.
We default to inserting to lane 0.

llvm-svn: 105722
2010-06-09 09:58:17 +00:00
Kalle Raiskila
b547a95a7b Handle loading from/storing to undef pointers on SPU by inserting a
random load/store, rather than crashing llc.

llvm-svn: 105710
2010-06-09 08:29:41 +00:00
Dan Gohman
1865db1b89 LSR needs to remember inserted instructions even in postinc mode, because
there could be multiple subexpressions within a single expansion which
require insert point adjustment. This fixes PR7306.

llvm-svn: 105510
2010-06-05 00:33:07 +00:00
Evan Cheng
0fb8a935a5 Re-apply 105308 with fix.
llvm-svn: 105502
2010-06-04 23:28:13 +00:00
Dale Johannesen
fc3c949f68 More tail call removal.
llvm-svn: 105485
2010-06-04 21:14:24 +00:00
Dan Gohman
332b06bd4f Fix normalization and de-normalization of non-affine SCEVs.
llvm-svn: 105480
2010-06-04 19:16:34 +00:00
Mon P Wang
f83cdf3d18 Fixed a bug during widening where we would avoid legalizing a node. When we
replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE
when recursively updating nodes.  Since OpA has been processed, the new uses are
not examined again.  The patch checks if this occurred and it it did, updates the
new uses of OpA to use OpB.

llvm-svn: 105453
2010-06-04 01:20:10 +00:00
Dale Johannesen
f03ef32e4e Remove more tail calls.
llvm-svn: 105450
2010-06-04 01:01:24 +00:00
Dale Johannesen
0c967c579f Remove a tail call, and move some CHECKs to the
functions where they belong.

llvm-svn: 105449
2010-06-04 01:01:04 +00:00
Dan Gohman
bbd309edaa This test doesn't need the ssp attribute.
llvm-svn: 105440
2010-06-04 00:14:48 +00:00
Dale Johannesen
3492389308 Remove tail call. A tail call version will follow.
llvm-svn: 105438
2010-06-04 00:03:37 +00:00
Dale Johannesen
f80ca136ca Remove tail call to preserve this test. A tail
call version will follow.

llvm-svn: 105422
2010-06-03 21:57:48 +00:00
Dale Johannesen
f49af36017 Make this test not use tail calls. A tail call
version will follow.

llvm-svn: 105419
2010-06-03 21:53:01 +00:00
Dan Gohman
ab8153cf58 Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. It
needs to demand the high bits because it's asserting that they're zero.

llvm-svn: 105406
2010-06-03 20:21:33 +00:00
Bob Wilson
15a21b6b97 Revert 105308.
llvm-svn: 105399
2010-06-03 18:28:31 +00:00
Bill Wendling
077afde4bf Machine sink could potentially sink instructions into a block where the physical
registers it defines then interfere with an existing preg live range.

For instance, if we had something like these machine instructions:

BB#0
  ... = imul ... EFLAGS<imp-def,dead>
  test ..., EFLAGS<imp-def>
  jcc BB#2 EFLAGS<imp-use>

BB#1
  ... ; fallthrough to BB#2

BB#2
  ... ; No code that defines EFLAGS
  jcc ... EFLAGS<imp-use>

Machine sink will come along, see that imul implicitly defines EFLAGS, but
because it's "dead", it assumes that it can move imul into BB#2. But when it
does, imul's "dead" imp-def of EFLAGS is raised from the dead (a zombie) and
messes up the condition code for the jump (and pretty much anything else which
relies upon it being correct).

The solution is to know which pregs are live going into a basic block. However,
that information isn't calculated at this point. Nor does the LiveVariables pass
take into account non-allocatable physical registers. In lieu of this, we do a
*very* conservative pass through the basic block to determine if a preg is live
coming out of it.

llvm-svn: 105387
2010-06-03 07:54:20 +00:00
Eric Christopher
00f399e90a One underscore, not two.
llvm-svn: 105379
2010-06-03 04:02:59 +00:00
Eli Friedman
60c8122bb0 Implement expansion in type legalization for add/sub with overflow. The
expansion is the same as that used by LegalizeDAG.

The resulting code sucks in terms of performance/codesize on x86-32 for a
64-bit operation; I haven't looked into whether different expansions might be
better in general.

llvm-svn: 105378
2010-06-03 03:49:50 +00:00
Evan Cheng
b137439a0a Enable machine cse of instructions which define physical registers.
llvm-svn: 105308
2010-06-02 01:08:27 +00:00
Dan Gohman
3a3a65dadc Fill in missing support for ISD::FEXP, ISD::FPOWI, and friends.
llvm-svn: 105283
2010-06-01 18:35:14 +00:00
Kalle Raiskila
ed7364d3e1 Fix handling of 'load' nodes.
llvm-svn: 105269
2010-06-01 13:34:47 +00:00
Chris Lattner
14bf35ae45 fix PR6623: when optimizing for size, don't inline memcpy/memsets
that are too large.  This causes the freebsd bootloader to be too
large apparently.

It's unclear if this should be an -Os or -Oz thing.  Thoughts welcome.

llvm-svn: 105228
2010-05-31 17:30:14 +00:00
Chris Lattner
e8b65c0352 upgrade and filecheckize this test.
llvm-svn: 105227
2010-05-31 17:27:17 +00:00
Evan Cheng
fd971f18cb Remove schedule-livein-copies. It's not being used.
llvm-svn: 105095
2010-05-29 02:23:39 +00:00
Evan Cheng
96bdf3e6f1 Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments.
llvm-svn: 105092
2010-05-29 01:35:22 +00:00
Evan Cheng
849bca1ab6 Fix some latency computation bugs: if the use is not a machine opcode do not just return zero.
llvm-svn: 105061
2010-05-28 23:26:21 +00:00
Jakob Stoklund Olesen
f58cd7c838 Fix more tests that depended on the default register allocator choice.
llvm-svn: 104961
2010-05-28 17:06:30 +00:00
Dan Gohman
bcee12027f Eliminate the restriction that the array size in an alloca must be i32.
This will help reduce the amount of casting required on 64-bit targets.

llvm-svn: 104911
2010-05-28 01:14:11 +00:00
Jakob Stoklund Olesen
d76041cf58 Add a -regalloc=default option that chooses a register allocator based on the -O
optimization level.

This only really affects llc for now because both the llvm-gcc and clang front
ends override the default register allocator. I intend to remove that code later.

llvm-svn: 104904
2010-05-27 23:57:25 +00:00
Evan Cheng
68be5ab54e llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.
llvm-svn: 104891
2010-05-27 22:08:38 +00:00
Devang Patel
bdda547db4 Simplify. Eliminate unneeded debug_loc entry.
llvm-svn: 104785
2010-05-26 23:55:23 +00:00
Devang Patel
2ea3f77515 Update debug info when live-in reg is copied into a vreg.
llvm-svn: 104732
2010-05-26 20:18:50 +00:00
Dale Johannesen
81afa3569a Testcase for 104624/104619/PR7191/8023512.
Reduced from one provided by Duncan Sands, thanks!

llvm-svn: 104710
2010-05-26 17:55:45 +00:00
Dale Johannesen
9d2f1f2b16 Removing test; Chris thinks it's better to have the
bug go untested than have a testcase this large.  So be it.

llvm-svn: 104632
2010-05-25 20:40:10 +00:00
Dale Johannesen
8fd73c1910 Fix another variant of PR 7191. Also add a testcase
Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite.  8023512.

llvm-svn: 104624
2010-05-25 18:47:23 +00:00
Bob Wilson
c71b7c8c61 Thumb2 RSBS instructions were being printed without the 'S' suffix.
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.

llvm-svn: 104531
2010-05-24 18:44:06 +00:00
Evan Cheng
9b011e343c LR is in GPR, not tGPR even in Thumb1 mode.
llvm-svn: 104518
2010-05-24 18:00:18 +00:00
Evan Cheng
241d2c434e Implement @llvm.returnaddress. rdar://8015977.
llvm-svn: 104421
2010-05-22 01:47:14 +00:00
Eric Christopher
189eca1291 This test is darwin only. Make it so(tm).
llvm-svn: 104418
2010-05-22 00:55:55 +00:00
Bob Wilson
b8ebb375b6 Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.

llvm-svn: 104415
2010-05-22 00:23:12 +00:00
Eric Christopher
165bcdf8a8 Add full bss data support for darwin tls variables.
llvm-svn: 104414
2010-05-22 00:10:22 +00:00
Bob Wilson
586811b244 Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.

llvm-svn: 104380
2010-05-21 21:05:32 +00:00