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6862 Commits

Author SHA1 Message Date
Eric Christopher
d8e045d29e This defaults to GenericDomain. 
llvm-svn: 120415
 2010-11-30 09:11:07 +00:00
Eric Christopher
6a21ceab5c Implement a PseudoI class and transfer the sse instructions over to use 
it.

llvm-svn: 120412
 2010-11-30 08:57:23 +00:00
Eric Christopher
73365ae8b6 Fix insertion point in pcmp expander. 
While I'm there, clean up too many \n even for me.

llvm-svn: 120411
 2010-11-30 08:20:21 +00:00
Eric Christopher
2170738538 Fix some cleanups from my last patch. 
llvm-svn: 120410
 2010-11-30 08:10:28 +00:00
Eric Christopher
f27f0b5234 Rewrite mwait and monitor support and custom lower arguments. 
Fixes PR8573.

llvm-svn: 120404
 2010-11-30 07:20:12 +00:00
Michael J. Spencer
d5ec932c3a Merge System into Support. 
llvm-svn: 120298
 2010-11-29 18:16:10 +00:00
Rafael Espindola
9287c4b38f Move lowering of TLS_addr32 and TLS_addr64 to X86MCInstLower. 
llvm-svn: 120263
 2010-11-28 21:16:39 +00:00
Chris Lattner
a11c5c5c32 fix PR8686, accepting a 'b' suffix at the end of all the setcc 
instructions.  I choose to handle this with an asmparser hack,
though it could be handled by changing all the instruction definitions
to allow be "setneb" instead of "setne".  The asm parser hack is
better in this case, because we want the disassembler to produce
setne, not setneb.

llvm-svn: 120260
 2010-11-28 20:23:50 +00:00
Rafael Espindola
f77005db2b Define generic 1, 2 and 4 byte pc relative relocations. They are common 
and at least the 4 byte one will be needed to implement the .cfi_* directives.

llvm-svn: 120240
 2010-11-28 14:17:56 +00:00
Anton Korobeynikov
598465c605 Move more PEI-related hooks to TFI 
llvm-svn: 120229
 2010-11-27 23:05:25 +00:00
Anton Korobeynikov
c87f68e32e Move callee-saved regs spills / reloads to TFI 
llvm-svn: 120228
 2010-11-27 23:05:03 +00:00
Rafael Espindola
45cd9713f2 Lower TLS_addr32 and TLS_addr64. 
llvm-svn: 120225
 2010-11-27 20:43:02 +00:00
Rafael Espindola
6f5680f4a0 Implement the data16 prefix. 
llvm-svn: 120224
 2010-11-27 20:29:45 +00:00
Daniel Dunbar
bcc15fb05d MC/Mach-O: Switch to using MachOFormat.h. 
- I'm leaving MachO.h, because I believe it has external consumers, but I would really like to eliminate it (we have stylistic disagreements with one another).

llvm-svn: 120187
 2010-11-27 04:38:36 +00:00
Rafael Espindola
0641196380 Remove the unused TheTarget member. 
llvm-svn: 120168
 2010-11-26 04:24:21 +00:00
Rafael Espindola
e3dc1c951c Use multiple 0x66 prefixes so that all nops up to 15 bytes are a single instruction. 
llvm-svn: 120147
 2010-11-25 17:14:16 +00:00
Rafael Espindola
72c8de703d Implement the rex64 prefix. 
llvm-svn: 120017
 2010-11-23 11:23:24 +00:00
Rafael Espindola
6f069fc35f Produce a relocation for pcrel absolute values. Based on a patch by David Meyer. 
llvm-svn: 120006
 2010-11-23 07:20:12 +00:00
Wesley Peck
d589353ad0 Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. 
llvm-svn: 119990
 2010-11-23 03:31:01 +00:00
Rafael Espindola
492580fa9a Remove duplicated constants. Thanks to Jason for noticing it. 
llvm-svn: 119985
 2010-11-22 21:49:05 +00:00
Chris Lattner
dd03f96698 apparently tailcalls are better on darwin/x86-64 than on linux? 
llvm-svn: 119947
 2010-11-21 18:59:20 +00:00
Chris Lattner
4aaa7fbb98 implement PR8524, apparently mainline gas accepts movq as an alias for movd 
when transfering between i64 gprs and mmx regs.

llvm-svn: 119931
 2010-11-21 08:18:57 +00:00
Anton Korobeynikov
ff8c52bd51 Move some more hooks to TargetFrameInfo 
llvm-svn: 119904
 2010-11-20 15:59:32 +00:00
Duncan Sands
028cf0619e On X86, MEMBARRIER, MFENCE, SFENCE, LFENCE are not target memory intrinsics, 
so don't claim they are.  They are allocated using DAG.getNode, so attempts
to access MemSDNode fields results in reading off the end of the allocated
memory.  This fixes crashes with "llc -debug" due to debug code trying to
print MemSDNode fields for these barrier nodes (since the crashes are not
deterministic, use valgrind to see this).  Add some nasty checking to try
to catch this kind of thing in the future.

llvm-svn: 119901
 2010-11-20 11:25:00 +00:00
Anton Korobeynikov
ce676f96e1 Move getInitialFrameState() to TargetFrameInfo 
llvm-svn: 119754
 2010-11-18 23:25:52 +00:00
Anton Korobeynikov
269e7d3be1 Move hasFP() and few related hooks to TargetFrameInfo. 
llvm-svn: 119740
 2010-11-18 21:19:35 +00:00
Chris Lattner
c85f76f7da trivial QoI improvement. On this invalid input: 
sahf	movl	344(%rdi),%r14d
we used to produce:

t.s:2:1: error: unexpected token in argument list

^

we now produce:
t.s:1:11: error: unexpected token in argument list
sahf	movl	344(%rdi),%r14d
    	    	^

rdar://8581401

llvm-svn: 119676
 2010-11-18 02:53:02 +00:00
Rafael Espindola
7fc5cd0a58 make isVirtualSection a virtual method on MCSection. Chris' suggestion. 
llvm-svn: 119547
 2010-11-17 20:03:54 +00:00
Dan Gohman
348c3f8197 Reapply r118917. With pseudo-instruction expansion moved to 
a different pass, the complicated interaction between cmov expansion
and fast isel is no longer a concern.

llvm-svn: 119400
 2010-11-16 22:43:23 +00:00
Oscar Fuentes
690d065e70 Fix assembling X86CompilationCallback_Win64.asm on VS 10. 
Patch by Louis Zhuang!

llvm-svn: 119394
 2010-11-16 22:07:47 +00:00
Rafael Espindola
53a8ae85b7 Change the 11 byte nop to be a single instruction. 
llvm-svn: 119286
 2010-11-15 23:10:30 +00:00
Chris Lattner
b2daeac125 add fields to the .td files unconditionally, simplifying tblgen a bit. 
Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120
 2010-11-15 05:19:05 +00:00
Chris Lattner
9a0a840839 add targetoperand flags for jump tables, constant pool and block address 
nodes to indicate when ha16/lo16 modifiers should be used.  This lets
us pass PowerPC/indirectbr.ll.

The one annoying thing about this patch is that the MCSymbolExpr isn't
expressive enough to represent ha16(label1-label2) which we need on
PowerPC.  I have a terrible hack in the meantime, but this will have
to be revisited at some point.

Last major conversion item left is global variable references.

llvm-svn: 119105
 2010-11-15 02:46:57 +00:00
Anton Korobeynikov
794259aec0 Attempt to unbreak cmake-based builds 
llvm-svn: 119098
 2010-11-15 00:48:12 +00:00
Anton Korobeynikov
76c52dcf44 First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place 
llvm-svn: 119097
 2010-11-15 00:06:54 +00:00
Chris Lattner
b347be831c tidy up, no functionality change. 
llvm-svn: 119092
 2010-11-14 23:32:42 +00:00
Chris Lattner
51168d6510 move the pic base symbol stuff up to MachineFunction 
since it is trivial and will be shared between ppc and x86.
This substantially simplifies the X86 backend also.

llvm-svn: 119089
 2010-11-14 22:48:15 +00:00
Chris Lattner
09ea2ce78f simplify getPICBaseSymbol a bit. 
llvm-svn: 119088
 2010-11-14 22:37:11 +00:00
Chris Lattner
3e3e29381e random acts of tidiness. 
llvm-svn: 119049
 2010-11-14 18:09:50 +00:00
Peter Collingbourne
4ec6b2dbe7 Recognise 32-bit ror-based bswap implementation used by uclibc 
llvm-svn: 119007
 2010-11-13 19:54:30 +00:00
Peter Collingbourne
6c3094234e Support ; as asm separator 
llvm-svn: 119006
 2010-11-13 19:54:23 +00:00
Daniel Dunbar
2ba9f79194 MC: Simplify Mach-O and ELF object writer implementations. 
- What was I thinking?????

llvm-svn: 118992
 2010-11-13 07:33:40 +00:00
Dan Gohman
a4aa69cf2a Revert r118917, which is implicated in the llvm-gcc-i386-linux-selfhost failure. 
llvm-svn: 118954
 2010-11-13 00:31:40 +00:00
Dan Gohman
8b86287a06 When the definition of an address value is in a different block 
from the user of the address, fall back to just using the
address in a register instead of bailing out of fast-isel
altogether.

llvm-svn: 118917
 2010-11-12 19:14:00 +00:00
Chris Lattner
2a70c4e38a accept lret as an alias for lretl, fixing the reopened part of PR8592 
llvm-svn: 118916
 2010-11-12 18:54:56 +00:00
Chris Lattner
612039e538 implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix. 
llvm-svn: 118903
 2010-11-12 17:41:20 +00:00
Chris Lattner
bcdb696f6c tidy up. 
llvm-svn: 118896
 2010-11-12 17:24:29 +00:00
Dale Johannesen
659061fcd3 Remove possibly useful info from comment, per Chris. 
llvm-svn: 118865
 2010-11-12 00:43:18 +00:00
Rafael Espindola
5766346831 Remove some explicit arguments to getELFSection. This is 
a leftover from the removal of isExplicit.

llvm-svn: 118774
 2010-11-11 03:40:25 +00:00
Bruno Cardoso Lopes
9f9f796756 Fix PR8211 
llvm-svn: 118445
 2010-11-08 21:24:59 +00:00
Chris Lattner
24ba201941 implement aliases for div/idiv that have an explicit A register operand, 
implementing rdar://8431864

llvm-svn: 118364
 2010-11-06 22:41:18 +00:00
Chris Lattner
25f31dcc8f add aliases for movs between seg registers and mem. There are multiple 
different forms of this instruction (movw/movl/movq) which we reported
as being ambiguous.  Since they all do the same thing, gas just picks the
one with the shortest encoding.  Follow its lead here.

This implements rdar://8208615

llvm-svn: 118362
 2010-11-06 22:35:34 +00:00
Chris Lattner
5cd42cb6f4 move the "sh[lr]d op,op" -> "shld $1, op,op" aliases to the .td file. 
llvm-svn: 118361
 2010-11-06 22:25:39 +00:00
Chris Lattner
95add4d79a work-in-progress 
llvm-svn: 118358
 2010-11-06 22:05:43 +00:00
Chris Lattner
0d6d870628 go to great lengths to work around a GAS bug my previous patch 
exposed:

GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)"
even though st(0) is implicit in all other fp stack instructions.

Fortunately, there is an alias for fcomip named "fcompi" and gas does
accept the default argument for the alias (boggle!).

As such, switch the canonical form of this instruction to "pi" instead
of "ip".  This makes the code generator and disassembler generate pi,
avoiding the gas bug.

llvm-svn: 118356
 2010-11-06 21:37:06 +00:00
Chris Lattner
bbd318b76a rework the rotate-by-1 instructions to be defined like the 
shift-by-1 instructions, where the asmstring doesn't contain
the implicit 1.  It turns out that a bunch of these rotate
instructions were completely broken because they used 1 
instead of $1.

This fixes assembly mismatches on "rclb	$1, %bl" and friends,
where we used to generate the 3 byte form, we now generate the
proper 2-byte form.

llvm-svn: 118355
 2010-11-06 21:23:40 +00:00
Chris Lattner
af1f50772a change the fp comparison instructions to not have %st0 explicitly 
listed in its asm string, for consistency with the other similar
instructions.

llvm-svn: 118354
 2010-11-06 20:55:09 +00:00
Chris Lattner
b64f8e10ab move the plethora of fp stack aliases to the .td file. 
llvm-svn: 118353
 2010-11-06 20:47:38 +00:00
Chris Lattner
4834890f0a add (and document) the ability for alias results to have 
fixed physical registers.  Start moving fp comparison
aliases to the .td file (which default to using %st1 if
nothing is specified).

llvm-svn: 118352
 2010-11-06 19:57:21 +00:00
Chris Lattner
c0e756dc47 generalize alias support to allow the result of an alias to 
add fixed immediate values.  Move the aad and aam aliases to
use this, and document it.

llvm-svn: 118350
 2010-11-06 19:25:43 +00:00
Chris Lattner
a7c7312e55 move fnstsw aliases to .td file, fix typo 
llvm-svn: 118349
 2010-11-06 18:58:32 +00:00
Chris Lattner
b686fb93c7 move in/out aliases to the .td files. 
llvm-svn: 118348
 2010-11-06 18:52:40 +00:00
Chris Lattner
6b905e3a10 move sldt, imul, and movabsq aliases from c++ to .td file. 
llvm-svn: 118347
 2010-11-06 18:44:26 +00:00
Chris Lattner
1beb2b3fc5 correct suffix matching to search for s/l/t suffixes on 
floating point stack instructions instead of looking for b/w/l/q.

This fixes issues where we'd accidentally match fistp to fistpl,
when it is in fact an ambiguous instruction.

This changes the behavior of llvm-mc to reject fstp, which was the
correct fix for rdar://8456389:
t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt')
fstp	(%rax)

it also causes us to correctly reject fistp and fist, which addresses
PR8528:

t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl')
fistp (%rax)
^
t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl')
fist (%rax)
^

Thanks to Ismail Donmez for tracking down the issue here!

llvm-svn: 118346
 2010-11-06 18:28:02 +00:00
Chris Lattner
637f4910c3 fix a bug where we had an implicit assumption that the 
result instruction operand numbering matched the result pattern.

Fixing this allows us to move the xchg/test aliases to the .td file.

llvm-svn: 118334
 2010-11-06 08:20:59 +00:00
Chris Lattner
4fd3b4ad94 move the lcall/ljmp aliases to the .td file. 
llvm-svn: 118332
 2010-11-06 07:48:45 +00:00
Chris Lattner
66c868f386 move the "movsd -> movsl" alias to the .td files, 
tidy up the movsx and movzx aliases.

llvm-svn: 118331
 2010-11-06 07:34:58 +00:00
Chris Lattner
ec0ef3385d fix some bugs in the alias support, unblocking changing of "clr" aliases 
from c++ hacks to proper .td InstAlias definitions.  Change them!

llvm-svn: 118330
 2010-11-06 07:31:43 +00:00
Chris Lattner
5d1361e9ed Reimplement BuildResultOperands to be in terms of the result instruction's 
operand list instead of the operand list redundantly declared on the alias
or instruction.

With this change, we finally remove the ins/outs list on the alias.  Before:
  def : InstAlias<(outs GR16:$dst), (ins GR8 :$src),
                  "movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;
After:
  def : InstAlias<"movsx $src, $dst",
                  (MOVSX16rr8W GR16:$dst, GR8:$src)>;

This also makes the alias mechanism more general and powerful, which will
be exploited in subsequent patches.

llvm-svn: 118329
 2010-11-06 07:14:44 +00:00
Jim Grosbach
a85416eb77 Allow targets to specify the MachO CPUType/CPUSubtype information. 
llvm-svn: 118288
 2010-11-05 18:48:58 +00:00
Duncan Sands
1af5c00d3c When passing a huge parameter using the byval mechanism, a long 
sequence of loads and stores was being generated to perform the
copy on the x86 targets if the parameter was less than 4 byte
aligned, causing llc to use up vast amounts of memory and time.
Use a "rep movs" form instead.  PR7170.

llvm-svn: 118260
 2010-11-04 21:16:46 +00:00
Duncan Sands
3bf2a701a5 In the calling convention logic, ValVT is always a legal type, 
and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.

llvm-svn: 118245
 2010-11-04 10:49:57 +00:00
Duncan Sands
41edf30895 Simplify uses of MVT and EVT. An MVT can be compared directly 
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.

llvm-svn: 118169
 2010-11-03 12:17:33 +00:00
Duncan Sands
f6e5e02c9b Inside the calling convention logic LocVT is always a simple 
value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.

llvm-svn: 118167
 2010-11-03 11:35:31 +00:00
Chris Lattner
f94c2b782a rearrange a bit. 
llvm-svn: 117967
 2010-11-01 23:07:52 +00:00
Chris Lattner
b0ac93cf15 use our fancy new MnemonicAlias mechanism to remove a bunch of hacks 
from X86AsmParser.cpp

llvm-svn: 117952
 2010-11-01 21:06:34 +00:00
Chris Lattner
d595d1f4d7 "mov[zs]x (mem), GR16" are not ambiguous: the mem 
must be 8 bits.  Support this memory form.

llvm-svn: 117902
 2010-11-01 05:41:10 +00:00
Chris Lattner
81d051481e Implement enough of the missing instalias support to get 
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901
 2010-11-01 05:34:34 +00:00
Chris Lattner
0a4807eefc make the asm matcher emitter reject instructions that have comments 
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897
 2010-11-01 04:44:29 +00:00
Chris Lattner
9da275f86b reject instructions that contain a \n in their asmstring. Mark 
various X86 and ARM instructions that are bitten by this as isCodeGenOnly,
as they are.

llvm-svn: 117884
 2010-11-01 00:46:16 +00:00
Chris Lattner
a4c36d0efe fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
 2010-10-31 19:22:57 +00:00
Chris Lattner
5d088218e5 two changes: make the asmmatcher generator ignore ARM pseudos properly, 
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.

llvm-svn: 117861
 2010-10-31 19:15:18 +00:00
Chris Lattner
8aaac91ca4 sketch out the planned instruction alias mechanism, add some comments about 
how the push/pop mnemonic aliases are wrong.

llvm-svn: 117857
 2010-10-31 18:43:46 +00:00
Duncan Sands
92f33ea784 Factorize the duplicated logic for choosing the right argument 
calling convention out of the fast and normal ISel files, and
into the calling convention TD file.

llvm-svn: 117856
 2010-10-31 13:21:44 +00:00
Duncan Sands
0f49c49476 Remove CCAssignFnForRet from X86 FastISel in favour of RetCC_X86, 
which has the same logic specified in the CallingConv TD file.
This brings FastISel in line with the standard X86 ISel.

llvm-svn: 117855
 2010-10-31 13:02:38 +00:00
Chris Lattner
49227ad505 Resolve a terrible hack in tblgen: instead of hardcoding 
"In32BitMode" and "In64BitMode" into tblgen, allow any
predicate that inherits from AssemblerPredicate.

llvm-svn: 117831
 2010-10-30 19:38:20 +00:00
Chris Lattner
15e92ddd01 Implement (and document!) support for MnemonicAlias's to have Requires 
directives, allowing things like this:

def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>;
def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>;

Move the rest of the X86 MnemonicAliases over to the .td file.

llvm-svn: 117830
 2010-10-30 19:23:13 +00:00
Chris Lattner
441672d7cb really zap alias. 
llvm-svn: 117824
 2010-10-30 18:23:25 +00:00
Chris Lattner
ba9271be5b move fcompi alias to .td file and zap some useless code. 
llvm-svn: 117823
 2010-10-30 18:22:53 +00:00
Chris Lattner
1b3b2e113f move rep aliases to td file 
llvm-svn: 117822
 2010-10-30 18:17:33 +00:00
Chris Lattner
49f977366f move sal aliases to .td file. 
llvm-svn: 117821
 2010-10-30 18:14:54 +00:00
Chris Lattner
54892b4d8d fix an encoding mismatch where "sal %eax, 1" was not using the short encoding 
for shl.  Caught by inspection.

llvm-svn: 117820
 2010-10-30 18:13:10 +00:00
Chris Lattner
38179edecd move a bunch more aliases from .cpp -> .td file. 
llvm-svn: 117819
 2010-10-30 18:07:17 +00:00
Chris Lattner
ac7f4957b1 move cmov aliases to .td file. 
llvm-svn: 117818
 2010-10-30 17:56:50 +00:00
Chris Lattner
acec7b7d46 move setcc and jcc aliases from .cpp to .td 
llvm-svn: 117817
 2010-10-30 17:51:45 +00:00
Chris Lattner
e90ff8dcb6 move some code. 
llvm-svn: 117816
 2010-10-30 17:38:55 +00:00
Chris Lattner
7c61e4bca2 implement (and document!) the first kind of MC assembler alias, which 
just remaps one mnemonic to another.  Convert a few of the X86 aliases
from .cpp to .td code.

llvm-svn: 117815
 2010-10-30 17:36:36 +00:00
Jim Grosbach
951667ac39 Clean up comments. 
llvm-svn: 117785
 2010-10-30 13:48:28 +00:00
Chris Lattner
45c679522d stay out of the reserved namespace 
llvm-svn: 117773
 2010-10-30 04:57:14 +00:00
John Thompson
6115a7f1d4 Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. 
llvm-svn: 117667
 2010-10-29 17:29:13 +00:00
Dale Johannesen
b78530f9b0 Fix pastos in handling of AVX cvttsd2si, PR8491. 
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!

llvm-svn: 117514
 2010-10-28 00:35:54 +00:00
Kevin Enderby
a53cc6a764 Added the x86 instruction ud2b (2nd official undefined instruction). 
llvm-svn: 117485
 2010-10-27 20:46:49 +00:00
Michael J. Spencer
5518dda87e x86-Win32: Switch ftol2 calling convention from stdcall to C. 
llvm-svn: 117474
 2010-10-27 18:52:38 +00:00
Kevin Enderby
74a2614673 Yet another tweak to X86 instructions to add ud2a as an alias to ud2 
(still to add ud2b).

llvm-svn: 117435
 2010-10-27 03:01:02 +00:00
Kevin Enderby
d22f3b9de7 Another tweak to X86 instructions to add the missing flex instruction (without 
the wait prefix).

llvm-svn: 117434
 2010-10-27 02:53:04 +00:00
Kevin Enderby
e812b356cc Tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
 2010-10-27 02:32:19 +00:00
Kevin Enderby
d5235bb45c Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc 
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
 2010-10-27 00:59:28 +00:00
Dale Johannesen
e7f07349e4 Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches 
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet).  No functional change except
for dump output.

llvm-svn: 117413
 2010-10-26 23:11:10 +00:00
Rafael Espindola
adaf2ea5c6 handle X86::EH_RETURN64 and X86::EH_RETURN. 
llvm-svn: 117378
 2010-10-26 18:09:55 +00:00
Rafael Espindola
e38790534e Implement some relaxations for arithmetic instructions. The limitation 
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.

llvm-svn: 117364
 2010-10-26 14:09:12 +00:00
Dale Johannesen
2566d39d07 An stdcall function calling a non-stdcall function 
cannot use tailcall.  PR 8461.

llvm-svn: 117322
 2010-10-25 22:17:05 +00:00
Rafael Espindola
c6e7790c4b Add X86::reloc_global_offset_table and use it to have a single place where 
we check for _GLOBAL_OFFSET_TABLE_.

llvm-svn: 117241
 2010-10-24 17:35:42 +00:00
Benjamin Kramer
ed68a7877c Make the disassembler tables const so they end up in read-only memory. 
llvm-svn: 117206
 2010-10-23 09:10:44 +00:00
Michael J. Spencer
87c8212d41 X86: Emit _fltused instead of __fltused on Windows x64. 
llvm-svn: 117205
 2010-10-23 09:06:59 +00:00
Chandler Carruth
ea67aaa252 Remove a define which is never referenced. 
llvm-svn: 117202
 2010-10-23 08:25:16 +00:00
Chandler Carruth
7799a873bb Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names 
until other LLVM projects using these are cleaned up.

llvm-svn: 117200
 2010-10-23 08:10:43 +00:00
Wesley Peck
488027efa3 Making the e_machine configurable by the target backend in ELFObjectWriter. 
llvm-svn: 117099
 2010-10-22 15:52:49 +00:00
Andrew Trick
b9e8700beb Reverting r117031 to cleanup valgrind errors. 
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.

llvm-svn: 117087
 2010-10-22 03:58:29 +00:00
Sean Callanan
9a40554de4 Fixed handling of immediate operand sizes, which 
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix.  Also added
a test case for this.

llvm-svn: 117084
 2010-10-22 01:24:11 +00:00
Kevin Enderby
c63105a064 More tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler allows
for these instructions.  Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).

llvm-svn: 117031
 2010-10-21 17:16:46 +00:00
Duncan Sands
0c166168a0 Remove some variables that are never really used 
(gcc-4.6 warns about these).

llvm-svn: 117021
 2010-10-21 16:03:28 +00:00
Duncan Sands
8c5f243aa0 Add parentheses to pacify gcc, which warns otherwise. 
llvm-svn: 117020
 2010-10-21 16:02:12 +00:00
Michael J. Spencer
5a68d7ce94 X86: Add alloca probing to dynamic alloca on Windows. Fixes PR8424. 
llvm-svn: 116984
 2010-10-21 01:41:01 +00:00
Michael J. Spencer
b9cffadc06 CodeGen-Windows: Only emit _fltused if a VarArg function is called with floating point args. 
This should be the minimum set of functions that could possibly need it.

llvm-svn: 116978
 2010-10-21 00:08:21 +00:00
Michael J. Spencer
54b462089f Fix Whitespace. 
llvm-svn: 116972
 2010-10-20 23:40:27 +00:00
Dale Johannesen
58fe3193a6 Remove Synthesizable from the Type system; as MMX vector 
types are no longer Legal on X86, we don't need it.
No functional change.  8499854.

llvm-svn: 116947
 2010-10-20 21:32:10 +00:00
Rafael Espindola
0a50bbaee1 Handle _GLOBAL_OFFSET_TABLE_ correctly. 
llvm-svn: 116932
 2010-10-20 16:46:08 +00:00
Evan Cheng
1c8dafd12a Re-enable register pressure aware machine licm with fixes. Hoist() may have 
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.

llvm-svn: 116845
 2010-10-19 18:58:51 +00:00
Daniel Dunbar
6ff550c84d Revert r116781 "- Add a hook for target to determine whether an instruction def 
is", which breaks some nightly tests.

llvm-svn: 116816
 2010-10-19 17:14:24 +00:00
Michael J. Spencer
e528f2588f X86: Add MS-CRT libcalls. 
llvm-svn: 116801
 2010-10-19 07:32:52 +00:00
Michael J. Spencer
cd6be63d05 Fix Whitespace. 
llvm-svn: 116800
 2010-10-19 07:32:42 +00:00
Evan Cheng
9c3f6f486e - Add a hook for target to determine whether an instruction def is 
"long latency" enough to hoist even if it may increase spilling. Reloading
  a value from spill slot is often cheaper than performing an expensive
  computation in the loop. For X86, that means machine LICM will hoist
  SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
  instructions.
- Enable register pressure aware machine LICM by default.

llvm-svn: 116781
 2010-10-19 00:55:07 +00:00
Kevin Enderby
8a3030c6af Added a few tweaks to the Intel Descriptor-table support instructions to allow 
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes.  This is again for use just with assembly source for llvm-mc .

llvm-svn: 116773
 2010-10-19 00:01:44 +00:00
Rafael Espindola
7cc236c87f Produce ELF::R_386_GOTPC relocations. 
llvm-svn: 116728
 2010-10-18 18:36:12 +00:00
Kevin Enderby
cb18d38b76 Added a handful of x86-32 instructions that were missing so that llvm-mc would 
be more complete.  These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files.  Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added.  Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records.  More missing instructions will be coming.

llvm-svn: 116716
 2010-10-18 17:04:36 +00:00
Rafael Espindola
be5c52d2dc Add a MCObjectFormat class so that code common to all targets that use a 
single object format can be shared.

This also adds support for

mov zed+(bar-foo), %eax

on ELF and COFF targets.

llvm-svn: 116675
 2010-10-16 18:23:53 +00:00
Michael J. Spencer
e57b670425 X86-Windows: Emit an undefined global __fltused symbol when targeting Windows 
if any floating point arguments are passed to an external function.

llvm-svn: 116665
 2010-10-16 08:25:41 +00:00
Rafael Espindola
b1ae74bd73 Fix another case where we were preferring instructions with large 
immediates instead of 8 bits ones.

llvm-svn: 116410
 2010-10-13 17:14:25 +00:00
Rafael Espindola
ff7f11c151 Fix PR8365 by adding a more specialized Pat that checks if an 'and' with 
8 bit constants can be used.

llvm-svn: 116403
 2010-10-13 13:31:20 +00:00
Evan Cheng
eefee972cf Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457. 
llvm-svn: 116368
 2010-10-12 23:19:28 +00:00
Eric Christopher
303692631e Combine these together - should probably have some text associated 
that says what why what we just asserted is wrong.

llvm-svn: 116333
 2010-10-12 19:44:17 +00:00
Nick Lewycky
a6815ae877 Mark variable 'NoImplicitFloatOps' used only in an assert as used. 
llvm-svn: 116323
 2010-10-12 18:18:03 +00:00
Dan Gohman
d904add908 Initial va_arg support for x86-64. Patch by David Meyer! 
llvm-svn: 116319
 2010-10-12 18:00:49 +00:00
Jakob Stoklund Olesen
499fe39d23 Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions. 
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

llvm-svn: 116314
 2010-10-12 17:15:00 +00:00
Andrew Trick
5704a15e36 Fixes bug 8297: i386 cmpxchg8b, missing MachineMemOperand 
llvm-svn: 116214
 2010-10-11 19:02:04 +00:00
Michael J. Spencer
08b96a9209 X86: Call ulldiv and ftol2 on Windows instead of their libgcc eqivilents. 
llvm-svn: 116188
 2010-10-11 05:29:15 +00:00
Michael J. Spencer
8f7251a0e9 X86: MinGW should always use libgcc on Windows. 
llvm-svn: 116177
 2010-10-10 23:11:06 +00:00
Michael J. Spencer
b13cb4dd72 X86: Call _alldiv instead of __divdi3 on Windows (excluding cygwin). 
llvm-svn: 116174
 2010-10-10 22:04:34 +00:00
Michael J. Spencer
ae56350c76 Fix Whitespace. 
llvm-svn: 116173
 2010-10-10 22:04:20 +00:00
Michael J. Spencer
1c60bd155b Fix Whitespace. 
llvm-svn: 116149
 2010-10-09 11:00:50 +00:00