Chris Lattner
68ff81a2e6
add jit support for the new psuedo instructions I added for
...
the add/or xform. The JIT isn't mcized yet, boo.
This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.
llvm-svn: 116125
2010-10-08 23:59:27 +00:00
Chris Lattner
2176ca6377
machine a mutable machineinstr down into emitInstruction.
...
llvm-svn: 116124
2010-10-08 23:54:01 +00:00
Cameron Esfahani
664317d6cd
Recommit 116056, now with the missing file...
...
llvm-svn: 116083
2010-10-08 19:24:18 +00:00
Andrew Trick
0d8a3d67e0
reverting 116056: win64_params.ll may need to be conditionalized?
...
llvm-svn: 116063
2010-10-08 17:22:42 +00:00
Cameron Esfahani
a9f8bb1356
Small patch to restore home register stack space allocation for the Win64 case. Add test case. This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.
...
llvm-svn: 116056
2010-10-08 10:31:30 +00:00
Chris Lattner
244e13f439
fix a subtle bug I introduced in my refactoring, where we stopped preferring
...
the i8 versions of instructions in some cases. In test6, we started
generating:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
## <MCInst #478 CMP64mi32
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
instead of:
cmpq $0, -8(%rsp) ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
## <MCInst #479 CMP64mi8
## <MCOperand Reg:114>
## <MCOperand Imm:1>
## <MCOperand Reg:0>
## <MCOperand Imm:-8>
## <MCOperand Reg:0>
## <MCOperand Imm:0>>
Fix this and add some comments.
llvm-svn: 116053
2010-10-08 05:12:14 +00:00
Chris Lattner
82ce325f16
reapply: Use the new TB_NOT_REVERSABLE flag instead of special
...
reapply: reimplement the second half of the or/add optimization. We should now
with no changes. Turns out that one missing "Defs = [EFLAGS]" can upset things
a bit.
llvm-svn: 116040
2010-10-08 03:57:25 +00:00
Chris Lattner
fbdd285dd6
reapply the patch reverted in r116033:
...
"Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'"
With a critical fix: the add pseudos clobber EFLAGS.
llvm-svn: 116039
2010-10-08 03:54:52 +00:00
Daniel Dunbar
d3b6b8bf2b
Revert "Reimplement (part of) the or -> add optimization. Matching 'or' into
...
'add'", which seems to have broken just about everything.
llvm-svn: 116033
2010-10-08 02:07:32 +00:00
Daniel Dunbar
59848f6703
Revert "Use the new TB_NOT_REVERSABLE flag instead of special ", which depends
...
on r116007, which I am about to revert.
llvm-svn: 116032
2010-10-08 02:07:29 +00:00
Daniel Dunbar
983fae5a86
Revert "reimplement the second half of the or/add optimization. We should now",
...
which depends on r116007, which I am about to revert.
llvm-svn: 116031
2010-10-08 02:07:26 +00:00
Chris Lattner
7577cb7b49
reimplement the second half of the or/add optimization. We should now
...
only end up emitting LEA instead of OR. If we aren't able to promote
something into an LEA, we should never be emitting it as an ADD.
Add some testcases that we emit "or" in cases where we used to produce
an "add".
llvm-svn: 116026
2010-10-08 01:05:10 +00:00
Chris Lattner
d62e94b465
Use the new TB_NOT_REVERSABLE flag instead of special
...
casing FsMOVAPDrr/FsMOVAPSrr.
llvm-svn: 116016
2010-10-08 00:03:02 +00:00
Chris Lattner
72e7e84c3f
simplify some map operations.
...
llvm-svn: 116014
2010-10-07 23:57:02 +00:00
Chris Lattner
d8f05bf65e
Reimplement (part of) the or -> add optimization. Matching 'or' into 'add'
...
is general goodness because it allows ORs to be converted to LEA to avoid
inserting copies. However, this is bad because it makes the generated .s
file less obvious and gives valgrind heartburn (tons of false positives in
bitfield code).
While the general fix should be in valgrind, we can at least try to avoid
emitting ADD instructions that *don't* get promoted to LEA. This is more
work because it requires introducing pseudo instructions to represents
"add that knows the bits are disjoint", but hey, people really love valgrind.
This fixes this testcase:
https://bugs.kde.org/show_bug.cgi?id=242137#c20
the add r/i cases are coming next.
llvm-svn: 116007
2010-10-07 23:36:18 +00:00
Chris Lattner
2212441ff7
Reduce casting in various tables by defining the table
...
with the right types.
llvm-svn: 116001
2010-10-07 23:08:41 +00:00
Chris Lattner
17850b2677
simplify code: don't build up vector only to assert it is empty.
...
llvm-svn: 115997
2010-10-07 22:26:19 +00:00
Chris Lattner
16aa36001d
convert test to use the existing classes that the multipatterns
...
use. Since TEST is completely different than all other binops,
don't define a multipattern for it.
This completes factorization of binops.
llvm-svn: 115982
2010-10-07 21:31:03 +00:00
Chris Lattner
bd89233607
convert cmp to use a multipattern
...
llvm-svn: 115978
2010-10-07 20:56:25 +00:00
Evan Cheng
7c89d70f27
Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311
...
llvm-svn: 115977
2010-10-07 20:50:20 +00:00
Chris Lattner
4b9e6fd743
reduce redundancy between pattern copies.
...
llvm-svn: 115968
2010-10-07 20:14:23 +00:00
Chris Lattner
41b3817cbd
the opcode for BinOpMI/BinOpMI8 is always the same, remove the argument.
...
llvm-svn: 115967
2010-10-07 20:06:24 +00:00
Chris Lattner
d7f7dc04f5
convert adc/sbb to a multipattern. Because the adde/sube nodes
...
are not defined as returning EFLAGS (like add_flag and friends),
the entire multipattern and several of the subclasses need to be
cloned.
This could be handled through better instantiation support in tblgen,
but it isn't meta enough.
llvm-svn: 115964
2010-10-07 20:01:55 +00:00
Jakob Stoklund Olesen
7f38b44415
Fix obvious mistake pointed out by Michael Spencer.
...
llvm-svn: 115952
2010-10-07 18:47:10 +00:00
Chris Lattner
f0d9834e08
add support for isConvertibleToThreeAddress to ArithBinOpEFLAGS,
...
allowing us to convert ADD over. deletes 160 lines of .td file.
llvm-svn: 115897
2010-10-07 01:37:01 +00:00
Chris Lattner
dea1395cfe
Fix a few issues in ArithBinOpEFLAGS that made it specific to and.
...
Start using ArithBinOpEFLAGS for OR, XOR, and SUB.
This removes 500 lines from the .td file. Now AND/OR/XOR/SUB are all
defined exactly the same way instead of being close relatives.
llvm-svn: 115896
2010-10-07 01:26:27 +00:00
Chris Lattner
f1f5df212b
Convert 'and' to single instance of a multipattern
...
which instantiates the 34 versions of and all in one
swoop. The BaseOpc/BaseOpc2/BaseOpc4 stuff should not
be required, but tblgen's feeble brain explodes when I
use Or4<BaseOpc>.V in the multipattern.
No change in the generated .inc files.
llvm-svn: 115893
2010-10-07 01:10:20 +00:00
Chris Lattner
a2b51bb341
add a new BinOpAI class to represent the immediate form that directly acts on EAX.
...
This does change the generated .inc files to include the implicit use/def of eax.
Since these instructions are only generated by the assembler and disassembler it
doesn't actually matter though.
llvm-svn: 115885
2010-10-07 00:43:39 +00:00
Chris Lattner
0df71280d1
add a bunch of classes for other common patterns.
...
As usual, no change in generated .inc files.
llvm-svn: 115882
2010-10-07 00:35:28 +00:00
Chris Lattner
9b3a494cdb
Define a new BinOpRI8 class and use it to define the imm8 versions of and.
...
llvm-svn: 115880
2010-10-07 00:12:45 +00:00
Jakob Stoklund Olesen
5e329859cd
Constrain the offset register to a *_NOSP register class when inserting LEA
...
instructions.
This unbreaks the machine code verifier and fixes PR8317.
llvm-svn: 115879
2010-10-07 00:07:26 +00:00
Chris Lattner
b520abade4
add the pattern operator to match to X86TypeInfo, use this to
...
convert AND64ri32 to use BinOpRI.
llvm-svn: 115878
2010-10-07 00:01:39 +00:00
Jakob Stoklund Olesen
8c1eafb4cb
Properly handle GR32_NOSP in X86RegisterInfo::getMatchingSuperRegClass.
...
This function looks like it is about ready to be generated by TebleGen.
llvm-svn: 115876
2010-10-06 23:56:46 +00:00
Chris Lattner
30c9a175a3
enhance X86TypeInfo to include information about the encoding and
...
operand kind for immediates. Use these to define a new BinOpRI
class and switch AND8/16/32ri over to it. AND64ri32 needs some
more refactoring before it can make the switcheroo.
llvm-svn: 115752
2010-10-06 05:55:42 +00:00
Chris Lattner
e9e2d51853
add a class for _REV nodes.
...
llvm-svn: 115748
2010-10-06 05:35:22 +00:00
Chris Lattner
88ccb4e6b5
sink more intelligence into the ITy base class. Now it knows
...
that i8 operations are even and i16,i32,i64 operations have a
low opcode bit set (they are odd).
llvm-svn: 115747
2010-10-06 05:28:38 +00:00
Chris Lattner
96dd50c055
refactor things a bit, now the REX_W and OpSize prefix bytes are inferred from the type info.
...
llvm-svn: 115745
2010-10-06 05:20:57 +00:00
Chris Lattner
7956e6b995
with tblgen suitably extended, we can now get the load node from typeinfo.
...
llvm-svn: 115744
2010-10-06 04:58:43 +00:00
Chris Lattner
5b3e46bd6b
lets go all meta and define new X86 type wrappers that declare the associated
...
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)
llvm-svn: 115727
2010-10-06 00:45:24 +00:00
Chris Lattner
e979874e3f
introduce a new BinOpRM class and use it to factor AND*rm. This points out
...
that I need a heavier handed approach to get ultimate factorization.
llvm-svn: 115726
2010-10-06 00:30:49 +00:00
Chris Lattner
84846b71af
remove the !nameconcat tblgen feature. It "shorthand" and only used in 4 places
...
where !cast is just as short.
llvm-svn: 115722
2010-10-06 00:19:21 +00:00
Chris Lattner
12274b9845
allow !strconcat to take more than two operands to eliminate
...
!strconcat(!strconcat(!strconcat(!strconcat
Simplify some x86 td files to use it.
llvm-svn: 115719
2010-10-05 23:58:18 +00:00
Chris Lattner
dd8227d488
associate the instruction suffix letter with the integer gpr
...
register class, and use this to simplify use of BinOpRR.
llvm-svn: 115716
2010-10-05 23:43:04 +00:00
Chris Lattner
dd4c597e38
introduce a new BinOpRR class, and convert 4 and instructions to use it.
...
llvm-svn: 115715
2010-10-05 23:32:05 +00:00
Chris Lattner
ef2e024af8
Move cmov pseudo instructions to InstrCompiler,
...
convert all the rest of the cmovs to the multiclass,
with good results:
X86InstrCMovSetCC.td | 598 +--------------------------------------------------
X86InstrCompiler.td | 61 +++++
2 files changed, 77 insertions(+), 582 deletions(-)
llvm-svn: 115707
2010-10-05 23:09:10 +00:00
Chris Lattner
195a9c3877
Use #NAME# to have the CMOV multiclass define things with the same names as before
...
(e.g. CMOVBE16rr instead of CMOVBErr16).
llvm-svn: 115705
2010-10-05 23:00:14 +00:00
Chris Lattner
3357066875
enhance tblgen to support anonymous defm's, use this to
...
simplify the X86 CMOVmr's.
llvm-svn: 115702
2010-10-05 22:51:56 +00:00
Chris Lattner
b2ac22f0a4
convert cmov mr patterns to use a multipattern. Death to redundancy
...
and verbosity
llvm-svn: 115701
2010-10-05 22:42:54 +00:00
Chris Lattner
c3c03dfeff
switch CMOVBE to the multipattern:
...
21 insertions(+), 53 deletions(-)
Moar change coming before I switch the rest.
llvm-svn: 115697
2010-10-05 22:23:58 +00:00
Chris Lattner
5673933e30
fix a bug I introduced in r115669, which ended up with MOV64mr_TC
...
not getting marked as mayStore. This fixes llvm-gcc bootstrap.
llvm-svn: 115693
2010-10-05 22:16:48 +00:00
Chris Lattner
a5c35bed7b
add a multiclass for cmov's, but don't start using it yet.
...
llvm-svn: 115692
2010-10-05 22:01:02 +00:00
Chris Lattner
7065387c35
use a multipattern to define setcc instructions:
...
X86InstrCMovSetCC.td | 200 ++++++---------------------------------------------
1 file changed, 27 insertions(+), 173 deletions(-)
llvm-svn: 115689
2010-10-05 21:34:29 +00:00
Chris Lattner
fa6f058b70
move SETB pseudos into the same place in InstrCompiler.td
...
llvm-svn: 115686
2010-10-05 21:18:04 +00:00
Chris Lattner
ca34143ddd
Replace a gross hack (the MOV64ri_alt instruction) with a slightly less
...
gross hack (having the asmmatcher handle the alias).
llvm-svn: 115685
2010-10-05 21:09:45 +00:00
Chris Lattner
5d7d5a81eb
distribute the rest of the contents of X86Instr64bit.td out to
...
the right places. X86Instr64bit.td now dies, long live x86-64!
llvm-svn: 115669
2010-10-05 20:49:15 +00:00
Chris Lattner
c06e348ff8
move the rest of the simple 64-bit arithmetic into InstrArithmetic.td
...
llvm-svn: 115663
2010-10-05 20:35:37 +00:00
Chris Lattner
80ffcbd80a
continue moving 64-bit stuff into X86InstrArithmetic.td
...
llvm-svn: 115660
2010-10-05 20:23:31 +00:00
Chris Lattner
aae0403342
move 64-bit add and adc to InstrArithmetic.
...
llvm-svn: 115632
2010-10-05 16:59:08 +00:00
Chris Lattner
f5f0742885
rewrote two addr constraints so that they are only set, not set and then nestedly cleared.
...
llvm-svn: 115631
2010-10-05 16:52:25 +00:00
Chris Lattner
cdf60fcc21
split the 32-bit integer arithmetic instructions out to their own file.
...
llvm-svn: 115627
2010-10-05 16:39:12 +00:00
Chris Lattner
4cf3aff9c1
integrate the 64-bit shifts into X86InstrShiftRotate.td. Enough for tonight.
...
llvm-svn: 115608
2010-10-05 07:13:35 +00:00
Chris Lattner
3d1c1ff4c2
move 32-bit shift and rotates out to their own file.
...
llvm-svn: 115607
2010-10-05 07:00:12 +00:00
Chris Lattner
40954218dd
add new file
...
llvm-svn: 115606
2010-10-05 06:52:35 +00:00
Chris Lattner
1c0cbe9571
move sign and zero extensions out to their own file.
...
llvm-svn: 115605
2010-10-05 06:52:26 +00:00
Chris Lattner
12a0f5c3bd
move some instructions from Instr64Bit -> InstrInfo.
...
bswap32 doesn't read eflags.
llvm-svn: 115604
2010-10-05 06:47:35 +00:00
Chris Lattner
9317bf2ed5
move CMOV_FR32 and friends to InstrCompiler, since they are
...
pseudo instructions.
Move POPCNT to InstrSSE since they are SSE4 instructions.
llvm-svn: 115603
2010-10-05 06:41:40 +00:00
Chris Lattner
d96f3fe646
move various pattern matching support goop out of X86Instr64Bit, to live
...
with the 32-bit stuff.
llvm-svn: 115602
2010-10-05 06:37:31 +00:00
Chris Lattner
7451cc0f59
split conditional moves and setcc's out to their own file.
...
llvm-svn: 115601
2010-10-05 06:33:16 +00:00
Chris Lattner
7114e187e1
move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bit together.
...
llvm-svn: 115600
2010-10-05 06:27:48 +00:00
Chris Lattner
e63d763713
move the atomic pseudo instructions out to X86InstrCompiler.td
...
llvm-svn: 115599
2010-10-05 06:22:35 +00:00
Chris Lattner
a2e5444bb4
move more pseudo instructions out to X86InstrCompiler.td
...
llvm-svn: 115598
2010-10-05 06:10:16 +00:00
Chris Lattner
383d15c9d8
move VMX instructions out to their own file.
...
llvm-svn: 115597
2010-10-05 06:06:53 +00:00
Chris Lattner
5f59acddbc
continue moving stuff out to X86InstrSystem.td. Move
...
control flow stuff out to X86InstrControl.td. Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td
llvm-svn: 115596
2010-10-05 06:04:14 +00:00
Chris Lattner
db65ba5acf
refactor .td files a bit, moving system instructions out to X86InstrSystem.td
...
llvm-svn: 115591
2010-10-05 05:32:15 +00:00
Bill Wendling
b94ade249a
The pshufw instruction came about in MMX2 when SSE was introduced. Don't place
...
it in with the SSSE3 instructions.
Steward! Could you place this chair by the aft sun deck? I'm trying to get away
from the Astors. They are such boors!
llvm-svn: 115552
2010-10-04 20:24:01 +00:00
Anton Korobeynikov
f1acea8615
va_args support for Win64.
...
Patch by Cameron!
llvm-svn: 115480
2010-10-03 22:52:07 +00:00
Anton Korobeynikov
31b3b2ca41
Properly emit stack probe on win64 (for non-mingw targets).
...
Based on the patch by Cameron Esfahani!
llvm-svn: 115479
2010-10-03 22:02:38 +00:00
Eli Friedman
35432e5685
Add 3DNowA instructions.
...
llvm-svn: 115477
2010-10-03 20:23:13 +00:00
Chris Lattner
d03783eaf2
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288
...
llvm-svn: 115473
2010-10-03 19:09:13 +00:00
Rafael Espindola
49d508fd19
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do
...
so and also change X86 for consistency.
Investigating if this can be improved a bit.
llvm-svn: 115469
2010-10-03 18:59:45 +00:00
Chris Lattner
4599fd89fd
add support for the prefetch/prefetchw instructions, move femms into
...
the right file. The assembler supports all the 3dnow instructions now,
but not the "3dnowa" ones.
llvm-svn: 115468
2010-10-03 18:42:30 +00:00
Chris Lattner
6d6f84f99c
what the heck, add support for the rest of the 3dNow! binary operations.
...
llvm-svn: 115467
2010-10-03 18:24:18 +00:00
Chris Lattner
8174253484
Implement support for the bizarre 3DNow! encoding (which is unlike anything
...
else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
llvm-svn: 115466
2010-10-03 18:08:05 +00:00
Chris Lattner
3d148e7e31
stub out a header to put 3dNow! instructions into.
...
llvm-svn: 115429
2010-10-02 23:06:23 +00:00
Chris Lattner
3c29a2b776
fix a regression introduced in r115243, in which the instruction
...
backing int_x86_ssse3_pshuf_w got removed. This caused PR8280.
llvm-svn: 115422
2010-10-02 21:32:15 +00:00
Jim Grosbach
2143c9d321
Rename the AsmPrinter directory to InstPrinter for those targets that have
...
been MC-ized for assembly printing. MSP430 is mostly so, but still has the
asm printer and lowering code in the printer subdir for the moment.
llvm-svn: 115360
2010-10-01 22:39:28 +00:00
Benjamin Kramer
65131b20b4
Delete token *after* reading from it.
...
llvm-svn: 115311
2010-10-01 12:25:27 +00:00
Dale Johannesen
c14a1eda84
Massive rewrite of MMX:
...
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
llvm-svn: 115243
2010-09-30 23:57:10 +00:00
Jim Grosbach
45de3f6747
Clean up asm writer usage for x86 and msp430 to flag that the writer should
...
use MC instructions in the printInstruction() method via the tablegen flag
for it rather than a #define prior to including the autogenerated bits.
llvm-svn: 115238
2010-09-30 23:40:25 +00:00
Chris Lattner
df2f5c0a40
preemptively add the rest of the non-n fpstack instructions.
...
llvm-svn: 115168
2010-09-30 17:11:29 +00:00
Chris Lattner
8e7a4b7b57
implement support for finit, PR8258
...
llvm-svn: 115156
2010-09-30 16:42:53 +00:00
Chris Lattner
fecf3a7717
add support for fstcw, PR8259
...
llvm-svn: 115154
2010-09-30 16:39:29 +00:00
Kevin Enderby
dd3306fcb5
Adds getPointerSize() to the AsmBackend which will be needed by the final patch
...
for the dwarf .loc support to emit dwarf line number tables.
llvm-svn: 115153
2010-09-30 16:38:07 +00:00
Rafael Espindola
480ee577ad
Correctly produce R_X86_64_32 or R_X86_64_32S.
...
With this patch in
movq $foo, foo(%rip)
foo:
.long foo
We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.
llvm-svn: 115134
2010-09-30 03:11:42 +00:00
Eric Christopher
80d620fb38
Noticed by inspection when looking for other cmov bits.
...
llvm-svn: 115100
2010-09-29 23:00:29 +00:00
Nick Lewycky
a533bd63e6
Add parens to fix GCC warning:
...
lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||'
llvm-svn: 115064
2010-09-29 18:56:57 +00:00
Chris Lattner
7f466d63e0
implement rdar://8491845 - Gas supports commuted forms of non-commutable instructions.
...
llvm-svn: 115061
2010-09-29 18:39:16 +00:00
Chris Lattner
9c58de2dc4
fix rdar://8490728 - llvm-mc rejects gpr64 form of 'movmskpd'
...
llvm-svn: 115029
2010-09-29 05:05:03 +00:00
Chris Lattner
890c21a20a
add assembler support for the cvtsd2sil/cvtsd2siq mnemonics, rdar://8456382
...
llvm-svn: 115027
2010-09-29 04:55:40 +00:00
Chris Lattner
54939ddf1f
make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same
...
order as cctools for diffability.
llvm-svn: 115022
2010-09-29 03:43:43 +00:00
Chris Lattner
13354d7bbc
implement support for 32-bit address operands in 64-bit mode, which
...
are defined to emit the 0x67 prefix byte. rdar://8482675
llvm-svn: 115021
2010-09-29 03:33:25 +00:00
Chris Lattner
c14d59589c
add basic avx support to the disassembler, also teach it about ssmem/sdmem
...
operands.
With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up. This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'
llvm-svn: 115019
2010-09-29 02:57:56 +00:00
Chris Lattner
f90296b045
add asmparser support for cvttpd2dq by removing some Int_ prefixes.
...
Clean up cvttps2dq by removing some redundant implementations of the
same instruction. rdar://8456382
llvm-svn: 115018
2010-09-29 02:36:32 +00:00
Chris Lattner
e5c5c8dc1f
implement rdar://8456382 - cvtsd2si support, by removing some Int_ prefixes.
...
llvm-svn: 115017
2010-09-29 02:24:57 +00:00
Chris Lattner
cbecb9a4d3
implement rdar://8456378 and PR7557 - support for the fstsw,
...
an instruction that requires a WHOLE NEW wonderful kind of alias.
llvm-svn: 115015
2010-09-29 01:50:45 +00:00
Chris Lattner
9b9a847b8c
change the protocol TargetAsmPArser::MatchInstruction method to take an
...
MCStreamer to emit into instead of an MCInst to fill in. This allows the
matcher extra flexibility and is more convenient.
llvm-svn: 115014
2010-09-29 01:42:58 +00:00
Dale Johannesen
119f97dcc3
MMX parameters aren't handled here yet.
...
llvm-svn: 114844
2010-09-27 17:29:47 +00:00
Chris Lattner
b335259960
yet more aliases.
...
llvm-svn: 114822
2010-09-27 07:24:57 +00:00
Chris Lattner
be06321564
add a couple more aliases, rdar://8456378
...
llvm-svn: 114821
2010-09-27 07:21:41 +00:00
Chris Lattner
26c94e7200
fix rdar://8470918 - llvm-mc can't assemble smovl
...
llvm-svn: 114819
2010-09-27 07:11:53 +00:00
Chris Lattner
5cadf79b60
Fix rdar://8468087 - llvm-mc commutes fmul (and friend) operands.
...
My previous fix for rdar://8456371 should only apply to fmulp/faddp,
not to fmul/fadd. Instruction set orthogonality is overrated or
something.
llvm-svn: 114818
2010-09-27 07:08:21 +00:00
Chris Lattner
2e3f9253fd
improve indentation
...
llvm-svn: 114815
2010-09-27 06:34:01 +00:00
Eric Christopher
467683e4ab
This code should never fire on non-darwin subtargets.
...
llvm-svn: 114811
2010-09-27 06:01:51 +00:00
Chris Lattner
75edc6b6e0
implement support for 'clr' alias. This is part of rdar://8416805,
...
but balrog was wanting it on irc.
llvm-svn: 114809
2010-09-27 04:23:03 +00:00
Rafael Espindola
e4c0edf697
Move ELF to HasReliableSymbolDifference=true. Also take the opportunity to put
...
symbols defined in merge sections in independent atoms.
llvm-svn: 114786
2010-09-25 05:42:19 +00:00
Dale Johannesen
d75242fa84
We can't return SSE/MMX vectors if SSE is disabled.
...
llvm-svn: 114745
2010-09-24 19:05:48 +00:00
Owen Anderson
4fc55c0e02
Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further
...
reflection, this isn't going to achieve the purpose I intended it for. Back to the drawing board!
llvm-svn: 114710
2010-09-23 23:45:25 +00:00
Owen Anderson
15c6948d29
Add isConditionalMove bits to X86 and ARM instructions.
...
llvm-svn: 114703
2010-09-23 22:57:01 +00:00
Cameron Esfahani
662193bddc
Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case.
...
llvm-svn: 114597
2010-09-22 22:35:21 +00:00
Eric Christopher
84827bd9f5
Temporarily work around new address lowering while I figure out what
...
needs to happen for darwin.
llvm-svn: 114577
2010-09-22 20:42:08 +00:00
Bob Wilson
3ff9f2d102
Attempt to fix llvm-gcc build. It was crashing when building gcov.o for an
...
ARM cross-compiler on x86, because the MMO size did not match the type size.
This fixes the MMO size and also the size of the stack object to match the
type size.
llvm-svn: 114554
2010-09-22 17:35:14 +00:00
Chris Lattner
f90b2a5a26
fix rdar://8456371 - Handle commutable instructions written backward.
...
llvm-svn: 114536
2010-09-22 06:26:39 +00:00
Chris Lattner
1864d6728d
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
...
x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly
named "callq", so this only impacted x86-32.
This fixes rdar://8456370 - llvm-mc rejects 'calll'
This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.
llvm-svn: 114534
2010-09-22 05:49:14 +00:00
Chris Lattner
1ff3935290
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"
...
Teaching the code generator about CR8-15, how to rex them up, etc.
llvm-svn: 114533
2010-09-22 05:29:50 +00:00
Chris Lattner
77d657ae6a
add the missing aliases for fp stack cmovs, rdar://8456391
...
llvm-svn: 114531
2010-09-22 04:56:20 +00:00
Chris Lattner
26d11d7501
reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.
...
llvm-svn: 114529
2010-09-22 04:39:11 +00:00
Chris Lattner
2e61516c5a
Fix rdar://8456364 - llvm-mc rejects '%CS'
...
llvm-svn: 114528
2010-09-22 04:11:10 +00:00
Chris Lattner
2d350c46e2
fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp'
...
-This line, and those below, will be ignored--
M test/MC/AsmParser/X86/x86_instructions.s
M lib/Target/X86/AsmParser/X86AsmParser.cpp
llvm-svn: 114527
2010-09-22 04:04:03 +00:00
Chris Lattner
f43f09693e
fix rdar://8456361 - llvm-mc rejects 'rep movsd'
...
llvm-svn: 114526
2010-09-22 03:50:32 +00:00
Chris Lattner
c81dcbec9e
convert the last 4 X86ISD nodes that should have memoperands to have them.
...
llvm-svn: 114523
2010-09-22 01:28:21 +00:00
Chris Lattner
29754fc406
give X86ISD::FNSTCW16m a memoperand, since it touches memory. It only
...
can access the stack due to how it is generated though.
llvm-svn: 114522
2010-09-22 01:11:26 +00:00
Chris Lattner
fee1ac61bd
give FP_TO_INT16_IN_MEM and friends a memoperand. They are only
...
used with stack slots, but hey, lets be safe.
llvm-svn: 114521
2010-09-22 01:05:16 +00:00
Chris Lattner
e52da86fab
give VZEXT_LOAD a memory operand, it now works with segment registers.
...
llvm-svn: 114515
2010-09-22 00:34:38 +00:00
Chris Lattner
706b9206da
revert r114386 now that address modes work correctly, we get a nice
...
call through gs-relative memory now.
llvm-svn: 114510
2010-09-22 00:11:31 +00:00
Chris Lattner
f9861312cb
give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257
...
llvm-svn: 114508
2010-09-21 23:59:42 +00:00
Chris Lattner
b227ae4ddb
reimplement support for GS and FS relative address space matching
...
by having X86DAGToDAGISel::SelectAddr get passed in the parent node
of the operand match (the load/store/atomic op) and having it get
the address space from that, instead of having special FS/GS addr
mode operations that require duplicating the entire instruction set
to support.
This makes FS and GS relative accesses *far* more predictable and
work much better. It also simplifies the X86 backend a bit, more
to come.
There is still a pending issue with nodes like ISD::PREFETCH and
X86ISD::FLD, which really should be MemSDNode's but aren't.
llvm-svn: 114491
2010-09-21 22:07:31 +00:00
Owen Anderson
f6dd8e7f5c
Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using
...
the predicate to discover the number of sign bits. Enhance X86's target lowering to provide
a useful response to this query.
llvm-svn: 114473
2010-09-21 20:42:50 +00:00
Chris Lattner
55043ef46a
fix a long standing wart: all the ComplexPattern's were being
...
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
llvm-svn: 114471
2010-09-21 20:31:19 +00:00
Chris Lattner
c153d48869
even though I'm about to rip it out, simplify the address mode stuff
...
llvm-svn: 114468
2010-09-21 19:41:58 +00:00
Chris Lattner
3dde58c15a
convert a couple more places to use the new getStore()
...
llvm-svn: 114463
2010-09-21 18:51:21 +00:00
Owen Anderson
97a8fdc19c
When adding the carry bit to another value on X86, exploit the fact that the carry-materialization
...
(sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.
This fixes <rdar://problem/8449754>.
llvm-svn: 114460
2010-09-21 18:41:19 +00:00
Chris Lattner
5f584efd31
eliminate some uses of the getStore overload.
...
llvm-svn: 114453
2010-09-21 17:50:43 +00:00
Chris Lattner
cdfd993df0
propagate MachinePointerInfo through various uses of the old
...
SelectionDAG::getExtLoad overload, and eliminate it.
llvm-svn: 114446
2010-09-21 17:04:51 +00:00
Chris Lattner
4320dda4fb
convert the targets off the non-MachinePointerInfo of getLoad.
...
llvm-svn: 114410
2010-09-21 06:44:06 +00:00
Chris Lattner
112cf9bc89
it's more elegant to put the "getConstantPool" and
...
"getFixedStack" on the MachinePointerInfo class. While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.
llvm-svn: 114406
2010-09-21 06:22:23 +00:00
Chris Lattner
810a630851
update the X86 backend to use the MachinePointerInfo version of one
...
of the getLoad methods. This fixes at least one bug where an incorrect
svoffset is passed in (a potential combiner-aa miscompile).
llvm-svn: 114404
2010-09-21 06:02:19 +00:00
Chris Lattner
80d9e51351
Fix a bug where the x86 backend would lower memcpy/memset of segment relative operations
...
into non-segment-relative copies.
llvm-svn: 114402
2010-09-21 05:43:34 +00:00
Chris Lattner
f94de5bf46
reimplement memcpy/memmove/memset lowering to use MachinePointerInfo
...
instead of srcvalue/offset pairs. This corrects SV info for mem
operations whose size is > 32-bits.
llvm-svn: 114401
2010-09-21 05:40:29 +00:00
Chris Lattner
2edbad8a3d
convert targets to the new MF.getMachineMemOperand interface.
...
llvm-svn: 114391
2010-09-21 04:39:43 +00:00
Chris Lattner
ecdba24738
fix rdar://8453210, a crash handling a call through a GS relative load.
...
For now, just disable folding the load into the call.
llvm-svn: 114386
2010-09-21 03:37:00 +00:00
NAKAMURA Takumi
a4a0276d4f
X86Subtarget.h: Fix Cygwin's TD.
...
llvm-svn: 114297
2010-09-18 19:50:42 +00:00
Dan Gohman
aaed2c137f
Avoid emitting a PIC base register if no PIC addresses are needed.
...
This fixes rdar://8396318.
llvm-svn: 114201
2010-09-17 20:24:24 +00:00
Chris Lattner
4bce01542c
fix rdar://8444631 - encoder crash on 'enter'
...
What a weird instruction.
llvm-svn: 114190
2010-09-17 18:02:29 +00:00
Chris Lattner
73fc5e794d
fix rdar://8438816 - unrecognized 'fildq' instruction
...
llvm-svn: 114116
2010-09-16 20:46:38 +00:00
Chris Lattner
fff8e3495b
lcall and ljmp always default to lcalll and ljmpl. This finally
...
wraps up r8418316
llvm-svn: 113949
2010-09-15 05:30:20 +00:00
Chris Lattner
726aae87ee
apparently jmpl $1,$2 is an alias for ljmpl, similiarly
...
for call. Add this.
llvm-svn: 113948
2010-09-15 05:25:21 +00:00
Chris Lattner
5b8a3129a5
Disambiguate lcall/ljmp to the 32-bit version. This happens
...
even in 64-bit mode apparently.
llvm-svn: 113945
2010-09-15 05:14:54 +00:00
Chris Lattner
e542e3e2ad
fix the encoding of sldt GR16 to have the 0x66 prefix, and
...
add sldt GR32, which isn't documented in the intel manual
but which gas accepts. Part of rdar://8418316
llvm-svn: 113938
2010-09-15 04:45:10 +00:00
Chris Lattner
c4a2e044f3
implement aliases for shld/shrd, part of rdar://8418316
...
llvm-svn: 113937
2010-09-15 04:37:18 +00:00
Chris Lattner
ad73a2623c
fix rdar://8431880 - rcl/rcr with no shift amount not recognized
...
llvm-svn: 113936
2010-09-15 04:33:27 +00:00
Chris Lattner
c48bd41698
add various broken forms of fnstsw. I didn't add the %rax
...
version because it adds a prefix and makes even less sense
than the other broken forms. This wraps up rdar://8431422
llvm-svn: 113932
2010-09-15 04:15:16 +00:00
Chris Lattner
b6167a8674
add some aliases for f[u]comi, part of rdar://8431422
...
llvm-svn: 113930
2010-09-15 04:08:38 +00:00
Chris Lattner
c9f1a5cd94
add a bunch of aliases for fp operations with no operand,
...
rdar://8431422
llvm-svn: 113929
2010-09-15 04:04:33 +00:00
Chris Lattner
a9a15c74b1
Diagnose invalid instructions like "incl" with "too few operands for instruction"
...
instead of crashing. This fixes:
rdar://8431815 - crash when invalid operand is one that isn't present
llvm-svn: 113921
2010-09-15 03:50:11 +00:00
Jim Grosbach
050a857211
trailing whitespace
...
llvm-svn: 113915
2010-09-15 01:01:45 +00:00
Chris Lattner
cd4eadce11
add a terrible hack to allow out with dx is parens, a gas bug.
...
This fixes PR8114
llvm-svn: 113894
2010-09-14 23:34:29 +00:00
Michael J. Spencer
90f807fda5
Revert "CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally."
...
This reverts commit r113632
Conflicts:
cmake/modules/AddLLVM.cmake
llvm-svn: 113819
2010-09-13 23:59:48 +00:00
Dale Johannesen
eb807a15a3
Fix typos. 128-bit PSHUFB takes 128-bit memory op.
...
v8i16 is not an MMX type; put it where it belongs.
llvm-svn: 113785
2010-09-13 21:15:43 +00:00
John Thompson
ae3a86d6de
Added skeleton for inline asm multiple alternative constraint support.
...
llvm-svn: 113766
2010-09-13 18:15:37 +00:00
Chris Lattner
46844daf49
add a missed cmov alias, part of rdar://8416805
...
llvm-svn: 113693
2010-09-11 17:08:22 +00:00
Chris Lattner
57c170e15b
add support for all the setCC aliases. Part of rdar://8416805
...
llvm-svn: 113692
2010-09-11 17:06:05 +00:00
Chris Lattner
7cb9d276e0
add support for pushfd/popfd which are aliases for pushfl/popfl.
...
This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors
llvm-svn: 113690
2010-09-11 16:39:16 +00:00
Chris Lattner
1fd69dd039
implement rdar://8407928 - support for in/out with a missing "a" register.
...
llvm-svn: 113689
2010-09-11 16:32:12 +00:00
Chris Lattner
ffe1efe7ef
fix the asmparser so that the target is responsible for skipping to
...
the end of the line on a parser error, allowing skipping to happen
for syntactic errors but not for semantic errors. Before we would
miss emitting a diagnostic about the second line, because we skipped
it due to the semantic error on the first line:
foo %eax
bar %al
This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors
llvm-svn: 113688
2010-09-11 16:18:25 +00:00
Michael J. Spencer
98ad3f2ea7
CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally.
...
llvm-svn: 113632
2010-09-10 21:14:25 +00:00
Bill Wendling
d7f4e62200
Reapply r113585. The msvc machine is mercurial.
...
llvm-svn: 113610
2010-09-10 20:20:28 +00:00
Bill Wendling
ddfcd9b819
r113585 was causing clang-i686-xp-msvc9 to fail in mysterious ways that I can't
...
understand (the log file was no help).
llvm-svn: 113605
2010-09-10 19:20:47 +00:00
Bill Wendling
bbdc6c49bf
Mark the sse_load_f32 and sse_load_f64 load patterns as having memoperands so
...
that the memoperands are properly set after DAG building and general mucking
about.
llvm-svn: 113585
2010-09-10 10:34:22 +00:00
Bruno Cardoso Lopes
49efee5c95
Add one more pattern to fallback movddup
...
llvm-svn: 113522
2010-09-09 18:48:34 +00:00
Roman Divacky
536c4ab8bd
Make ELF OS ABI dependent on the OS from target triple.
...
llvm-svn: 113508
2010-09-09 17:57:50 +00:00
Dale Johannesen
de53df20d6
Move remaining MMX instructions from SSE to MMX.
...
llvm-svn: 113501
2010-09-09 17:13:07 +00:00
Dale Johannesen
7469923117
Move most MMX instructions (defined as anything that
...
uses MMX, even if it also uses other things) from InstrSSE
into InstrMMX. No (intended) functional change.
llvm-svn: 113462
2010-09-09 01:02:39 +00:00
Chris Lattner
43c86a062c
fix rdar://8407548, I missed the commuted form of xchg/test without a suffix.
...
llvm-svn: 113427
2010-09-08 22:27:05 +00:00
Chris Lattner
7e0932fb43
fix wonky formatting.
...
llvm-svn: 113426
2010-09-08 22:22:10 +00:00
Chris Lattner
5234733554
fix bugs in push/pop segment support, rdar://8407242
...
llvm-svn: 113422
2010-09-08 22:13:08 +00:00
Dale Johannesen
165cfe63b4
Add intrinsic-based patterns for MMX PINSRW and PEXTRW.
...
llvm-svn: 113420
2010-09-08 22:08:40 +00:00
Dale Johannesen
3716bed25c
Check in forgotten file. Should fix build.
...
llvm-svn: 113409
2010-09-08 21:09:48 +00:00
Dale Johannesen
92311463f4
Slight cleanup, use only one form of MMXI_binop_rm_int.
...
llvm-svn: 113406
2010-09-08 20:54:00 +00:00
Dale Johannesen
464762ad1a
Add intrinsic forms of mmx<->sse conversions. Notes:
...
Omission of memory form of PI2PD is intentional; this
does not use an MMX register and does not put the chip
into MMX mode (PI2PS, oddly enough, does).
Operands of PI2PS follow the gcc builtin, not Intel.
llvm-svn: 113388
2010-09-08 19:15:38 +00:00
Bruno Cardoso Lopes
a74c787dc8
Minor change. Fix comments and remove unused and redundant code
...
llvm-svn: 113378
2010-09-08 18:12:31 +00:00
Bruno Cardoso Lopes
892c337123
x86 vector shuffle lowering now relies only on target specific
...
nodes to emit shuffles and don't do isel mask matching anymore.
- Add the selection of the remaining shuffle opcode (movddup)
- Introduce two new functions to "recognize" where we may get
potential folds and add several comments to them explaining why
they are not yet in the desidered shape.
- Add more patterns to fallback the case where we select
a specific shuffle opcode as if it could fold a load, but it
can't, so remap to a valid instruction.
- Add a couple of FIXMEs to address in the following days once
there's a good solution to the current folding problem.
llvm-svn: 113369
2010-09-08 17:43:25 +00:00
Chris Lattner
4e8c89174f
add support for the commuted form of the test instruction, rdar://8018260.
...
llvm-svn: 113352
2010-09-08 05:51:12 +00:00
Chris Lattner
752daa9624
implement proper support for sysret{,l,q}, rdar://8403907
...
llvm-svn: 113350
2010-09-08 05:45:34 +00:00
Chris Lattner
40f9f0fdba
implement the iret suite of instructions properly,
...
fixing rdar://8403974
llvm-svn: 113349
2010-09-08 05:38:31 +00:00
Chris Lattner
05818145f8
add support for instruction prefixes on the same line as the instruction,
...
implementing rdar://8033482 and PR7254.
llvm-svn: 113348
2010-09-08 05:17:37 +00:00
Chris Lattner
0e0f9094e9
change the MC "ParseInstruction" interface to make it the
...
implementation's job to check for and lex the EndOfStatement
marker.
llvm-svn: 113347
2010-09-08 05:10:46 +00:00
Chris Lattner
7435beb421
gas accepts xchg <mem>, <reg> as a synonym for xchg <reg>, <mem>.
...
Add this to the mc assembler, fixing PR8061
llvm-svn: 113346
2010-09-08 04:53:27 +00:00
Chris Lattner
8f621d5039
fix the encoding of the "jump on *cx" family of instructions,
...
rdar://8061602
llvm-svn: 113343
2010-09-08 04:30:51 +00:00
Bruno Cardoso Lopes
a4ca8c3ac5
Factor out some x86 vector shuffle rewriting and add comments about the direction the shuffle lowering is heading to
...
llvm-svn: 113286
2010-09-07 21:03:14 +00:00
Bruno Cardoso Lopes
e33983dba9
Move code around to prepare for moving some of the logic together to another function
...
llvm-svn: 113267
2010-09-07 20:20:27 +00:00
Bill Wendling
9bb7ac566f
Add an MVT::x86mmx type. It will take the place of all current MMX vector types.
...
llvm-svn: 113261
2010-09-07 20:03:56 +00:00
Evan Cheng
5a058ed2a0
Remove a dead comment.
...
llvm-svn: 113259
2010-09-07 20:01:10 +00:00
Bruno Cardoso Lopes
21e1fc67c3
decouple MMX check from regular splat checks. Some refactoring is coming, and MMX should be left alone to be easily removed after moving to intrinsics
...
llvm-svn: 113247
2010-09-07 18:41:45 +00:00
Bruno Cardoso Lopes
dcc8690051
Remove now useless check, because the code can be matched below, no need to leave it for isel
...
llvm-svn: 113242
2010-09-07 18:29:03 +00:00
Bruno Cardoso Lopes
e6f7e4684d
Minor change. Since the checks are equivalent, use isMMX
...
llvm-svn: 113239
2010-09-07 18:24:00 +00:00
Dale Johannesen
8354cab2de
Add patterns for MMX that use the new intrinsics.
...
Enable palignr intrinsic.
These may need adjustment for a new VT in due course.
llvm-svn: 113233
2010-09-07 18:10:56 +00:00
Bruno Cardoso Lopes
92bb02f722
Remove unused target specific node
...
llvm-svn: 113224
2010-09-07 17:38:55 +00:00
Benjamin Kramer
32f7af702a
Don't leak the old operand when transforming "sldt" into "sldtw".
...
llvm-svn: 113200
2010-09-07 14:40:58 +00:00
Chris Lattner
fd65cfd3eb
add missing cmov aliases, this resolves rdar://8208499
...
llvm-svn: 113189
2010-09-07 00:05:45 +00:00
Chris Lattner
927dc7a5d2
remove duplicated entry
...
llvm-svn: 113188
2010-09-06 23:57:24 +00:00
Chris Lattner
5a696fb3ca
"sldt <mem>" is ambiguous in 64-bit mode, but should
...
always be disambiguated as sldtw. sldtw and sldtq with
a mem operands have the same effect, but sldtw is more
compact. Force it to sldtw, resolving rdar://8017530
llvm-svn: 113186
2010-09-06 23:51:44 +00:00
Chris Lattner
3377802111
fix rdar://8017621 - llvm-mc can't guess encoding for "push $(1000)"
...
llvm-svn: 113184
2010-09-06 23:40:56 +00:00
Chris Lattner
6ecbbff857
fix the operand constraints of the immediate form of in/out,
...
allowing unsigned 8-bit operands. This fixes rdar://8208481
llvm-svn: 113182
2010-09-06 23:29:05 +00:00
Chris Lattner
6bfa0d9988
in the case where an instruction only has one implementation
...
of a mneumonic, report operand errors with better location
info. For example, we now report:
t.s:6:14: error: invalid operand for instruction
cwtl $1
^
but we fail for common cases like:
t.s:11:4: error: invalid operand for instruction
addl $1, $1
^
because we don't know if this is supposed to be the reg/imm or imm/reg
form.
llvm-svn: 113178
2010-09-06 22:11:18 +00:00
Chris Lattner
bb5e19cb63
Now that we know if we had a total fail on the instruction mnemonic,
...
give a more detailed error. Before:
t.s:11:4: error: unrecognized instruction
addl $1, $1
^
t.s:12:4: error: unrecognized instruction
f2efqefa $1
^
After:
t.s:11:4: error: invalid operand for instruction
addl $1, $1
^
t.s:12:4: error: invalid instruction mnemonic 'f2efqefa'
f2efqefa $1
^
This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands"
llvm-svn: 113176
2010-09-06 21:54:15 +00:00
Chris Lattner
87234fd589
simplify the hacks around jrcxz.
...
llvm-svn: 113167
2010-09-06 20:10:12 +00:00
Chris Lattner
68f7c5b750
have tblgen detect when an instruction would have matched, but
...
failed because a subtarget feature was not enabled. Use this to
remove a bunch of hacks from the X86AsmParser for rejecting things
like popfl in 64-bit mode. Previously these hacks weren't needed,
but were important to get a message better than "invalid instruction"
when used in the wrong mode.
This also fixes bugs where pushal would not be rejected correctly in
32-bit mode (just pusha).
llvm-svn: 113166
2010-09-06 20:08:02 +00:00
Chris Lattner
22bb9cb511
change MatchInstructionImpl to return an enum instead of bool.
...
llvm-svn: 113165
2010-09-06 19:22:17 +00:00
Chris Lattner
45a204be76
have AsmMatcherEmitter.cpp produce the hunk of code that gets included
...
into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.
llvm-svn: 113163
2010-09-06 19:11:01 +00:00
Roman Divacky
f760edb301
Redefine LOOP* instructions from I to Ii8PCRel as they take an i8 argument.
...
llvm-svn: 113158
2010-09-06 18:43:14 +00:00
Chris Lattner
3bd0996c77
random cleanups
...
llvm-svn: 113157
2010-09-06 18:32:06 +00:00
Chris Lattner
908d8e9de2
update this.
...
llvm-svn: 113116
2010-09-05 20:22:09 +00:00
Chris Lattner
684ae57b8e
implement rdar://6653118 - fastisel should fold loads where possible.
...
Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:
int foo(int x, int y, int z) {
return x+y+z;
}
used to compile into:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
movl 4(%rsp), %esi
addl %edx, %esi
movl (%rsp), %edx
addl %esi, %edx
movl %edx, %eax
addq $12, %rsp
ret
Now we produce:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
addl 4(%rsp), %edx ## Folded load
addl (%rsp), %edx ## Folded load
movl %edx, %eax
addq $12, %rsp
ret
Fewer instructions and less register use = faster compiles.
llvm-svn: 113102
2010-09-05 02:18:34 +00:00
Chris Lattner
8df3ffd7ac
zap dead code.
...
llvm-svn: 113073
2010-09-04 18:12:00 +00:00
Bruno Cardoso Lopes
8d76bbe31c
Remove the last bit of isShuffleMaskLegal checks and improve the comment regarding mmx shuffles
...
llvm-svn: 113059
2010-09-04 02:58:56 +00:00
Bruno Cardoso Lopes
fccf00be8c
make explicit that we not handle several mmx shuffles
...
llvm-svn: 113058
2010-09-04 02:50:13 +00:00
Bruno Cardoso Lopes
0562140ec3
Emit target specific nodes to handle palignr. Do not touch it for MMX versions yet.
...
llvm-svn: 113056
2010-09-04 02:36:07 +00:00
Bruno Cardoso Lopes
73651844b2
Emit target specific nodes to handle splats starting at zero indicies
...
llvm-svn: 113055
2010-09-04 02:02:14 +00:00
Bruno Cardoso Lopes
483bb7eed2
Emit target specific nodes for isPSHUFHWMask and isPSHUFLWMask
...
llvm-svn: 113050
2010-09-04 01:36:45 +00:00
Bruno Cardoso Lopes
742030b3db
Emit target specific nodes for isSHUFPMask
...
llvm-svn: 113048
2010-09-04 01:22:57 +00:00
Bruno Cardoso Lopes
3e3169873e
Previous isMOVLMask matching already emits targets nodes, remove check
...
llvm-svn: 113047
2010-09-04 00:50:08 +00:00
Bruno Cardoso Lopes
b867456bfc
One more check from the original isShuffleMaskLegal goes away
...
llvm-svn: 113045
2010-09-04 00:46:16 +00:00
Bruno Cardoso Lopes
3081ae493b
Remove a duplicated but useless check that i've inserted in the previous commit.
...
llvm-svn: 113044
2010-09-04 00:43:12 +00:00
Bruno Cardoso Lopes
22775e6e65
Refactor some code and remove the extra checks for unpckl_undef and unpckh_undef
...
llvm-svn: 113043
2010-09-04 00:39:43 +00:00
Bruno Cardoso Lopes
5d71537f4a
Remove check for unpckh mask
...
llvm-svn: 113035
2010-09-03 23:32:47 +00:00
Bruno Cardoso Lopes
d9d2ed558e
Remove check for unpckl mask
...
llvm-svn: 113034
2010-09-03 23:31:50 +00:00
Bruno Cardoso Lopes
ecfa52b251
Inline isShuffleMaskLegal into LowerVECTOR_SHUFFLE, so we can start
...
checking each standalone condition and decide whether emit target
specific nodes or remove the condition if it's already matched before.
llvm-svn: 113031
2010-09-03 23:24:06 +00:00
Bruno Cardoso Lopes
01dc6f1195
Reapply considered harmfull part of rr112934 and r112942.
...
"Use target specific nodes instead of relying in unpckl and
unpckh pattern fragments during isel time. Also place a
depth limit in getShuffleScalarElt.
llvm-svn: 113020
2010-09-03 22:09:41 +00:00
Dale Johannesen
2f4f8f5705
Remove the rest of the nonexistent 64-bit AVX instructions.
...
Bruno, please review.
llvm-svn: 113014
2010-09-03 21:23:00 +00:00
Bruno Cardoso Lopes
b8ce8b7e9f
Reapply last harmless part of r112934, the pattern fragment to match X86Unpcklpd
...
llvm-svn: 113009
2010-09-03 20:44:26 +00:00
Bruno Cardoso Lopes
4753ce5e2c
Reintroduce a simple function refactoring done in r112934, also without any functionality changes
...
llvm-svn: 113008
2010-09-03 20:20:02 +00:00
Bruno Cardoso Lopes
3c43bc3214
Reapply piecies of r112942 and r112934 which don't do
...
functional changes
llvm-svn: 113007
2010-09-03 20:10:35 +00:00
Bruno Cardoso Lopes
9635a81d34
Reapply Fix comment
...
llvm-svn: 113006
2010-09-03 19:55:05 +00:00
Daniel Dunbar
26e0e964ab
Revert r112934, "- Use specific nodes to match unpckl masks.", which introduced
...
some infinite loop and select failures.
- Apologies for eager reverting, but its branch day.
llvm-svn: 113000
2010-09-03 19:38:11 +00:00
Daniel Dunbar
c8af4f3a0a
Revert r112938 "Fix comment", which depends on r112934, which introduced some
...
infinite loop and select failures.
llvm-svn: 112999
2010-09-03 19:38:08 +00:00
Daniel Dunbar
4ece67890b
Revert r112942, "Use punpckh and unpckh family of nodes instead of using unpckh
...
mask pattern fragment", which depends on r112934, which introduced some infinite
loop and select failures.
llvm-svn: 112998
2010-09-03 19:38:05 +00:00
Bruno Cardoso Lopes
f91bd70e9a
AVX doesn't support mm operations neither its instrinsics.
...
The AVX versions of PALIGN and PABS* should only exist for
128-bit. Remove the unnecessary stuff.
llvm-svn: 112944
2010-09-03 02:08:45 +00:00
Bruno Cardoso Lopes
70f376e9da
Use punpckh and unpckh family of nodes instead of using unpckh mask pattern fragment
...
llvm-svn: 112942
2010-09-03 01:39:08 +00:00
Bruno Cardoso Lopes
b107a092a5
Fix comment
...
llvm-svn: 112938
2010-09-03 01:28:51 +00:00
Bruno Cardoso Lopes
e1ad6555a8
- Use specific nodes to match unpckl masks.
...
- Teach getShuffleScalarElt how to handle more target
specific nodes, so the DAGCombine can make use of it.
- Add another hack to avoid the node update problem
during legalization. More description on the comments
llvm-svn: 112934
2010-09-03 01:24:00 +00:00
Jakob Stoklund Olesen
b7bd26db67
Don't call Predicate_* from X86 target.
...
llvm-svn: 112921
2010-09-03 00:35:18 +00:00
Anton Korobeynikov
32cecc0ecc
Properly emit __chkstk call instead of __alloca on non-mingw windows targets.
...
Patch by Cameron Esfahani!
llvm-svn: 112902
2010-09-02 23:03:46 +00:00
Bruno Cardoso Lopes
9c1614674a
Move insertps mask decoding to header file
...
llvm-svn: 112896
2010-09-02 22:43:39 +00:00
Anton Korobeynikov
a65910e5ca
Revert win64 changes. They seem to be incomplete
...
llvm-svn: 112885
2010-09-02 22:31:32 +00:00
Anton Korobeynikov
339ab60a5b
Properly allocate win64 shadow reg area.
...
Patch by Jan Sjodin!
llvm-svn: 112875
2010-09-02 22:16:28 +00:00
Bruno Cardoso Lopes
c24f2a0880
Move decoding of insertps back to avoid unused warnings in x86 isel lowering, and fix movlhps/movhlps to decode 4 elements shuffles
...
llvm-svn: 112869
2010-09-02 21:51:11 +00:00
Dan Gohman
6824bfc554
Don't narrow the load and store in a load+twiddle+store sequence unless
...
there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.
This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.
llvm-svn: 112861
2010-09-02 21:18:42 +00:00
Bruno Cardoso Lopes
7132e91cdb
Move x86 specific shuffle mask decoding to its own header, it's also going to be used elsewhere. Also trim trailing whitespaces
...
llvm-svn: 112846
2010-09-02 18:40:13 +00:00
Bruno Cardoso Lopes
659f549638
Replace unpckl_undef and unpckh_undef matching with target specific opcodes
...
llvm-svn: 112806
2010-09-02 05:23:12 +00:00
Bruno Cardoso Lopes
9d4a11d4c6
Move condition out to prepare for more matching
...
llvm-svn: 112805
2010-09-02 04:20:26 +00:00
Bruno Cardoso Lopes
1b9095fff1
Remove checking for isUNPCKL_v_undef_Mask, the specific node is already emitted for it
...
llvm-svn: 112804
2010-09-02 03:57:58 +00:00
Bruno Cardoso Lopes
dcdab94661
become more strict about when it's safe to use X86ISD::MOVLPS
...
llvm-svn: 112799
2010-09-02 02:35:51 +00:00
Bruno Cardoso Lopes
b73f0cbc7a
Revert r112689, avoid those kind of checks cause they mess up with mmx
...
llvm-svn: 112760
2010-09-01 22:59:03 +00:00
Bruno Cardoso Lopes
601bf4c6d3
Using target specific nodes for shuffle nodes makes the mask
...
check more strict, breaking some cases not checked in the
testsuite, but also exposes some foldings not done before,
as this example:
movaps (%rdi), %xmm0
movaps (%rax), %xmm1
movaps %xmm0, %xmm2
movss %xmm1, %xmm2
shufps $36, %xmm2, %xmm0
now is generated as:
movaps (%rdi), %xmm0
movaps %xmm0, %xmm1
movlps (%rax), %xmm1
shufps $36, %xmm1, %xmm0
llvm-svn: 112753
2010-09-01 22:33:20 +00:00
Bruno Cardoso Lopes
9375b2f67d
Use movlps, movlpd, movss and movsd specific nodes instead of pattern matching with movlp pattern fragment
...
llvm-svn: 112694
2010-09-01 05:08:25 +00:00
Bruno Cardoso Lopes
b69568ab33
minor change, simplify some logic
...
llvm-svn: 112689
2010-09-01 00:57:08 +00:00
Bruno Cardoso Lopes
c31697f68c
Move some functions around so they can be used for some other to come function
...
llvm-svn: 112687
2010-09-01 00:51:36 +00:00
Bruno Cardoso Lopes
80613a070e
Use x86 specific MOVSLDUP node, add more patterns to match it and remove useless load nodes
...
llvm-svn: 112661
2010-08-31 22:35:05 +00:00
Bruno Cardoso Lopes
8fc83b1960
Use x86 specific MOVSHDUP node and add more patterns to match it
...
llvm-svn: 112657
2010-08-31 22:22:11 +00:00
Jakob Stoklund Olesen
7ffcddc113
Make %EFLAGS unallocatable.
...
No CCR virtual registers should exist, and %EFLAGS is used in ways that can
surprise RegAllocFast.
llvm-svn: 112650
2010-08-31 21:51:07 +00:00
Bruno Cardoso Lopes
dfa177cf81
Use MOVHLPS node instead of matching using movhlps and movhlps_undef pattern fragments
...
llvm-svn: 112644
2010-08-31 21:38:49 +00:00
Bruno Cardoso Lopes
6fbe7b9ddd
Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some useless nodes
...
llvm-svn: 112642
2010-08-31 21:15:21 +00:00
Bruno Cardoso Lopes
08d5d62dcb
Use X86ISD::MOVSS and MOVSD to represent the movl mask pattern, also fix the handling of those nodes when seeking for scalars inside vector shuffles
...
llvm-svn: 112570
2010-08-31 02:26:40 +00:00
Eli Friedman
6ccafafe61
A couple of small missed optimizations.
...
llvm-svn: 112411
2010-08-29 05:07:40 +00:00
Chris Lattner
646fee99c3
add a bunch more common shuffles to the instprinter.
...
llvm-svn: 112397
2010-08-29 03:08:08 +00:00
Chris Lattner
56bc8ba493
I have manually decoded the imm field of an insertps one too many
...
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
llvm-svn: 112387
2010-08-28 20:42:31 +00:00
Chris Lattner
8cb4abbc0e
fix the buildvector->insertp[sd] logic to not always create a redundant
...
insertp[sd] $0, which is a noop. Before:
_f32: ## @f32
pshufd $1, %xmm1, %xmm2
pshufd $1, %xmm0, %xmm3
addss %xmm2, %xmm3
addss %xmm1, %xmm0
## kill: XMM0<def> XMM0<kill> XMM0<def>
insertps $0, %xmm0, %xmm0
insertps $16, %xmm3, %xmm0
ret
after:
_f32: ## @f32
movdqa %xmm0, %xmm2
addss %xmm1, %xmm2
pshufd $1, %xmm1, %xmm1
pshufd $1, %xmm0, %xmm3
addss %xmm1, %xmm3
movdqa %xmm2, %xmm0
insertps $16, %xmm3, %xmm0
ret
The extra movs are due to a random (poor) scheduling decision.
llvm-svn: 112379
2010-08-28 17:59:08 +00:00
Chris Lattner
c3b630d64b
fix the BuildVector -> unpcklps logic to not do pointless shuffles
...
when the top elements of a vector are undefined. This happens all
the time for X86-64 ABI stuff because only the low 2 elements of
a 4 element vector are defined. For example, on:
_Complex float f32(_Complex float A, _Complex float B) {
return A+B;
}
We used to produce (with SSE2, SSE4.1+ uses insertps):
_f32: ## @f32
movdqa %xmm0, %xmm2
addss %xmm1, %xmm2
pshufd $16, %xmm2, %xmm2
pshufd $1, %xmm1, %xmm1
pshufd $1, %xmm0, %xmm0
addss %xmm1, %xmm0
pshufd $16, %xmm0, %xmm1
movdqa %xmm2, %xmm0
unpcklps %xmm1, %xmm0
ret
We now produce:
_f32: ## @f32
movdqa %xmm0, %xmm2
addss %xmm1, %xmm2
pshufd $1, %xmm1, %xmm1
pshufd $1, %xmm0, %xmm3
addss %xmm1, %xmm3
movaps %xmm2, %xmm0
unpcklps %xmm3, %xmm0
ret
This implements rdar://8368414
llvm-svn: 112378
2010-08-28 17:28:30 +00:00
Chris Lattner
7fa5fa1207
improve comments in the unpcklps generating logic, introduce
...
a new EltStride variable instead of reusing NumElems variable
for a non-obvious purpose. No functionality change.
llvm-svn: 112377
2010-08-28 17:15:43 +00:00
Bruno Cardoso Lopes
1052e6d5d9
Clean up the logic of vector shuffles -> vector shifts.
...
Also teach this logic how to handle target specific shuffles if
needed, this is necessary while searching recursively for zeroed
scalar elements in vector shuffle operands.
llvm-svn: 112348
2010-08-28 02:46:39 +00:00
Anton Korobeynikov
62a9879ef4
Properly handle passing of FP stuff to varargs function on Win64:
...
value should be copied to the corresponding shadow reg as well.
Patch by Cameron Esfahani!
llvm-svn: 112262
2010-08-27 14:43:06 +00:00
Daniel Dunbar
f642d43594
X86: Fix an encoding issue with LOCK_ADD64mr, which could lead to very hard to find miscompiles with the integrated assembler.
...
llvm-svn: 112250
2010-08-27 01:30:14 +00:00
Jim Grosbach
2b81a07dc7
Simplify eliminateFrameIndex() interface back down now that PEI doesn't need
...
to try to re-use scavenged frame index reference registers. rdar://8277890
llvm-svn: 112241
2010-08-26 23:32:16 +00:00
Bruno Cardoso Lopes
6150648a64
zap the now unused MVT::getIntVectorWithNumElements
...
llvm-svn: 112218
2010-08-26 20:53:12 +00:00
Bob Wilson
640cc8ce83
Fix comment typos.
...
llvm-svn: 112202
2010-08-26 18:08:11 +00:00
Chris Lattner
148485f707
implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1.
...
llvm-svn: 112171
2010-08-26 05:51:22 +00:00
Chris Lattner
5256226fc8
fix sse1 only codegen in x86-64 mode, which is something we
...
apparently try to support.
llvm-svn: 112168
2010-08-26 05:24:29 +00:00
Bruno Cardoso Lopes
8bb7c79c1a
Fix PR7748 without using microsoft extensions
...
llvm-svn: 112128
2010-08-26 01:02:53 +00:00
Chris Lattner
eb4c7e43cc
we should pattern match the SSE complex arithmetic ops.
...
llvm-svn: 112109
2010-08-25 23:31:42 +00:00
Bruno Cardoso Lopes
28f3261dbd
Revert this for now, PUNPCKLDQ dont operate on v4f32
...
llvm-svn: 112090
2010-08-25 21:26:37 +00:00
Daniel Dunbar
1a881a3eca
X86: Fix misencode of RI64mi8. This fixes OpenSSL / x86_64-apple-darwin10 / clang -O3.
...
llvm-svn: 112089
2010-08-25 21:11:02 +00:00
Benjamin Kramer
4eb0e8bb2c
Remove dead recursive function. Yay for clang -Wunused-function.
...
llvm-svn: 112060
2010-08-25 17:27:58 +00:00
Anton Korobeynikov
1544f79e36
Fix nasty mingw32 bug, which e.g. prevented llvm-gcc bootstrap there.
...
Mark _alloca call as clobberring EFLAGS, otherwise some DCE might remove
other flags-clobberring stuff (e.g. cmp instructions) occuring after
_alloca call.
llvm-svn: 112034
2010-08-25 07:50:11 +00:00
Bruno Cardoso Lopes
af72dd7362
PUNPCKLDQ should also be used for v4f32
...
llvm-svn: 112020
2010-08-25 02:55:40 +00:00
Bruno Cardoso Lopes
33aa4f7d1c
teach lowering to get target specific nodes for pshufd, emulating the same isel behavior for now, so we can pass all vector shuffle tests
...
llvm-svn: 112017
2010-08-25 02:35:37 +00:00
Daniel Dunbar
b96b0c40d3
MC/X86: Tweak imul recognition, previous hack only applies for the imul form
...
taking immediates.
llvm-svn: 111950
2010-08-24 19:37:56 +00:00
Daniel Dunbar
3b74f75d13
MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends.
...
llvm-svn: 111947
2010-08-24 19:24:18 +00:00
Daniel Dunbar
75e77b0063
MC/X86: Warn on scale factors > 1 without index register, instead of erroring,
...
for 'as' compatibility.
llvm-svn: 111945
2010-08-24 19:13:38 +00:00
Dan Gohman
e400c660e4
Fix X86's isLegalAddressingMode to recognize that static addresses
...
need not be RIP-relative in small mode.
llvm-svn: 111917
2010-08-24 15:55:12 +00:00
Bruno Cardoso Lopes
7939025262
Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of arguments
...
llvm-svn: 111890
2010-08-24 01:16:15 +00:00