Dan Gohman
5022dd9cc9
Make tail merging handle blocks with repeated predecessors correctly, and
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remove RemoveDuplicateSuccessor, as it is no longer necessary, and because
it breaks assumptions made in
MachineBasicBlock::isOnlyReachableByFallthrough.
Convert test/CodeGen/X86/omit-label.ll to FileCheck and add a testcase
for PR4732.
test/CodeGen/Thumb2/thumb2-ifcvt2.ll sees a diff with this commit due to
it being bugpoint-reduced to the point where it doesn't matter what the
condition for the branch is.
Add some more interesting code to
test/CodeGen/X86/2009-08-06-branchfolder-crash.ll, which is the testcase
that originally motivated the RemoveDuplicateSuccessor code, to help
verify that the original problem isn't being re-broken.
llvm-svn: 79338
2009-08-18 15:18:18 +00:00
Evan Cheng
d4d2a3d0a6
Fix revsh pattern.
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llvm-svn: 79318
2009-08-18 05:43:23 +00:00
Evan Cheng
b9c8d65369
Fix tests.
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llvm-svn: 79086
2009-08-15 08:23:11 +00:00
Evan Cheng
9d351a7246
Turn on if-conversion for thumb2.
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llvm-svn: 79084
2009-08-15 07:59:10 +00:00
Evan Cheng
4e97ccc132
Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim.
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llvm-svn: 79039
2009-08-14 20:48:13 +00:00
Evan Cheng
7d8caa143b
Also shrink immediate branches; also more assembler workarounds.
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llvm-svn: 79014
2009-08-14 18:31:44 +00:00
Evan Cheng
45d6a21e21
Shrink ADR and LDR from constantpool late during constantpool island pass.
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llvm-svn: 78970
2009-08-14 00:32:16 +00:00
Evan Cheng
9302c40108
Remove an Darwin assembler workaround.
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llvm-svn: 78777
2009-08-12 01:56:42 +00:00
Evan Cheng
65f3e466df
Shrink ADDS, ADC, RSB, and SUBS.
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llvm-svn: 78776
2009-08-12 01:49:45 +00:00
Evan Cheng
a29ee9f509
Shrinkify Thumb2 r = add sp, imm.
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llvm-svn: 78745
2009-08-11 23:00:31 +00:00
Evan Cheng
783028063e
Shrinkify Thumb2 load / store multiple instructions.
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llvm-svn: 78717
2009-08-11 21:11:32 +00:00
Evan Cheng
249f07cf57
Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.
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llvm-svn: 78659
2009-08-11 09:37:40 +00:00
Evan Cheng
49aac700f4
Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch of thumb2 tests to FileCheck.
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llvm-svn: 78622
2009-08-10 23:56:04 +00:00
Evan Cheng
f0bb0f5204
Handle the constantfp created during post-legalization dag combiner phase.
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llvm-svn: 78594
2009-08-10 20:25:59 +00:00
Jakob Stoklund Olesen
f73b30b329
Simplify RegScavenger::forward a bit more.
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Verify that early clobber registers and their aliases are not used.
All changes to RegsAvailable are now done as a transaction so the order of
operands makes no difference.
The included test case is from PR4686. It has behaviour that was dependent on the order of operands.
llvm-svn: 78465
2009-08-08 13:18:47 +00:00
Evan Cheng
2bdb247c12
Thumb2 32-bit ldm / stm needs .w suffix if submode is ia.
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llvm-svn: 78410
2009-08-07 21:19:10 +00:00
Evan Cheng
0dab4cc8a0
Fix support to use NEON for single precision fp math.
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llvm-svn: 78397
2009-08-07 19:30:41 +00:00
Evan Cheng
a565450757
Another coalescer bug. When a dead copy is eliminated, transfer the kill to a def of the exact register rather than a super-register.
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llvm-svn: 78376
2009-08-07 07:14:14 +00:00
Evan Cheng
48b49cf5b9
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
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This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
Evan Cheng
eb8c4db271
Disable stack coloring with register for now. It's not able to set kill markers.
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llvm-svn: 78179
2009-08-05 07:26:17 +00:00
Evan Cheng
87e24bb76e
Another nasty coalescer bug (is there another kind):
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After coalescing reg1027's def and kill are both at the same point:
%reg1027,0.000000e+00 = [56,814:0) 0@70-(814)
bb5:
60 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
68 %reg1027<def> = t2LDRi12 %reg1027<kill>, 8, 14, %reg0
76 t2CMPzri %reg1038<kill,undef>, 0, 14, %reg0, %CPSR<imp-def>
84 %reg1027<def> = t2MOVr %reg1027, 14, %reg0, %reg0
96 t2Bcc mbb<bb5,0x2030910>, 1, %CPSR<kill>
Do not remove the kill marker on t2LDRi12.
llvm-svn: 78178
2009-08-05 07:05:41 +00:00
Evan Cheng
9b8516d864
One more. Transfer kill of the larger register when lowering an EXTRACT_SUBREG.
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llvm-svn: 78145
2009-08-05 02:25:11 +00:00
Evan Cheng
d85e73ca64
One more place where subreg lowering forgot to transfer undefness.
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llvm-svn: 78144
2009-08-05 01:57:22 +00:00
Evan Cheng
3020badc5c
If the insert_subreg source is <undef>, insert an implicit_def instead of a copy.
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llvm-svn: 78141
2009-08-05 01:29:24 +00:00
Evan Cheng
e366789b50
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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llvm-svn: 78126
2009-08-04 23:47:55 +00:00
Evan Cheng
7963a20a2d
Fix test.
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llvm-svn: 78113
2009-08-04 22:22:58 +00:00
Evan Cheng
2ec9ab08d8
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
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llvm-svn: 78104
2009-08-04 21:12:13 +00:00
Evan Cheng
29fe8806d5
In thumb mode, r7 is used as frame register. This fixes pr4681.
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llvm-svn: 78086
2009-08-04 18:46:17 +00:00
Evan Cheng
817618d570
Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction.
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llvm-svn: 78030
2009-08-04 01:41:15 +00:00
Evan Cheng
ff81990e49
Fix a coaelescer bug. If a copy val# is extended to eliminate a non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy.
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llvm-svn: 77967
2009-08-03 08:41:59 +00:00
Evan Cheng
27ee95d344
Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.
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llvm-svn: 77939
2009-08-03 02:38:06 +00:00
Evan Cheng
3c2d9a0698
Test both darwin and linux.
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llvm-svn: 77852
2009-08-02 02:54:34 +00:00
Eli Friedman
cd4d9ff7fa
Hack to make this test work on platforms which aren't Macs. Fixing this
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myself because I'm getting tired of seeing the red buildbots, which have
been red since 5:30PM PDT last night.
Proposed supplement to developer policy: committers should make sure to
be around to watch for buildbot failures after committing.
llvm-svn: 77785
2009-08-01 16:37:18 +00:00
Evan Cheng
b9b4b9aa15
Workaround a couple of Darwin assembler bugs.
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llvm-svn: 77781
2009-08-01 06:13:52 +00:00
Evan Cheng
c165700a7f
Split t2MOVCCs since some assemblers do not recognize mov shifted register alias with predicate.
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llvm-svn: 77764
2009-08-01 01:43:45 +00:00
Evan Cheng
5ef6928dff
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
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instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
llvm-svn: 77756
2009-08-01 00:16:10 +00:00
Evan Cheng
0c9705feed
Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .align
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to ensure the instruction that follows a TBB (when the number of table entries
is odd) is 2-byte aligned.
Patch by Sandeep Patel.
llvm-svn: 77705
2009-07-31 18:35:56 +00:00
Evan Cheng
c9f31ae969
When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.
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llvm-svn: 77642
2009-07-30 23:29:25 +00:00
David Goodwin
62efc71b9f
Darwin assembler now recognizes "orn", so remove workaround.
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llvm-svn: 77627
2009-07-30 21:51:41 +00:00
David Goodwin
d29f81da16
Darwin assembler now supports "rrx", so remove workaround.
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llvm-svn: 77625
2009-07-30 21:38:40 +00:00
David Goodwin
2eaffa79af
Cleanup and include code selection for some frame index cases.
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llvm-svn: 77622
2009-07-30 18:56:48 +00:00
Evan Cheng
31ac181755
tbb / tbh instructions only branch forward, not backwards.
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llvm-svn: 77522
2009-07-29 23:20:20 +00:00
Evan Cheng
fc846dd401
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
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llvm-svn: 77422
2009-07-29 02:18:14 +00:00
Evan Cheng
cf483eb0c0
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
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llvm-svn: 77364
2009-07-28 20:53:24 +00:00
David Goodwin
0c9e96bf09
Remove support for ORN to workaround <rdar://problem/7096522>.
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llvm-svn: 77363
2009-07-28 20:51:25 +00:00
David Goodwin
dbc23ece04
Add workaround for <rdar://problem/7098328>.
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llvm-svn: 77340
2009-07-28 18:15:38 +00:00
David Goodwin
e94d490b89
Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag.
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llvm-svn: 77329
2009-07-28 17:06:49 +00:00
Evan Cheng
b740190d2e
- More refactoring. This gets rid of all of the getOpcode calls.
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- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
llvm-svn: 77300
2009-07-28 05:48:47 +00:00
David Goodwin
0bcb94eeff
ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM.
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llvm-svn: 77275
2009-07-27 23:34:12 +00:00
David Goodwin
471e9f5b8d
Add ".w" suffix for wide thumb-2 instructions.
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llvm-svn: 77199
2009-07-27 16:31:55 +00:00