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3112 Commits

Author SHA1 Message Date
Dan Gohman
59cddd1327 Change push_all to a non-virtual function and implement it in the 
base class, since all the implementations are the same.

llvm-svn: 104659
 2010-05-26 01:10:55 +00:00
Dan Gohman
ba28c900a2 Delete an unused function. 
llvm-svn: 104658
 2010-05-26 00:56:27 +00:00
Bill Wendling
04fbdac5ac Dale and Evan suggested putting the "check for setjmp" much earlier in the 
machine code generation. That's a good idea, so I made it so.

llvm-svn: 104655
 2010-05-26 00:32:40 +00:00
Evan Cheng
e34814c0bc Avoid adding duplicate function live-in's. 
llvm-svn: 104560
 2010-05-24 21:33:37 +00:00
Evan Cheng
241d2c434e Implement @llvm.returnaddress. rdar://8015977. 
llvm-svn: 104421
 2010-05-22 01:47:14 +00:00
Jim Grosbach
b6cc69c655 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419
 2010-05-22 01:06:18 +00:00
Evan Cheng
3c850aecf6 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs 
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377
 2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen
0f1087b284 Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction 
reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

llvm-svn: 104372
 2010-05-21 20:02:01 +00:00
Chris Lattner
1794093960 constify accessor. 
llvm-svn: 104325
 2010-05-21 17:47:50 +00:00
Jakob Stoklund Olesen
a3cca88b41 Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read." 
This reverts r104322. I think it was causing miscompilations.

llvm-svn: 104323
 2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen
edf8136011 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read. 
This correctly handles partial redefines and undef uses.

llvm-svn: 104322
 2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
6c22635216 If the first definition of a virtual register is a partial redef, add an 
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

llvm-svn: 104320
 2010-05-21 16:32:16 +00:00
Lang Hames
b579a16d82 Removed scaleNumbering method declaration from LiveInterval (not defined, not used). 
llvm-svn: 104311
 2010-05-21 03:04:04 +00:00
Evan Cheng
b5de7de4ce Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
llvm-svn: 104293
 2010-05-20 23:26:43 +00:00
Evan Cheng
0d88ad2de1 Add a hybrid bottom up scheduler that reduce register usage while avoiding 
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.

llvm-svn: 104216
 2010-05-20 06:13:19 +00:00
Jim Grosbach
523fa7acaa Fix the post-RA instruction scheduler to handle instructions referenced by 
more than one dbg_value instruction. rdar://7759363

llvm-svn: 104174
 2010-05-19 22:57:06 +00:00
Jakob Stoklund Olesen
56998cc8aa Add MachineInstr::readsVirtualRegister() in preparation for proper handling of 
partial redefines.

We are going to treat a partial redefine of a virtual register as a
read-modify-write:

  %reg1024:6 = OP

Unless the register is fully clobbered:

  %reg1024:6 = OP, %reg1024<imp-def>

MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.

llvm-svn: 104149
 2010-05-19 20:36:22 +00:00
mike-m
f12653f97d Fix enum to address array bounds regression. 
llvm-svn: 104058
 2010-05-18 21:22:12 +00:00
Eric Christopher
6ea9cf8425 More data/parsing support for tls directives. Add a few more testcases 
and cleanup comments as well.

llvm-svn: 103985
 2010-05-17 22:53:55 +00:00
Eric Christopher
380e16a725 Add some section and constant support for darwin TLS. 
llvm-svn: 103974
 2010-05-17 21:02:07 +00:00
Zhongxing Xu
a44f4d62bc Remove unused member variable. 
llvm-svn: 103936
 2010-05-17 09:47:55 +00:00
Jakob Stoklund Olesen
420d93c484 Add reg_nodbg_iterator 
llvm-svn: 103856
 2010-05-15 02:52:58 +00:00
Bill Wendling
e346a38ed4 Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what 
the variable actually tracks.

N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.

llvm-svn: 103802
 2010-05-14 21:14:32 +00:00
Evan Cheng
775549c9e7 Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. 
llvm-svn: 103746
 2010-05-13 23:55:47 +00:00
Dan Gohman
33e9c347bf Teach MachineLICM and MachineSink how to clear kill flags conservatively 
when they move instructions.

llvm-svn: 103737
 2010-05-13 20:34:42 +00:00
Dan Gohman
223379b3a9 Add a utility function for conservatively clearing kill flags, and make 
use of it in MachineCSE.

llvm-svn: 103726
 2010-05-13 19:24:00 +00:00
Dan Gohman
03e407ed83 Add initial kill flag support to FastISel. 
llvm-svn: 103529
 2010-05-11 23:54:07 +00:00
Jakob Stoklund Olesen
e27902ac68 Simplify the tracking of used physregs to a bulk bitor followed by a transitive 
closure after allocating all blocks.

Add a few more test cases for -regalloc=fast.

llvm-svn: 103500
 2010-05-11 20:30:28 +00:00
Dan Gohman
fb6f4da0e0 Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.

llvm-svn: 103481
 2010-05-11 17:31:57 +00:00
Chris Lattner
f474647323 remove a dead file. 
llvm-svn: 103383
 2010-05-09 17:34:13 +00:00
Dale Johannesen
1ee37ac5d4 Fix PR 7087, and probably other things, by extending 
getConstantFP to accept the two supported long double
target types.  This was not the original intent, but
there are other places that assume this works and it's
easy enough to do.

llvm-svn: 103299
 2010-05-07 21:35:53 +00:00
Chris Lattner
c1d0e3a79e switch MCSectionCOFF from a syntactic to semantic representation, 
patch by Peter Housel!

llvm-svn: 103267
 2010-05-07 17:17:41 +00:00
Dan Gohman
180422793f Add an "IsBottomUp" member function to FastISel, which will be used to 
support a new bottom-up mode.

llvm-svn: 103138
 2010-05-05 23:58:35 +00:00
Evan Cheng
d7bc27a079 Move REG_SEQUENCE removal to 2addr pass. 
llvm-svn: 103109
 2010-05-05 18:45:40 +00:00
Evan Cheng
25c07ac593 Teach liveintervalanalysis about virtual registers which are defined by reg_sequence instructions that are formed by registers defined by distinct instructions. e.g. 
80      %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
. . .
120     %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0

llvm-svn: 103102
 2010-05-05 18:27:40 +00:00
Bob Wilson
e81252b747 Combine the implementations of the core part of the SSAUpdater and 
MachineSSAUpdater to avoid duplicating all the code.

llvm-svn: 103060
 2010-05-04 23:18:19 +00:00
Dan Gohman
8bfd5f99b5 Factor out FastISel's code for materializing constants and other values 
in registers into a separate function to de-couple it from the
top-down-specific logic in getRegForValue.

llvm-svn: 102975
 2010-05-03 23:36:34 +00:00
Dan Gohman
68f04d06c8 Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.

llvm-svn: 102809
 2010-05-01 00:01:06 +00:00
Dan Gohman
78c9ada867 Elaborate on a comment. 
llvm-svn: 102637
 2010-04-29 16:57:54 +00:00
Evan Cheng
a02c9072fc Replace r102368 with code that's less fragile. This creates DBG_VALUE instructions for function arguments early and insert them after instruction selection is done. 
llvm-svn: 102554
 2010-04-28 23:08:54 +00:00
Chris Lattner
9867c1a075 Rework global alignment computation again. Now we do round up 
alignment of globals to the preferred alignment, but only when
there is no section specified on the global (by far the common
case).

llvm-svn: 102515
 2010-04-28 19:58:07 +00:00
Devang Patel
570e9d53a7 Emit debug info for byval parameters. 
llvm-svn: 102486
 2010-04-28 01:39:28 +00:00
Chris Lattner
19715b76b7 further simplify EmitAlignment by eliminating the 
ForcedAlignBits argument, tweaking the single client of it.

llvm-svn: 102484
 2010-04-28 01:08:40 +00:00
Chris Lattner
d14f04d0f7 remove a dead argument to EmitAlignment. 
llvm-svn: 102483
 2010-04-28 01:06:02 +00:00
Dale Johannesen
4327f03110 Add DBG_VALUE handling for byval parameters; this 
produces a comment on targets that support it, but
the Dwarf writer is not hooked up yet.

llvm-svn: 102372
 2010-04-26 20:06:49 +00:00
Bob Wilson
01b2bccb00 Update MachineSSAUpdater with the same changes I made for the IR-level 
SSAUpdater.  I'm going to try to refactor this to share most of the code
between them.

llvm-svn: 102353
 2010-04-26 17:40:49 +00:00
Dan Gohman
6680b97d89 Move FastISel's HandlePHINodesInSuccessorBlocks call down into FastISel 
itself too.

llvm-svn: 102176
 2010-04-23 15:29:50 +00:00
Dan Gohman
d819e7fc95 Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel 
and into SelectionDAGBuilder and FastISel.

llvm-svn: 102123
 2010-04-22 20:46:50 +00:00
Jakob Stoklund Olesen
8cf10fe9e4 Add fast register allocator, enabled with -regalloc=fast. 
So far this is just a clone of -regalloc=local that has been lobotomized to run
25% faster. It drops the least-recently-used calculations, and is just plain
stupid when it runs out of registers.

The plan is to make this go even faster for -O0 by taking advantage of the short
live intervals in unoptimized code. It should not be necessary to calculate
liveness when most virtual registers are killed 2-3 instructions after they are
born.

llvm-svn: 102006
 2010-04-21 18:02:42 +00:00
Dan Gohman
4ff2d817a3 Add more const qualifiers on TargetMachine and friends. 
llvm-svn: 101977
 2010-04-21 01:34:56 +00:00