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14015 Commits

Author SHA1 Message Date
Daniel Dunbar
469dddef0e MC/X86: Extend suffix matching hack to match 'q' suffix. 
llvm-svn: 103535
 2010-05-12 00:54:20 +00:00
Daniel Dunbar
e5a79692cf MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can 
be diced into atoms, and adjust getAtom() to take this into account.
 - This fixes relocations to symbols in fixed size literal sections, for
   example.

llvm-svn: 103532
 2010-05-12 00:38:17 +00:00
Dan Gohman
03e407ed83 Add initial kill flag support to FastISel. 
llvm-svn: 103529
 2010-05-11 23:54:07 +00:00
Evan Cheng
e46afad99b Avoid breaking vstd when reg_sequence is not used. 
llvm-svn: 103513
 2010-05-11 21:07:36 +00:00
Bill Wendling
4769f124cd Simplify this logic of creating a default Features object. 
llvm-svn: 103507
 2010-05-11 20:46:04 +00:00
Duncan Sands
7d5e4152c3 I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it 
to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.

llvm-svn: 103495
 2010-05-11 20:16:09 +00:00
Dan Gohman
5f389dacab Remove the "WantsWholeFile" concept, as it's no longer needed. CBE 
and the others use the regular addPassesToEmitFile hook now, and
llc no longer needs a bunch of redundant code to handle the
whole-file case.

llvm-svn: 103492
 2010-05-11 19:57:55 +00:00
Dan Gohman
fb6f4da0e0 Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.

llvm-svn: 103481
 2010-05-11 17:31:57 +00:00
Dan Gohman
eaacb8cb1f Remove the TargetLowering::getSubtarget() virtual function, which 
was unused. TargetMachine::getSubtarget() is used instead.

llvm-svn: 103474
 2010-05-11 16:21:03 +00:00
Kalle Raiskila
e302300b51 Make SPU backend not assert on jump tables. 
llvm-svn: 103466
 2010-05-11 11:00:02 +00:00
Evan Cheng
11130a0a22 Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
llvm-svn: 103459
 2010-05-11 07:26:32 +00:00
Bill Wendling
03d3cef073 Don't create a StringRef with a NULL value. 
llvm-svn: 103455
 2010-05-11 01:33:39 +00:00
Evan Cheng
5311f25b0b Model some vst3 and vst4 with reg_sequence. 
llvm-svn: 103453
 2010-05-11 01:19:40 +00:00
Bill Wendling
ed91169004 The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a 
string of features for that target. However LTO was using that string to pass
into the "create target machine" stuff. That stuff needed the feature string to
be in a particular form. In particular, it needed the CPU specified first and
then the attributes. If there isn't a CPU specified, it required it to be blank
-- e.g., ",+altivec". Yuck.

Modify the getDefaultSubtargetFeatures method to be a non-static member
function. For all attributes for a specific subtarget, it will add them in like
normal. It will also take a CPU string so that it can satisfy this horrible
syntax.

llvm-svn: 103451
 2010-05-11 00:30:02 +00:00
Evan Cheng
91747dc5dc Model some vld3 instructions with REG_SEQUENCE. 
llvm-svn: 103437
 2010-05-10 21:26:24 +00:00
Evan Cheng
7f0d8f1ab0 Model vld2 / vst2 with reg_sequence. 
llvm-svn: 103411
 2010-05-10 17:34:18 +00:00
Kalle Raiskila
61289abcda Fix encoding of 'sf' and 'sfh' instructions. 
llvm-svn: 103399
 2010-05-10 08:13:49 +00:00
Nathan Jeffords
7a7c1e206b updated handling dllexport in X86AsmPrinter 
changed dllexport code to use EmitBytes instead of EmitRawText, and changed the export option to use /EXPORT: instead of -export: on the windows platform

llvm-svn: 103377
 2010-05-09 08:40:06 +00:00
Nathan Jeffords
e9d4a38d5e made COFF target dllexport logic apply to all subtargets 
llvm-svn: 103373
 2010-05-09 05:52:28 +00:00
Chris Lattner
568058ef71 break coff symbol definition stuff out into proper MCStreamer callbacks, 
patch by Nathan Jeffords!

llvm-svn: 103346
 2010-05-08 19:54:22 +00:00
Jim Grosbach
2db1618b44 Clean up the conditional for handling of sign_extend_inreg based on 
whether the extract instructions are available.

rdar://7956878

llvm-svn: 103277
 2010-05-07 18:34:55 +00:00
Devang Patel
5b2d1c23a7 Use overloaded operators instead of DIDescriptor::getNode() 
llvm-svn: 103276
 2010-05-07 18:19:32 +00:00
Kalle Raiskila
9b9dc13910 Testing svn access with a note added to documentation. 
llvm-svn: 103271
 2010-05-07 18:06:28 +00:00
Chris Lattner
c1d0e3a79e switch MCSectionCOFF from a syntactic to semantic representation, 
patch by Peter Housel!

llvm-svn: 103267
 2010-05-07 17:17:41 +00:00
Evan Cheng
2d9c4df15f Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise. 
llvm-svn: 103235
 2010-05-07 02:04:02 +00:00
Evan Cheng
859a6d2135 Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values. 
llvm-svn: 103234
 2010-05-07 01:54:08 +00:00
Dan Gohman
79efb5a2ad When rematerializing, use the debug location of the original 
instruction, rather than a location near where the new instruction
is being inserted.

llvm-svn: 103232
 2010-05-07 01:28:10 +00:00
Evan Cheng
c82be8216f Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers. 
llvm-svn: 103218
 2010-05-07 00:24:52 +00:00
Daniel Dunbar
45589cd853 MC/X86: X86AbsMemAsmOperand is subclass of X86NoSegMemAsmOperand. 
- This fixes "leal 0, %eax", for example.

llvm-svn: 103205
 2010-05-06 22:39:14 +00:00
Chris Lattner
c788971da7 fix rdar://7947167 - llvm-mc doesn't match movsq 
llvm-svn: 103199
 2010-05-06 21:48:14 +00:00
Sean Callanan
4331428e24 Eliminated the classification of control registers into %ecr_ 
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196
 2010-05-06 20:59:00 +00:00
Daniel Dunbar
33433c1e3c MC/X86: Error out if we see a non-constant FK_Data_1 or FK_Data_2 fixup, since 
we don't currently support relaxing them.

llvm-svn: 103195
 2010-05-06 20:34:01 +00:00
Dan Gohman
497e752655 Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it 
doesn't have to guess.

llvm-svn: 103194
 2010-05-06 20:33:48 +00:00
Evan Cheng
80f3051bb7 Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. 
llvm-svn: 103193
 2010-05-06 19:06:44 +00:00
Bob Wilson
e5f295c76d Add a missing break statement to fix unintentional fall-through 
(replacing the previous patch for the same issue).

llvm-svn: 103183
 2010-05-06 16:05:26 +00:00
Jim Grosbach
bffae8af60 Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com> 
llvm-svn: 103181
 2010-05-06 15:32:49 +00:00
Shantonu Sen
0fc6812809 Fix "warning: extra ';' inside a struct or union" when building llvm with clang 
llvm-svn: 103179
 2010-05-06 14:57:47 +00:00
Evan Cheng
4c3022f869 Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170. 
llvm-svn: 103172
 2010-05-06 06:36:08 +00:00
Dan Gohman
ff6a33e8da Revert r103157, which broke test/CodeGen/ARM/2009-11-30-LiveVariablesBug.ll. 
llvm-svn: 103163
 2010-05-06 05:08:57 +00:00
Eric Christopher
72ca6fc94e Revert r103156 since it was breaking the build bots. 
Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td

llvm-svn: 103159
 2010-05-06 02:29:06 +00:00
Evan Cheng
b877797172 Fix an obvious bug in isMoveInstr. It needs to return sub-register indices. 
llvm-svn: 103157
 2010-05-06 01:54:03 +00:00
Evan Cheng
f25111f27f Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. 
llvm-svn: 103156
 2010-05-06 01:52:03 +00:00
Evan Cheng
d02b8d33c4 Cosmetic changes. 
llvm-svn: 103155
 2010-05-06 01:34:11 +00:00
Evan Cheng
960323d4a7 storeRegToStackSlot has forgotten about QPR_8 register class. 
llvm-svn: 103154
 2010-05-06 01:32:54 +00:00
Jim Grosbach
e04cc6cb43 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136
 2010-05-05 23:44:43 +00:00
Sean Callanan
7edf493591 Fixed a sign-extension bug in the X86 disassembler 
that was causing PC-relative branch targets to be
evaluated incorrectly.  Also added support for
checking operand values to the llvm-mc tester.

llvm-svn: 103128
 2010-05-05 22:47:27 +00:00
Evan Cheng
cfe5f2dba5 Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order. 
llvm-svn: 103124
 2010-05-05 22:15:40 +00:00
Dan Gohman
87a1315fce No-ops emitted for scheduling don't correspond with anything in the 
user's source, so don't arbitrarily assign them a debug location.

llvm-svn: 103121
 2010-05-05 20:58:01 +00:00
Jim Grosbach
3630aff780 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119
 2010-05-05 20:44:35 +00:00
Evan Cheng
6a76e7d9ae Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. 
llvm-svn: 103104
 2010-05-05 18:28:36 +00:00