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Author SHA1 Message Date
Jakob Stoklund Olesen
5c0d2aecc5 Add a LiveRangeEdit delegate callback before shrinking a live range. 
The register allocator needs to adjust its live interval unions when that happens.

llvm-svn: 127774
 2011-03-16 22:56:16 +00:00
Jakob Stoklund Olesen
8751b4e276 Erase virtual registers that are unused after DCE. 
llvm-svn: 127773
 2011-03-16 22:56:13 +00:00
Jakob Stoklund Olesen
940b7d46d3 Tag cached interference with a user-provided tag instead of the virtual register number. 
The live range of a virtual register may change which invalidates the cached
interference information.

llvm-svn: 127772
 2011-03-16 22:56:11 +00:00
Jakob Stoklund Olesen
7b60f4161a Clarify debugging output. 
llvm-svn: 127771
 2011-03-16 22:56:08 +00:00
Cameron Zwarich
2bb1e45ea3 The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byte 
rather than an int. Thankfully, this only causes LLVM to miss optimizations, not
generate incorrect code.

This just fixes the zext at the return. We still insert an i32 ZextAssert when
reading a function's arguments, but it is followed by a truncate and another i8
ZextAssert so it is not optimized.

llvm-svn: 127766
 2011-03-16 22:20:18 +00:00
Cameron Zwarich
005920cae9 Rename a test to be more inclusive. 
llvm-svn: 127765
 2011-03-16 22:20:12 +00:00
Cameron Zwarich
860d06739b Don't recompute something that we already have in a local variable. 
llvm-svn: 127764
 2011-03-16 22:20:07 +00:00
Daniel Dunbar
8757b8c000 Revert r127757, "Patch to a fix dwarf relocation problem on ARM. One-line fix 
plus the test where it used to break.", which broke Clang self-host of a
Debug+Asserts compiler, on OS X.

llvm-svn: 127763
 2011-03-16 22:16:39 +00:00
Richard Osborne
8b90369d96 Add XCore intrinsics for setclk, setrdy. 
llvm-svn: 127761
 2011-03-16 21:56:00 +00:00
Renato Golin
bf788a5626 Patch to a fix dwarf relocation problem on ARM. One-line fix plus the test where it used to break. 
llvm-svn: 127757
 2011-03-16 21:05:52 +00:00
Cameron Zwarich
05eb0080d6 Add a test for i1 zeroext arguments on x86-64. We currently generate code that 
conforms to the ABI, but DAGCombine could in theory recognize the sequence of
zext asserts and truncates and generate incorrect code.

llvm-svn: 127754
 2011-03-16 20:15:44 +00:00
Richard Osborne
318e25c620 Add checkevent intrinsic to check if any resources owned by the current thread 
can event.

llvm-svn: 127741
 2011-03-16 18:34:00 +00:00
NAKAMURA Takumi
7fd500c31d test/CodeGen/X86: FileCheck-ize and add actions for x86_64-linux and x86_64-win32. 
llvm-svn: 127734
 2011-03-16 13:53:07 +00:00
NAKAMURA Takumi
aa13f3550e test/CodeGen/X86: Add a pattern for Win64. 
llvm-svn: 127733
 2011-03-16 13:52:51 +00:00
NAKAMURA Takumi
e776f16e9d test/CodeGen/X86: FileCheck-ize and add explicit -mtriple=x86_64-linux. They are useless to Win64 target. 
llvm-svn: 127732
 2011-03-16 13:52:38 +00:00
NAKAMURA Takumi
bfbbe15937 test/CodeGen/X86/byval*.ll: Win64 has not supported byval yet. 
llvm-svn: 127731
 2011-03-16 13:52:20 +00:00
NAKAMURA Takumi
73a9789e43 test/CodeGen/X86/dyn-stackalloc.ll: FileCheck-ize. 
llvm-svn: 127730
 2011-03-16 13:52:08 +00:00
Cameron Zwarich
c60b47a7e2 Fix a comment. 
llvm-svn: 127728
 2011-03-16 08:13:42 +00:00
NAKAMURA Takumi
341bf54557 lib/Support/raw_ostream.cpp: On mingw, report_fatal_error() should not be called at dtor context. 
report_fatal_error() invokes exit(). We know report_fatal_error() might not write messages to stderr when any errors were detected on FD == 2.

llvm-svn: 127726
 2011-03-16 02:53:39 +00:00
NAKAMURA Takumi
bcbcf099b4 Windows/PathV2.inc: [PR8520] Recognize "NUL" as special (character) file. 
FIXME: It is a temporal hack. We should detect as many "special file name" as possible.
llvm-svn: 127724
 2011-03-16 02:53:32 +00:00
NAKAMURA Takumi
042801b7d2 Windows/Path.inc: [PR6270] PathV1::makeUnique(): Give arbitrary initial seed for workaround. 
FIXME: We should use sys::fs::unique_file() in future.
llvm-svn: 127723
 2011-03-16 02:53:24 +00:00
Jim Grosbach
c68c99f640 Tidy up. Whitespace and 80 column. 
llvm-svn: 127721
 2011-03-16 01:21:55 +00:00
Devang Patel
f0148aca2e Do not accidently initialize NumDbgValueLost and NumDbgLineLost counts. 
llvm-svn: 127720
 2011-03-16 00:27:57 +00:00
Cameron Zwarich
7fd94ea393 Only convert allocas to scalars if it is profitable. The profitability metric I 
chose is having a non-memcpy/memset use and being larger than any native integer
type. Originally I chose having an access of a size smaller than the total size
of the alloca, but this caused some minor issues on the spirit benchmark where
SRoA runs again after some inlining.

This fixes <rdar://problem/8613163>.

llvm-svn: 127718
 2011-03-16 00:13:44 +00:00
Cameron Zwarich
68f72463eb Add native integer type TargetData to some existing tests. 
llvm-svn: 127717
 2011-03-16 00:13:40 +00:00
Cameron Zwarich
88790f3d4d Better use initializer lists. 
llvm-svn: 127716
 2011-03-16 00:13:37 +00:00
Cameron Zwarich
f09bb5f2f5 Add a clarifying comment. 
llvm-svn: 127715
 2011-03-16 00:13:35 +00:00
Cameron Zwarich
96e380e650 Add TargetData::fitsInLegalInteger(). 
llvm-svn: 127714
 2011-03-16 00:13:28 +00:00
Johnny Chen
e88573849d There were two issues fixed: 
1. The ARM Darwin *r9 call instructions were pseudo-ized recently.
   Modify the ARMDisassemblerCore.cpp file to accomodate the change.

2. The disassembler was unnecessarily adding 8 to the sign-extended imm24:

   imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate)
                                       // Encoding A1

   It has no business doing such.  Removed the offending logic.

Add test cases to arm-tests.txt.

llvm-svn: 127707
 2011-03-15 22:27:33 +00:00
John Thompson
da294e31da Add scei vendor 
llvm-svn: 127705
 2011-03-15 21:51:56 +00:00
Bill Wendling
c12aadb9b6 The VTBL (and VTBX) instructions are rather permissive concerning the masks they 
accept. If a value in the mask is out of range, it uses the value 0, for VTBL,
or leaves the value unchanged, for VTBX.

llvm-svn: 127700
 2011-03-15 21:15:20 +00:00
Jakob Stoklund Olesen
26ac368165 Trace back through sibling copies to hoist spills and find rematerializable defs. 
After live range splitting, an original value may be available in multiple
registers. Tracing back through the registers containing the same value, find
the best place to insert a spill, determine if the value has already been
spilled, or discover a reaching def that may be rematerialized.

This is only the analysis part. The information is not used for anything yet.

llvm-svn: 127698
 2011-03-15 21:13:25 +00:00
Jakob Stoklund Olesen
992adc7152 Preserve both isPHIDef and isDefByCopy bits when copying parent values. 
llvm-svn: 127697
 2011-03-15 21:13:22 +00:00
NAKAMURA Takumi
82c316b78a lit/ProgressBar.py: [PR7919] Improve line wrap for XN-incapable terminals. 
On Win32 console, emitting char to col#79 causes linefeed, and the cursor will not return to col#79 upper line with backspace.

llvm-svn: 127696
 2011-03-15 21:07:44 +00:00
Bill Wendling
388dad6d62 Some minor cleanups based on feedback. 
llvm-svn: 127694
 2011-03-15 20:47:26 +00:00
Jim Grosbach
611d473405 Trailing whitespae. 
llvm-svn: 127691
 2011-03-15 20:25:54 +00:00
Cameron Zwarich
333ed540e7 Clean up something noticed by Fritz. 
llvm-svn: 127684
 2011-03-15 18:42:33 +00:00
Evan Cheng
59ba6777c3 Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587 
llvm-svn: 127683
 2011-03-15 18:41:52 +00:00
Richard Osborne
601c8a703b Don't indent cases in a switch, no functionality change. 
llvm-svn: 127681
 2011-03-15 15:55:30 +00:00
Richard Osborne
af1b66c427 On the XCore the scavenging slot should be closest to the SP. 
llvm-svn: 127680
 2011-03-15 15:10:11 +00:00
Oscar Fuentes
d892829b56 is_llvm_target_library: recognize libraries without the LLVM prefix. 
Without this cmake fails at configuration when some target pass
"native" on LLVM_LINK_COMPONENTS and that is expanded to "X86".

llvm-svn: 127679
 2011-03-15 14:53:53 +00:00
Richard Osborne
70204c1c29 Add XCore intrinsics for getps, setps, setsr and clrsr. 
llvm-svn: 127678
 2011-03-15 13:45:47 +00:00
Justin Holewinski
8948485aa7 PTX: Set PTX 2.0 as the minimum supported version 
- Remove PTX 1.4 code generation
- Change type of intrinsics to .v4.i32 instead of .v4.i16
- Add and/or/xor integer instructions

llvm-svn: 127677
 2011-03-15 13:24:15 +00:00
Duncan Sands
e91289191a Silence compiler warning about case values not being in the enumerated type 
MCFixupKind.  This is the same technique that is used elsewhere in MC.

llvm-svn: 127676
 2011-03-15 08:54:51 +00:00
Duncan Sands
fc3e4d63e1 Avoid a compiler warning about reg possibly being used uninitialized 
when building with assertions disabled.

llvm-svn: 127675
 2011-03-15 08:41:24 +00:00
Cameron Zwarich
7947e73536 Do not add PHIs with no users when creating LCSSA form. Patch by Andrew Clinton. 
llvm-svn: 127674
 2011-03-15 07:41:25 +00:00
Nick Lewycky
e30c07ab2b Add C++ global operator {new,new[],delete,delete[]}(unsigned {int,long}) to the 
memory builtins as equivalent to malloc/free.

This is different from any attribute we have. For example, you can delete the
allocators when their result is unused, but you can't collapse two calls to the
same function, even if no global/memory state has changed in between. The
noalias return states that the result does not alias any other pointer, but
instcombine optimizes malloc() as though the result is non-null for the purpose
of eliminating unused pointers.

llvm-svn: 127673
 2011-03-15 07:31:32 +00:00
Evan Cheng
29faaebae9 Add a peephole optimization to optimize pairs of bitcasts. e.g. 
v2 = bitcast v1
...
v3 = bitcast v2
...
   = v3
=>
v2 = bitcast v1
...
   = v1
if v1 and v3 are of in the same register class.

bitcast between i32 and fp (and others) are often not nops since they
are in different register classes. These bitcast instructions are often
left because they are in different basic blocks and cannot be
eliminated by dag combine.

rdar://9104514

llvm-svn: 127668
 2011-03-15 05:13:13 +00:00
Evan Cheng
14eff5d627 - Add "Bitcast" target instruction property for instructions which perform 
nothing more than a bitcast.
- Teach tablegen to automatically infer "Bitcast" property.

llvm-svn: 127667
 2011-03-15 05:09:26 +00:00
Eli Friedman
c0bfbd0610 PR9450: Make switch optimization in SimplifyCFG not dependent on the ordering 
of pointers in an std::map.

llvm-svn: 127650
 2011-03-15 02:23:35 +00:00