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11612 Commits

Author SHA1 Message Date
Jim Grosbach
d788f9b580 back out 104862/104869. Can reuse stacksave after all. Very cool. 
llvm-svn: 104897
 2010-05-27 23:11:57 +00:00
Dan Gohman
92ee877dcd Make ParseIRFile and getLazyIRFileModule incoporate the underlying 
error message string into their own error message string, so that
the information isn't lost.

llvm-svn: 104887
 2010-05-27 20:47:38 +00:00
Dan Gohman
d13e45d0ec Don't special-case stdout in llvm::WriteBitcodeToFile; just consider 
it to be the caller's responsibility to provide a stream in binary
mode. This fixes a layering violation and avoids an outs() call.

llvm-svn: 104878
 2010-05-27 20:06:51 +00:00
Jim Grosbach
0ff473d68a hook ISD::STACKADDR to an intrinsic 
llvm-svn: 104869
 2010-05-27 18:52:11 +00:00
Jim Grosbach
c2c7753f15 add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EH 
to update the jmpbuf in the presence of VLAs.

llvm-svn: 104862
 2010-05-27 18:23:48 +00:00
Dan Gohman
9789093ab7 Add basic error checking to MemoryBuffer::getSTDIN. 
llvm-svn: 104855
 2010-05-27 17:31:51 +00:00
Jim Grosbach
73ce6687df remove incorrect GCCBuiltin<> usage 
llvm-svn: 104833
 2010-05-27 15:04:02 +00:00
Gabor Greif
d8e3e9f572 typo 
llvm-svn: 104832
 2010-05-27 09:48:47 +00:00
Dan Gohman
0b5922b032 Fix Lint printing warnings multiple times. Remove the ErrorStr 
option from lintModule, which was an artifact from being
based on Verifier code.

llvm-svn: 104765
 2010-05-26 22:28:53 +00:00
Daniel Dunbar
bf243d9440 MC: Add TargetMachine support for setting the value of MCRelaxAll with 
-filetype=obj.

llvm-svn: 104747
 2010-05-26 21:48:55 +00:00
Jakob Stoklund Olesen
1c0aa5f14a Add StringRef::compare_numeric and use it to sort TableGen register records. 
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

llvm-svn: 104745
 2010-05-26 21:47:28 +00:00
Jim Grosbach
bb4860d2a2 Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in 
ISD::. No functional change.

llvm-svn: 104734
 2010-05-26 20:22:18 +00:00
Bill Wendling
fbe85886bb Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by 
more than just the stack slot coloring algorithm.

llvm-svn: 104722
 2010-05-26 19:46:12 +00:00
Dan Gohman
616845c384 Eliminate the use of PriorityQueue and just use a std::vector, 
implementing pop with a linear search for a "best" element. The priority
queue was a neat idea, but in practice the comparison functions depend
on dynamic information.

llvm-svn: 104718
 2010-05-26 18:52:00 +00:00
Dan Gohman
3391366b42 Fix indentation. 
llvm-svn: 104717
 2010-05-26 18:37:48 +00:00
Daniel Dunbar
1b8e1aafae MC: Change RelaxInstruction to only take the input and output instructions. 
llvm-svn: 104713
 2010-05-26 18:15:06 +00:00
Daniel Dunbar
77240e2337 MC: Simplify MayNeedRelaxation to not provide the fixups, so we can query it 
before encoding.

llvm-svn: 104707
 2010-05-26 17:45:29 +00:00
Jakob Stoklund Olesen
83d2cfd6cd Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104704
 2010-05-26 17:27:12 +00:00
Daniel Dunbar
87dcbd1ee5 MC: Eliminate MCAsmFixup, replace with MCFixup. 
llvm-svn: 104699
 2010-05-26 15:18:56 +00:00
Daniel Dunbar
fe22195ea6 MC: Simplify MCFixup and increase the available offset size. 
llvm-svn: 104698
 2010-05-26 15:18:40 +00:00
Daniel Dunbar
55c1bf55fe MC: Use accessors for access to MCAsmFixup. 
llvm-svn: 104697
 2010-05-26 15:18:31 +00:00
Daniel Dunbar
a06aa279f4 MC: Eliminate MCFragment vtable, which was unnecessary. 
llvm-svn: 104689
 2010-05-26 06:50:57 +00:00
Eric Christopher
13ac28ede3 Temporarily revert r104655 as it's breaking the bots. 
llvm-svn: 104664
 2010-05-26 01:59:55 +00:00
Jakob Stoklund Olesen
0fefdf4d2a Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." 
This reverts commit 104654.

llvm-svn: 104660
 2010-05-26 01:21:14 +00:00
Dan Gohman
59cddd1327 Change push_all to a non-virtual function and implement it in the 
base class, since all the implementations are the same.

llvm-svn: 104659
 2010-05-26 01:10:55 +00:00
Dan Gohman
ba28c900a2 Delete an unused function. 
llvm-svn: 104658
 2010-05-26 00:56:27 +00:00
Bill Wendling
04fbdac5ac Dale and Evan suggested putting the "check for setjmp" much earlier in the 
machine code generation. That's a good idea, so I made it so.

llvm-svn: 104655
 2010-05-26 00:32:40 +00:00
Jakob Stoklund Olesen
a2f0c34e41 Replace the SubRegSet tablegen class with a less error-prone mechanism. 
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

llvm-svn: 104654
 2010-05-26 00:28:19 +00:00
Eric Christopher
371732bd2a Start adding mach-o tls reloc support. 
llvm-svn: 104651
 2010-05-26 00:02:12 +00:00
Jakob Stoklund Olesen
41388819f1 Drop the SuperregHashTable. It is essentially the same as SubregHashTable. 
llvm-svn: 104650
 2010-05-25 23:43:18 +00:00
Jakob Stoklund Olesen
9210d3b189 Print symbolic SubRegIndex names on machine operands. 
llvm-svn: 104628
 2010-05-25 19:49:38 +00:00
Jakob Stoklund Olesen
696fbed514 Remove NumberHack entirely. 
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

llvm-svn: 104627
 2010-05-25 19:49:33 +00:00
Eric Christopher
627e887b3d Make sure aeskeygenassist uses an unsigned immediate field. 
Fixes rdar://8017638

llvm-svn: 104617
 2010-05-25 17:33:22 +00:00
Jakob Stoklund Olesen
d1f4d14609 Switch SubRegSet to using symbolic SubRegIndices 
llvm-svn: 104571
 2010-05-24 23:03:18 +00:00
Jakob Stoklund Olesen
3a19b732d8 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data 
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563
 2010-05-24 21:46:58 +00:00
Evan Cheng
e34814c0bc Avoid adding duplicate function live-in's. 
llvm-svn: 104560
 2010-05-24 21:33:37 +00:00
Jakob Stoklund Olesen
9a54fec092 Add the SubRegIndex TableGen class. 
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492
 2010-05-24 14:48:12 +00:00
Daniel Dunbar
eb23d9ac22 MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches. 
llvm-svn: 104463
 2010-05-23 17:44:06 +00:00
Daniel Dunbar
ee525943d8 tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one. 
llvm-svn: 104452
 2010-05-22 21:02:29 +00:00
John Mosby
cec9b7fc9c Trivial change to dump() function for SparseBitVector 
llvm-svn: 104433
 2010-05-22 05:13:17 +00:00
Evan Cheng
241d2c434e Implement @llvm.returnaddress. rdar://8015977. 
llvm-svn: 104421
 2010-05-22 01:47:14 +00:00
Jim Grosbach
b6cc69c655 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419
 2010-05-22 01:06:18 +00:00
Eric Christopher
6bd67791da Add a new section and accessor for TLS data. 
llvm-svn: 104411
 2010-05-22 00:00:58 +00:00
Eric Christopher
0df4e8b6a5 Fix comment and whitespace. 
llvm-svn: 104392
 2010-05-21 22:39:11 +00:00
Evan Cheng
3c850aecf6 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs 
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377
 2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen
0f1087b284 Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction 
reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

llvm-svn: 104372
 2010-05-21 20:02:01 +00:00
Nathan Jeffords
28b485543b added an assertion to MCObjectWriter::WriteBytes to catch misuse of the ZeroFillSize parameter 
If the size of the string is greater than the zero fill size, the function will attempt to write a very large string of zeros to the object file (~4GB on 32 bit platforms). This assertion will catch the scenario and crash the program before the write occurs.

llvm-svn: 104334
 2010-05-21 18:23:56 +00:00
Chris Lattner
1794093960 constify accessor. 
llvm-svn: 104325
 2010-05-21 17:47:50 +00:00
Jakob Stoklund Olesen
a3cca88b41 Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read." 
This reverts r104322. I think it was causing miscompilations.

llvm-svn: 104323
 2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen
edf8136011 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read. 
This correctly handles partial redefines and undef uses.

llvm-svn: 104322
 2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
6c22635216 If the first definition of a virtual register is a partial redef, add an 
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

llvm-svn: 104320
 2010-05-21 16:32:16 +00:00
Matt Fleming
5d40d53cab Currently, createMachOStreamer() is invoked directly in llvm-mc which 
isn't ideal if we want to be able to use another object file format.

Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.

llvm-svn: 104318
 2010-05-21 12:54:43 +00:00
Matt Fleming
0ca99c0262 Add support for parsing the ELF .type assembler directive. 
llvm-svn: 104316
 2010-05-21 11:36:59 +00:00
Lang Hames
b579a16d82 Removed scaleNumbering method declaration from LiveInterval (not defined, not used). 
llvm-svn: 104311
 2010-05-21 03:04:04 +00:00
Evan Cheng
b5de7de4ce Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
llvm-svn: 104293
 2010-05-20 23:26:43 +00:00
Devang Patel
3d4cd812aa Rename variable. add comment. 
llvm-svn: 104274
 2010-05-20 20:35:24 +00:00
Daniel Dunbar
64807873ec tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor 
it.

llvm-svn: 104270
 2010-05-20 20:20:32 +00:00
Evan Cheng
0d88ad2de1 Add a hybrid bottom up scheduler that reduce register usage while avoiding 
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.

llvm-svn: 104216
 2010-05-20 06:13:19 +00:00
Eric Christopher
09658d704d Fix build by actually declaring the variable. 
llvm-svn: 104201
 2010-05-20 00:59:30 +00:00
Eric Christopher
1a7bc06b28 Partial code for emitting thread local bss data. 
llvm-svn: 104197
 2010-05-20 00:49:07 +00:00
Jim Grosbach
523fa7acaa Fix the post-RA instruction scheduler to handle instructions referenced by 
more than one dbg_value instruction. rdar://7759363

llvm-svn: 104174
 2010-05-19 22:57:06 +00:00
Jakob Stoklund Olesen
56998cc8aa Add MachineInstr::readsVirtualRegister() in preparation for proper handling of 
partial redefines.

We are going to treat a partial redefine of a virtual register as a
read-modify-write:

  %reg1024:6 = OP

Unless the register is fully clobbered:

  %reg1024:6 = OP, %reg1024<imp-def>

MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.

llvm-svn: 104149
 2010-05-19 20:36:22 +00:00
Evan Cheng
46e08acfa5 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. 
llvm-svn: 104147
 2010-05-19 20:19:50 +00:00
mike-m
f12653f97d Fix enum to address array bounds regression. 
llvm-svn: 104058
 2010-05-18 21:22:12 +00:00
Eric Christopher
4a9013f115 Make EmitTBSSSymbol take a section argument so that we can find it later. 
Fix up callers and users.

llvm-svn: 104057
 2010-05-18 21:16:04 +00:00
Kevin Enderby
14c986967b Added support in MC for Directional Local Labels. 
llvm-svn: 103989
 2010-05-17 23:08:19 +00:00
Eric Christopher
6ea9cf8425 More data/parsing support for tls directives. Add a few more testcases 
and cleanup comments as well.

llvm-svn: 103985
 2010-05-17 22:53:55 +00:00
Daniel Dunbar
7e141838cd MC: Add dyn_cast support to MCSection. 
- Of questionable utility, since in general anything which wants to do this should probably be within a target specific hook, which can rely on the sections being of the appropriate type. However, it can be useful for short term hacks.

llvm-svn: 103980
 2010-05-17 21:54:26 +00:00
Eric Christopher
380e16a725 Add some section and constant support for darwin TLS. 
llvm-svn: 103974
 2010-05-17 21:02:07 +00:00
Jakob Stoklund Olesen
011cea42b9 Optimize empty DenseMap iteration. 
llvm-svn: 103962
 2010-05-17 20:01:24 +00:00
Daniel Dunbar
8f5da3624f llvm-mc: Support reassignment of variables in one special case, when the 
variable has not yet been used in an expression. This allows us to support a few
cases that show up in real code (mostly because gcc generates it for Objective-C
on Darwin), without giving up a reasonable semantic model for assignment.

llvm-svn: 103950
 2010-05-17 17:46:23 +00:00
Zhongxing Xu
a44f4d62bc Remove unused member variable. 
llvm-svn: 103936
 2010-05-17 09:47:55 +00:00
Anton Korobeynikov
925a32ae37 Add support for thiscall calling convention. 
Patch by Charles Davis and Steven Watanabe!

llvm-svn: 103902
 2010-05-16 09:08:45 +00:00
Chris Lattner
a1f4042939 improve portability to systems that don't have round, patch by 
Evzen Muller!

llvm-svn: 103877
 2010-05-15 17:11:55 +00:00
Jakob Stoklund Olesen
420d93c484 Add reg_nodbg_iterator 
llvm-svn: 103856
 2010-05-15 02:52:58 +00:00
Evan Cheng
85497bd415 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also 
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.

llvm-svn: 103854
 2010-05-15 02:18:07 +00:00
Evan Cheng
0a651c3314 Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE 
instructions.

e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12

After REG_SEQUENCE is eliminated, we are left with:

%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5

The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible, 
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.

llvm-svn: 103835
 2010-05-14 23:21:14 +00:00
Dan Gohman
2859ef1a1b Add some comments about undef. 
llvm-svn: 103834
 2010-05-14 23:01:02 +00:00
Bill Wendling
e346a38ed4 Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what 
the variable actually tracks.

N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.

llvm-svn: 103802
 2010-05-14 21:14:32 +00:00
Devang Patel
2b99c27e47 Add support to preserve type info for the variables that are removed by the optimizer. 
llvm-svn: 103798
 2010-05-14 21:01:35 +00:00
Dan Gohman
6815a4c74d Use PassManagerBase, to give clients the option of using either 
FunctionPassManager or regular PassManager.

llvm-svn: 103773
 2010-05-14 15:35:10 +00:00
Dan Gohman
9383d0f144 Add an isNodeHidden to the graph traits, to support definition of 
subgraph views.

llvm-svn: 103772
 2010-05-14 15:29:31 +00:00
Evan Cheng
ec0d7e6cf2 Get rid of the bit twiddling to read / set OpActions and ValueTypeActions. The small saving in memory isn't worth the increase in runtime and code complexity in my opinion. 
llvm-svn: 103768
 2010-05-14 07:37:40 +00:00
Eric Christopher
ebea91f168 Add AsmParser support for darwin tbss directive. 
Nothing uses this yet.

llvm-svn: 103757
 2010-05-14 01:50:28 +00:00
Nick Lewycky
aeb998db39 Fix typo. 
llvm-svn: 103755
 2010-05-14 01:02:48 +00:00
Daniel Dunbar
7fee3c7b28 MC: Switch to completely lazy layout. 
- The eliminates the last major algorithmic problem with MC.

llvm-svn: 103754
 2010-05-14 00:51:14 +00:00
Daniel Dunbar
66c2ccec2d MC: Extend MCAsmLayout to explicitly track which fragments have been layed out, and enforce several invariants to LayoutFragment to ensure we only do layout in a sensible order. 
llvm-svn: 103753
 2010-05-14 00:37:21 +00:00
Daniel Dunbar
11467b2eaa MC: Switch MCFragment to storing the layout order index, not its index in the file. 
llvm-svn: 103751
 2010-05-14 00:37:14 +00:00
Daniel Dunbar
b2a98e0a16 MC: Change LayoutSection() to only do the section initializiation. 
Also, elimminate MCAsmLayout::set*, which are no longer needed.

llvm-svn: 103750
 2010-05-14 00:37:11 +00:00
Evan Cheng
775549c9e7 Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. 
llvm-svn: 103746
 2010-05-13 23:55:47 +00:00
Evan Cheng
5e115a09ec Eliminate use of magic numbers to access OpActions. It also has the effect of allowing more than 31 scalar value types. MAX_ALLOWED_VALUETYPE had already been updated to 64 a while back. 
llvm-svn: 103743
 2010-05-13 23:25:21 +00:00
Evan Cheng
f2572ea73b Fix up LoadExtActions, TruncStoreActions, and IndexedModeActions representation and setter and getter's so they will continue to work if the number of scalar ValueType's exceeds 31. 
llvm-svn: 103742
 2010-05-13 23:01:26 +00:00
Daniel Dunbar
86825a9719 MC: Move Layout{Fragment,Section} into MCAsmLayout, and add LayoutFile(). 
llvm-svn: 103738
 2010-05-13 20:40:12 +00:00
Dan Gohman
33e9c347bf Teach MachineLICM and MachineSink how to clear kill flags conservatively 
when they move instructions.

llvm-svn: 103737
 2010-05-13 20:34:42 +00:00
Evan Cheng
fd47525512 80 col violation. 
llvm-svn: 103733
 2010-05-13 20:14:58 +00:00
Dan Gohman
223379b3a9 Add a utility function for conservatively clearing kill flags, and make 
use of it in MachineCSE.

llvm-svn: 103726
 2010-05-13 19:24:00 +00:00
Daniel Dunbar
b142c00db4 MC: Factor out MCAssembler::ComputeFragmentSize. 
llvm-svn: 103724
 2010-05-13 18:35:06 +00:00
Daniel Dunbar
10ef3afee3 Fix const ilist_node::get{Prev,Next}Node() to actually compile. Picky, picky. 
llvm-svn: 103723
 2010-05-13 18:35:02 +00:00
Daniel Dunbar
5a601f9e09 MC: Add section layout order indices to MCSectionData. 
llvm-svn: 103715
 2010-05-13 15:17:26 +00:00
Daniel Dunbar
5ef1bcbb97 MC: Add MCAsmLayout::FragmentReplaced() helper function. 
llvm-svn: 103709
 2010-05-13 08:43:31 +00:00