Jim Grosbach
76dd8a9702
ARM VST1 w/ writeback assembly parsing and encoding.
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llvm-svn: 143369
2011-10-31 21:50:31 +00:00
Owen Anderson
5fdb303642
Specify that the high bit of the alignment field is fixed to 0 on these instructions.
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llvm-svn: 143220
2011-10-28 20:43:24 +00:00
Jim Grosbach
fabe0f2f0b
ARM assembly parsing and encoding for VLD1 with writeback.
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Four entry register lists.
llvm-svn: 142882
2011-10-25 00:14:01 +00:00
Jim Grosbach
e8a2edd71c
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.
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llvm-svn: 142877
2011-10-24 23:40:46 +00:00
Jim Grosbach
688186941f
ARM assembly parsing and encoding for VLD1 w/ writeback.
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Three entry register list variation.
llvm-svn: 142876
2011-10-24 23:26:05 +00:00
Jim Grosbach
cf4fba1dd0
ARM assembly parsing and encoding for VLD1 w/ writeback.
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One and two length register list variants.
llvm-svn: 142861
2011-10-24 22:16:58 +00:00
Jim Grosbach
4a6508dd4e
ARM refactor am6offset usage for VLD1.
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Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
llvm-svn: 142853
2011-10-24 21:45:13 +00:00
Jim Grosbach
d964cf8939
Assembly parsing for 4-register sequential variant of VLD2.
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llvm-svn: 142704
2011-10-21 23:58:57 +00:00
Jim Grosbach
a6e536367e
Assembly parsing for 2-register sequential variant of VLD2.
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llvm-svn: 142691
2011-10-21 22:21:10 +00:00
Jim Grosbach
68dfc88f95
Assembly parsing for 4-register variant of VLD1.
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llvm-svn: 142682
2011-10-21 20:35:01 +00:00
Jim Grosbach
2c1ca90ac9
Assembly parsing for 3-register variant of VLD1.
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llvm-svn: 142675
2011-10-21 20:02:19 +00:00
Jim Grosbach
6bb38d0e97
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
Jim Grosbach
501c72cdc5
Remove some outdated comments.
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llvm-svn: 142653
2011-10-21 16:14:12 +00:00
Jim Grosbach
e9d1df8266
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
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llvm-svn: 142583
2011-10-20 15:04:25 +00:00
Jim Grosbach
972f26d936
ARM VTBX (one register) assembly parsing and encoding.
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llvm-svn: 142581
2011-10-20 14:48:50 +00:00
Jim Grosbach
6a932d6ad1
ARM VTBL (one register) assembly parsing and encoding.
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llvm-svn: 142441
2011-10-18 23:02:30 +00:00
Jim Grosbach
d748cf251f
Yet more ARM NEON assembly parsing for the lane index operand.
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llvm-svn: 142416
2011-10-18 20:21:17 +00:00
Jim Grosbach
ff8c26a53f
ARM vmla/vmls assembly parsing for the lane index operand.
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llvm-svn: 142413
2011-10-18 20:14:56 +00:00
Jim Grosbach
ed5cb526e2
ARM vmov assembly parsing for the lane index operand.
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llvm-svn: 142412
2011-10-18 20:10:47 +00:00
Jim Grosbach
988b8dd4ce
ARM vmla/vmls assembly parsing for the lane index operand.
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llvm-svn: 142389
2011-10-18 18:27:07 +00:00
Jim Grosbach
2752e0b869
ARM vqdmulh assembly parsing for the lane index operand.
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llvm-svn: 142386
2011-10-18 18:12:09 +00:00
Jim Grosbach
b56577b650
ARM vmul assembly parsing for the lane index operand.
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llvm-svn: 142381
2011-10-18 18:01:52 +00:00
Jim Grosbach
4a138cb8d9
ARM vqdmlal assembly parsing for the lane index operand.
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llvm-svn: 142365
2011-10-18 17:16:30 +00:00
Jim Grosbach
031bb99231
ARM assembly parsing and encoding for VMOV.i64.
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llvm-svn: 142356
2011-10-18 16:18:11 +00:00
Jim Grosbach
bcfb4ed53c
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
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llvm-svn: 142321
2011-10-18 00:22:00 +00:00
Jim Grosbach
1e994e76a7
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
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llvm-svn: 142303
2011-10-17 23:09:09 +00:00
Jim Grosbach
f3d495fbbd
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
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NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
llvm-svn: 142293
2011-10-17 22:26:03 +00:00
Jim Grosbach
eeb05f7532
Tidy up organization.
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llvm-svn: 142248
2011-10-17 21:00:11 +00:00
Jim Grosbach
94980a23e6
ARM NEON assembly parsing and encoding for VDUP(scalar).
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llvm-svn: 141446
2011-10-07 23:56:00 +00:00
Chad Rosier
3c596dbe51
Remove the VMOVQQ pseudo instruction.
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llvm-svn: 138177
2011-08-20 00:52:40 +00:00
Chad Rosier
0d49bb37fb
Remove VMOVQQQQ pseudo instruction.
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llvm-svn: 138174
2011-08-20 00:40:14 +00:00
Owen Anderson
2e722e7cd4
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
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llvm-svn: 137686
2011-08-15 23:38:54 +00:00
Owen Anderson
894585de33
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
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llvm-svn: 137635
2011-08-15 18:44:44 +00:00
Owen Anderson
ffe1c55752
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Bob Wilson
e241d2cd04
Add missing register constraint for some VLD3/VLD4 pseudo instructions.
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<rdar://problem/9878189>
llvm-svn: 136962
2011-08-05 07:24:09 +00:00
Owen Anderson
7a380bac06
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
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llvm-svn: 135290
2011-07-15 18:46:47 +00:00
Owen Anderson
4cf53f7ec4
Remove unnecessary duplicate instruction definitions that simply overloaded the type of VEXT. This can be achieved with a Pat definition, and is much more disassembler friendly.
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llvm-svn: 135283
2011-07-15 17:48:05 +00:00
Jim Grosbach
eff8e5d153
Clean up a few 80 column violations.
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llvm-svn: 132946
2011-06-13 22:54:22 +00:00
Tanya Lattner
aa1f6df650
Fix encoding for VEXTdf.
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llvm-svn: 132486
2011-06-02 21:25:24 +00:00
Mon P Wang
08d3b69861
Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32
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llvm-svn: 131085
2011-05-09 17:47:27 +00:00
Mon P Wang
9aa67ff50a
Fixed encoding for VEXTqf
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llvm-svn: 129101
2011-04-07 19:56:12 +00:00
Owen Anderson
d4e1a2f2b6
Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler.
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llvm-svn: 128587
2011-03-30 23:45:29 +00:00
Cameron Zwarich
1b8f91d2c8
Add a ARM-specific SD node for VBSL so that forms with a constant first operand
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can be recognized. This fixes <rdar://problem/9183078>.
llvm-svn: 128584
2011-03-30 23:01:21 +00:00
Owen Anderson
d73041e884
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
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llvm-svn: 128461
2011-03-29 16:45:53 +00:00
Jim Grosbach
ee6075cda5
ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
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as for VDUP32d and VDUP32q, respectively.
llvm-svn: 127489
2011-03-11 20:44:08 +00:00
Jim Grosbach
3329263352
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
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and VDUPLN32d, respectively.
llvm-svn: 127486
2011-03-11 20:31:17 +00:00
Jim Grosbach
431682981d
ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
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as for VREV64d32 and VREV64q32, respectively.
llvm-svn: 127485
2011-03-11 20:18:05 +00:00
Bill Wendling
68934338ab
* Correct encoding for VSRI.
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* Add tests for VSRI and VSLI.
llvm-svn: 127297
2011-03-09 00:33:17 +00:00
Bill Wendling
b790c462c0
Correct the encoding for VRSRA and VSRA instructions.
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llvm-svn: 127294
2011-03-09 00:00:35 +00:00
Bill Wendling
ab9f04b6d8
* Fix VRSHR and VSHR to have the correct encoding for the immediate.
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* Update the NEON shift instruction test to expect what 'as' produces.
llvm-svn: 127293
2011-03-08 23:48:09 +00:00