Bruno Cardoso Lopes
632295a03c
Support x86 "eiz" and "riz" pseudo index registers in the assembler.
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llvm-svn: 109295
2010-07-24 00:06:39 +00:00
Bruno Cardoso Lopes
8907fcd2b5
Move AVX encoding tests to different files
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llvm-svn: 109269
2010-07-23 21:25:26 +00:00
Bruno Cardoso Lopes
a80b57e5fc
Add AVX version of CLMUL instructions
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llvm-svn: 109248
2010-07-23 18:41:12 +00:00
Bruno Cardoso Lopes
b9182e3051
Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual
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llvm-svn: 109204
2010-07-23 00:54:35 +00:00
Bruno Cardoso Lopes
7722724eee
Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step
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llvm-svn: 109168
2010-07-22 21:18:49 +00:00
Bruno Cardoso Lopes
5920e38cd2
Add more 256-bit forms for a bunch of regular AVX instructions
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Add 64-bit (GR64) versions of some instructions (which are not
described in their SSE forms, but are described in AVX)
llvm-svn: 109063
2010-07-21 23:53:50 +00:00
Bruno Cardoso Lopes
eea3b7ed83
Add missing AVX convert instructions. Those instructions are not described in their SSE forms (although they exist), but add the AVX forms anyway, so the assembler can benefit from it
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llvm-svn: 109039
2010-07-21 21:37:59 +00:00
Bruno Cardoso Lopes
d13d8c2562
Add AVX only vzeroall and vzeroupper instructions
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llvm-svn: 109002
2010-07-21 08:56:24 +00:00
Bruno Cardoso Lopes
c4d93a5a34
Add new AVX vpermilps, vpermilpd and vperm2f128 instructions
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llvm-svn: 108984
2010-07-21 03:07:42 +00:00
Bruno Cardoso Lopes
a7efb29695
Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it
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llvm-svn: 108983
2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes
e0dce1c741
Add new AVX vextractf128 instructions
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llvm-svn: 108964
2010-07-20 23:19:02 +00:00
Bruno Cardoso Lopes
b677cbc9b2
Add new AVX instruction vinsertf128
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llvm-svn: 108892
2010-07-20 19:44:51 +00:00
Bruno Cardoso Lopes
a4ef0f6f09
x86_32 tests for vbroadcast
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llvm-svn: 108789
2010-07-20 00:11:50 +00:00
Bruno Cardoso Lopes
88869cb4db
Add AVX vbroadcast new instruction
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llvm-svn: 108788
2010-07-20 00:11:13 +00:00
Bruno Cardoso Lopes
4ca44dda21
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
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llvm-svn: 108769
2010-07-19 23:32:44 +00:00
Daniel Dunbar
1dd74c37c5
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same
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instruction, we only want to allow the one for the current subtarget.
- This also fixes suffix matching for jmp instructions, because it eliminates
the ambiguity between 'jmpl' and 'jmpq'.
llvm-svn: 108746
2010-07-19 20:44:16 +00:00
Daniel Dunbar
220bd809bf
X86-64: Mark WINCALL and more tail call instructions as code gen only.
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llvm-svn: 108685
2010-07-19 07:21:07 +00:00
Daniel Dunbar
3b0ff3bac3
MC/X86: We now match instructions like "incl %eax" correctly for the arch we are
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assembling; remove crufty custom cleanup code.
llvm-svn: 108681
2010-07-19 06:14:54 +00:00
Bruno Cardoso Lopes
0616a418b6
Add AVX 256-bit compare instructions and a bunch of testcases
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llvm-svn: 108286
2010-07-13 22:06:38 +00:00
Bruno Cardoso Lopes
7bc71d2d0a
AVX 256-bit conversion instructions
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Add the x86 VEX_L form to handle special cases where VEX_L must be set.
llvm-svn: 108274
2010-07-13 21:07:28 +00:00
Bruno Cardoso Lopes
ae37153b05
Add AVX 256-bit packed logical forms
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llvm-svn: 108224
2010-07-13 02:38:35 +00:00
Bruno Cardoso Lopes
495ae629bb
Add AVX 256-bit unop arithmetic instructions
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llvm-svn: 108223
2010-07-13 01:53:31 +00:00
Bruno Cardoso Lopes
852e3bf472
Add AVX 256 binary arithmetic instructions
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llvm-svn: 108207
2010-07-12 23:04:15 +00:00
Bruno Cardoso Lopes
a4889e6f93
Add AVX 256-bit MOVMSK forms
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llvm-svn: 108184
2010-07-12 20:06:32 +00:00
Bruno Cardoso Lopes
f4180a9a7b
Add AVX 256-bit packed MOVNT variants
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llvm-svn: 108021
2010-07-09 21:42:42 +00:00
Bruno Cardoso Lopes
6ca8dc935c
Add AVX 256-bit unpack and interleave
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llvm-svn: 108017
2010-07-09 21:20:35 +00:00
Bruno Cardoso Lopes
3676e24b67
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
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notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
llvm-svn: 107996
2010-07-09 18:27:43 +00:00
Chris Lattner
012d7537ee
Rework segment prefix emission code to handle segments
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in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax
This fixes rdar://8127102. I have several cleanup patches coming
next.
llvm-svn: 107917
2010-07-08 22:28:12 +00:00
Chris Lattner
6a5db9c9c9
Implement the major chunk of PR7195: support for 'callw'
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in the integrated assembler. Still some discussion to be
done.
llvm-svn: 107825
2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes
b92b51191e
Add more assembly opcodes for SSE compare instructions
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llvm-svn: 107823
2010-07-07 22:24:03 +00:00
Bruno Cardoso Lopes
8d350872d4
Add AVX AES instructions
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llvm-svn: 107798
2010-07-07 18:24:20 +00:00
Bruno Cardoso Lopes
6222076cd1
Add AVX SSE4.2 instructions
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llvm-svn: 107752
2010-07-07 03:39:29 +00:00
Bruno Cardoso Lopes
675ebe2dc0
Add AVX SSE4.1 insertps, ptest and movntdqa instructions
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llvm-svn: 107747
2010-07-07 01:14:56 +00:00
Bruno Cardoso Lopes
fa10461265
Add AVX SSE4.1 extractps and pinsr instructions
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llvm-svn: 107746
2010-07-07 01:01:13 +00:00
Bruno Cardoso Lopes
54c2f858b3
Add AVX SSE4.1 Extract Integer instructions
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llvm-svn: 107740
2010-07-07 00:07:24 +00:00
Bruno Cardoso Lopes
b9e1c33054
Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions
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llvm-svn: 107723
2010-07-06 23:15:17 +00:00
Bruno Cardoso Lopes
0c6ec0b068
Add part of AVX SSE4.1 packed move with sign/zero extend instructions
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llvm-svn: 107720
2010-07-06 23:01:41 +00:00
Bruno Cardoso Lopes
a0b37e839c
Add AVX vblendvpd, vblendvps and vpblendvb instructions
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Update VEX encoding to support those new instructions
llvm-svn: 107715
2010-07-06 22:36:24 +00:00
Bruno Cardoso Lopes
dc16024895
Add AVX SSE4.1 blend, mpsadbw and vdp
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llvm-svn: 107560
2010-07-03 01:37:03 +00:00
Bruno Cardoso Lopes
9cbb625579
Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions
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llvm-svn: 107558
2010-07-03 01:15:47 +00:00
Bruno Cardoso Lopes
df02d037e4
Add AVX SSE4.1 Horizontal Minimum and Position instruction
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llvm-svn: 107552
2010-07-03 00:49:21 +00:00
Bruno Cardoso Lopes
e6b70efcb0
Add AVX SSE4.1 round instructions
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llvm-svn: 107549
2010-07-03 00:37:44 +00:00
Bruno Cardoso Lopes
4931e183b5
- Add support for the rest of AVX SSE3 instructions
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- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode
llvm-svn: 107523
2010-07-02 22:06:54 +00:00
Bruno Cardoso Lopes
511e5f47de
Move SSE3 Move patterns to a more appropriate section
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Add AVX SSE3 packed horizontal and & sub instructions
llvm-svn: 107405
2010-07-01 17:35:02 +00:00
Bruno Cardoso Lopes
0a3048e8b9
Add AVX SSE3 packed addsub instructions
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llvm-svn: 107404
2010-07-01 17:08:18 +00:00
Bruno Cardoso Lopes
c1abe91367
Add AVX SSE3 replicate and convert instructions
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llvm-svn: 107375
2010-07-01 02:33:39 +00:00
Bruno Cardoso Lopes
956316a3d7
- Add AVX SSE2 Move doubleword and quadword instructions.
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- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
in the .td file now have a AVX encoded form already working.
llvm-svn: 107365
2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes
f8855c22be
Add AVX SSE2 mask creation and conditional store instructions
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llvm-svn: 107306
2010-06-30 18:38:10 +00:00
Bruno Cardoso Lopes
3c02702830
Add AVX SSE2 packed integer extract/insert instructions
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llvm-svn: 107293
2010-06-30 17:03:03 +00:00
Bruno Cardoso Lopes
39594cc5d0
Add AVX SSE2 integer unpack instructions
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llvm-svn: 107246
2010-06-30 04:06:39 +00:00