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394 Commits

Author SHA1 Message Date
Bob Wilson
d662e8cd02 Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee 
that the high halfword is zero.  The shift need not be exactly 16 bits.

llvm-svn: 111196
 2010-08-16 22:26:55 +00:00
Bob Wilson
985dab611d Rename sat_shift operand to shift_imm, in preparation for using it for other 
instructions besides saturate instructions.  No functional changes.

llvm-svn: 111168
 2010-08-16 18:27:34 +00:00
Bob Wilson
98641e5a51 Remove unused code. 
llvm-svn: 111154
 2010-08-16 17:06:03 +00:00
Johnny Chen
78345b1dfe Cleaned up the for-disassembly-only entries in the arm instruction table so that 
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951
 2010-08-12 20:46:17 +00:00
Johnny Chen
9a37d16281 Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. 
Added two test cases to arm-tests.txt.

llvm-svn: 110880
 2010-08-11 23:35:12 +00:00
Bob Wilson
3582107cf8 Move the ARM SSAT and USAT optional shift amount operand out of the 
instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875
 2010-08-11 23:10:46 +00:00
Evan Cheng
e67c4c3723 Really control isel of barrier instructions with cpu feature. 
llvm-svn: 110787
 2010-08-11 06:36:31 +00:00
Evan Cheng
5fca4ca5f9 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the 
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.

llvm-svn: 110785
 2010-08-11 06:22:01 +00:00
Bill Wendling
735305d4d8 Mark ARM compare instructions as isCompare. 
llvm-svn: 110761
 2010-08-11 00:22:27 +00:00
Bob Wilson
0650cceb38 Add a separate ARM instruction format for Saturate instructions. 
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754
 2010-08-11 00:01:18 +00:00
Bob Wilson
fbce203f20 Fix indentation. 
llvm-svn: 110363
 2010-08-05 19:00:21 +00:00
Bob Wilson
4ba3c0a5e1 Add an ARM RSCrr instruction for disassembly only. 
Partial fix for PR7792.

llvm-svn: 110361
 2010-08-05 18:59:36 +00:00
Bob Wilson
9fbaea3765 Add an ARM RSBrr instruction for disassembly only. 
Partial fix for PR7792.

llvm-svn: 110358
 2010-08-05 18:23:43 +00:00
Bob Wilson
58c8a5da9e Move newlines before inline jumptables from the asm strings in .td files to 
the jtblock_operand print methods.  This avoids extra newlines in the
disassembler's output.  PR7757.

llvm-svn: 109948
 2010-07-31 06:28:10 +00:00
Nate Begeman
0b0f838c32 Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics. 
llvm-svn: 109813
 2010-07-29 22:48:09 +00:00
Nate Begeman
b24fa8b8ae Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions. 
Behave identically to __qadd & __qsub RealView instruction intrinsics.

llvm-svn: 109770
 2010-07-29 17:56:55 +00:00
Jim Grosbach
8764c0127d ARM mode version of r109693. Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138 
llvm-svn: 109696
 2010-07-28 23:25:44 +00:00
Jim Grosbach
749f4fca0a Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction 
and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.

llvm-svn: 108570
 2010-07-16 23:05:05 +00:00
Jim Grosbach
e2d1ecbe70 Improve 64-subtraction of immediates when parts of the immediate can fit 
in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284

llvm-svn: 108339
 2010-07-14 17:45:16 +00:00
Evan Cheng
069f1f7c9a Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. 
llvm-svn: 108258
 2010-07-13 19:27:42 +00:00
Dale Johannesen
2df647f882 Changes to ARM tail calls, mostly cosmetic. 
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851
 2010-07-08 01:18:23 +00:00
Jim Grosbach
bc31f7a24b LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it 
being moved around away from the jump table it references. rdar://8104340

llvm-svn: 106483
 2010-06-21 21:27:27 +00:00
Dale Johannesen
ef3db5dea3 Fix PR 7433. Silly typo in non-Darwin ARM tail call 
handling, plus correct R9 handling in that mode.

llvm-svn: 106434
 2010-06-21 18:21:49 +00:00
Evan Cheng
604fd85b52 Indentation and remove dead code. 
llvm-svn: 106362
 2010-06-19 00:11:54 +00:00
Dale Johannesen
3f9da2755d Fix ARM/Thumb reversal in previous attempt. 
llvm-svn: 106314
 2010-06-18 21:07:47 +00:00
Dale Johannesen
81914dea4e An attempt to fix the problem Anton reported with 
ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.

llvm-svn: 106309
 2010-06-18 20:44:28 +00:00
Dale Johannesen
9f18fc3fa2 Last round of changes for ARM tail calls. 
Not turning them on yet.

llvm-svn: 106295
 2010-06-18 18:13:11 +00:00
Dale Johannesen
f35ca445f6 Add file missing from previous commit. 
llvm-svn: 106058
 2010-06-15 22:24:08 +00:00
Dale Johannesen
891a19d5ae Early implementation of tail call for ARM. 
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.

llvm-svn: 105413
 2010-06-03 21:09:53 +00:00
Jim Grosbach
f3bd81ce11 Clean up 80 column violations. No functional change. 
llvm-svn: 105350
 2010-06-02 21:53:11 +00:00
Jim Grosbach
7dd85bebee correct retattr 
llvm-svn: 104980
 2010-05-28 18:03:48 +00:00
Jim Grosbach
2eb2c2d257 make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n. 
llvm-svn: 104967
 2010-05-28 17:37:40 +00:00
Jim Grosbach
b004e2cf0f Update the saved stack pointer in the sjlj function context following either 
an alloca() or an llvm.stackrestore(). rdar://8031573

llvm-svn: 104900
 2010-05-27 23:49:24 +00:00
Jim Grosbach
bb4860d2a2 Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry in 
ISD::. No functional change.

llvm-svn: 104734
 2010-05-26 20:22:18 +00:00
Jim Grosbach
b6cc69c655 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419
 2010-05-22 01:06:18 +00:00
Evan Cheng
d4118b6c8d Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable. 
llvm-svn: 104114
 2010-05-19 07:26:50 +00:00
Evan Cheng
0aa58d5b69 Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects. 
llvm-svn: 104111
 2010-05-19 06:07:03 +00:00
Evan Cheng
23fb523b44 Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM. 
llvm-svn: 104102
 2010-05-19 01:52:25 +00:00
Anton Korobeynikov
a63555c10d Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td 
llvm-svn: 103903
 2010-05-16 09:15:36 +00:00
Anton Korobeynikov
4f8b48d8c6 "trap" pseudo-op turned out to be apple-local. 
Temporary emit it as raw bytes until it will be added to binutils as well.

llvm-svn: 103878
 2010-05-15 17:19:20 +00:00
Evan Cheng
11130a0a22 Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
llvm-svn: 103459
 2010-05-11 07:26:32 +00:00
Jim Grosbach
e04cc6cb43 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136
 2010-05-05 23:44:43 +00:00
Jim Grosbach
3630aff780 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119
 2010-05-05 20:44:35 +00:00
Johnny Chen
3cc0200f74 Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. Changed 
to the UAL syntax of LDCL<c>, instead.

Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().

llvm-svn: 101527
 2010-04-16 19:33:23 +00:00
Johnny Chen
53225c4582 Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, not 
am2offset.  Modified the instruction table entry and added a new test case.

llvm-svn: 101415
 2010-04-15 23:12:47 +00:00
Bob Wilson
ef934eac9f Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets 
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.

llvm-svn: 100892
 2010-04-09 20:41:18 +00:00
Jim Grosbach
d285f71b9a Make the use of the vmla and vmls VFP instructions controllable via cmd line. 
Preliminary testing shows significant performance wins by not using these
instructions.

llvm-svn: 99436
 2010-03-24 22:31:46 +00:00
Bob Wilson
73d7323c91 Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") 
with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

llvm-svn: 99095
 2010-03-20 22:13:40 +00:00
Johnny Chen
8f2103ae78 Revert r98679. The disassembler will be updated to depend on the existence of 
IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.

llvm-svn: 99013
 2010-03-19 23:50:27 +00:00
Bob Wilson
9501c478f7 Revert this change, since it was causing ARM performance regressions. 
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td

llvm-svn: 99010
 2010-03-19 22:51:32 +00:00