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Commit Graph

91720 Commits

Author SHA1 Message Date
Rafael Espindola
6a1e273872 XFAIL this on ppc64.
It looks like eh uses an unimplemented relocation on pp64

llvm-svn: 181169
2013-05-05 21:04:18 +00:00
Rafael Espindola
4ae75aafcb Port ExceptionDemo to MCJIT.
llvm-svn: 181168
2013-05-05 20:57:58 +00:00
Rafael Espindola
297c5a1e10 Add EH support to the MCJIT.
This gets exception handling working on ELF and Macho (x86-64 at least).
Other than the EH frame registration, this patch also implements support
for GOT relocations which are used to locate the personality function on
MachO.

llvm-svn: 181167
2013-05-05 20:43:10 +00:00
Evan Cheng
2fcdb53946 Test case for r181160 and r181161. rdar://13782395
llvm-svn: 181162
2013-05-05 18:07:15 +00:00
Evan Cheng
4d42f5b1d5 ARM AnalyzeBranch should conservatively return true when it sees a predicated
indirect branch at the end of the BB. Otherwise if-converter, branch folding
pass may incorrectly update its successor info if it consider BB as fallthrough
to the next BB.

rdar://13782395

llvm-svn: 181161
2013-05-05 18:06:32 +00:00
Evan Cheng
2ebed7706f Teach if-converter to avoid removing BBs whose addresses are takne. rdar://13782395
llvm-svn: 181160
2013-05-05 18:03:49 +00:00
Benjamin Kramer
06f30fc527 LoopVectorize: Print values instead of pointers in debug output.
llvm-svn: 181157
2013-05-05 14:54:52 +00:00
Richard Osborne
1c4909b705 [docs] Update Target Feature Matrix for the XCore backend.
Disassembler support has recently been added. Fill in some other unknowns
at the same time.

llvm-svn: 181156
2013-05-05 14:09:55 +00:00
Richard Osborne
816f899c45 [XCore] Add LDAPB instructions.
With the change the disassembler now supports the XCore ISA in its
entirety.

llvm-svn: 181155
2013-05-05 13:36:53 +00:00
Richard Osborne
f5ff5a7e6f [XCore] Update LDAP to use pcrel_imm.
llvm-svn: 181154
2013-05-05 13:33:10 +00:00
Richard Osborne
0777489aca [XCore] Rename calltarget -> pcrel_imm.
No functionality change.

llvm-svn: 181153
2013-05-05 13:29:02 +00:00
Richard Osborne
6600501755 [XCore] Add BLRB instructions.
llvm-svn: 181152
2013-05-05 13:24:16 +00:00
Richard Osborne
4a26a37a60 [XCore] Remove '-' from back branch asm syntax.
Instead operands are treated as negative immediates
where the sign bit is implicit in the instruction
encoding.

llvm-svn: 181151
2013-05-05 13:20:22 +00:00
Benjamin Kramer
ba8759510f InlineSpiller: Remove quadratic behavior.
No functionality change.

llvm-svn: 181149
2013-05-05 11:29:14 +00:00
Stepan Dyatkovskiy
c06cd03f6e For ARM backend, fixed "byval" attribute support.
Now even the small structures could be passed within byval (small enough
to be stored in GPRs).
In regression tests next function prototypes are checked:

PR15293:
  %artz = type { i32 }
  define void @foo(%artz* byval %s)
  define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2)
foo: "s" stored in R0
foo2: "s" stored in R0, "s2" stored in R2.

Next AAPCS rules are checked:
5.5 Parameters Passing, C.4 and C.5,
"ParamSize" is parameter size in 32bit words:
-- NSAA != 0, NCRN < R4 and NCRN+ParamSize > R4.
   Parameter should be sent to the stack; NCRN := R4.
-- NSAA != 0, and NCRN < R4, NCRN+ParamSize < R4.
   Parameter stored in GPRs; NCRN += ParamSize.

llvm-svn: 181148
2013-05-05 07:48:36 +00:00
Arnold Schwaighofer
64ae7f79b0 Add missing PatternMatch.cpp to CMakeLists.txt
llvm-svn: 181147
2013-05-05 02:14:28 +00:00
Arnold Schwaighofer
804d6f0d4b PatternMatch: Fix documentation - 'function' not 'attribute'
llvm-svn: 181146
2013-05-05 02:01:41 +00:00
David Majnemer
d5ba4da281 Remove a recently redundant transform from X86ISelLowering.
X86ISelLowering has support to treat:
(icmp ne (and (xor %flags, -1), (shl 1, flag)), 0)

as if it were actually:
(icmp eq (and %flags, (shl 1, flag)), 0)

However, r179386 has code at the InstCombine level to handle this.

llvm-svn: 181145
2013-05-05 02:00:10 +00:00
Arnold Schwaighofer
0a0d84c7b7 LoopVectorize: Add support for floating point min/max reductions
Add support for min/max reductions when "no-nans-float-math" is enabled. This
allows us to assume we have ordered floating point math and treat ordered and
unordered predicates equally.

radar://13723044

llvm-svn: 181144
2013-05-05 01:54:48 +00:00
Arnold Schwaighofer
83cedfffb0 PatternMatch: Matcher for (un)ordered floating point min/max
Add support for matching 'ordered' and 'unordered' floating point min/max
constructs.

In LLVM we can express min/max functions as a combination of compare and select.
We have support for matching such constructs for integers but not for floating
point. In floating point math there is no total order because of the presence of
'NaN'. Therefore, we have to be careful to preserve the original fcmp semantics
when interpreting floating point compare select combinations as a minimum or
maximum function. The resulting 'ordered/unordered' floating point maximum
function has to select the same value as the select/fcmp combination it is based
on.

 ordered_max(x,y)   = max(x,y) iff x and y are not NaN, y otherwise
 unordered_max(x,y) = max(x,y) iff x and y are not NaN, x otherwise
 ordered_min(x,y)   = min(x,y) iff x and y are not NaN, y otherwise
 unordered_min(x,y) = min(x,y) iff x and y are not NaN, x otherwise

This matches the behavior of the underlying select(fcmp(olt/ult/.., L, R), L, R)
construct.

Any code using this predicate has to preserve this semantics.

A follow-up patch will use this to implement floating point min/max reductions
in the vectorizer.

radar://13723044

llvm-svn: 181143
2013-05-05 01:54:46 +00:00
Arnold Schwaighofer
0791ec5e44 LoopVectorizer: Cleanup of miminimum/maximum pattern match code
No need for setting the operands. The pointers are going to be bound by the
matcher.

radar://13723044

llvm-svn: 181142
2013-05-05 01:54:44 +00:00
Arnold Schwaighofer
0158aa58f2 LoopVectorize: We don't need an identity element for min/max reductions
We can just use the initial element that feeds the reduction.

  max(max(x, y), z) == max(max(x,y), max(x,z))

radar://13723044

llvm-svn: 181141
2013-05-05 01:54:42 +00:00
Dmitri Gribenko
82c92dc3dd Add ArrayRef constructor from None, and do the cleanups that this constructor enables
Patch by Robert Wilhelm.

llvm-svn: 181138
2013-05-05 00:40:33 +00:00
Nadav Rotem
8c293c00fc whitespace
llvm-svn: 181137
2013-05-04 23:27:32 +00:00
Nadav Rotem
1330c4432b Fix an odd comment.
llvm-svn: 181136
2013-05-04 23:24:56 +00:00
Tim Northover
390335941f AArch64: enable MCJIT and tests now that everything passes.
This removes dire warnings about AArch64 being unsupported and enables
the tests when appropriate on this platform.

llvm-svn: 181135
2013-05-04 20:14:22 +00:00
Tim Northover
1394ed35df AArch64: implement 64-bit absolute relocation in MCJIT
This is about the simplest relocation, but surprisingly rare in actual
code.

It occurs in (for example) the MCJIT test test-ptr-reloc.ll.

llvm-svn: 181134
2013-05-04 20:14:14 +00:00
Tim Northover
41e94642a9 AArch64: add stubs to support long function calls on MCJIT
As with global accesses, external functions could exist anywhere in
memory. Therefore the stub must create a complete 64-bit address. This
patch implements the fragment as (roughly):
    movz x16, #:abs_g3:somefunc
    movk x16, #:abs_g2_nc:somefunc
    movk x16, #:abs_g1_nc:somefunc
    movk x16, #:abs_g0_nc:somefunc
    br x16

In principle we could save 4 bytes by using a literal-load instead,
but it is unclear that would be more efficient and can only be tested
when real hardware is readily available.

This allows (for example) the MCJIT test 2003-05-07-ArgumentTest to
pass on AArch64.

llvm-svn: 181133
2013-05-04 20:14:09 +00:00
Tim Northover
71cd109478 AArch64: implement relocations for global access
The large memory model (default and main viable for JIT) emits
addresses in need of relocation as
    movz x0, #:abs_g3:somewhere
    movk x0, #:abs_g2_nc:somewhere
    movk x0, #:abs_g1_nc:somewhere
    movk x0, #:abs_g0_nc:somewhere

To support this we must implement those four relocations in the
dynamic loader.

This allows (for example) the test-global.ll MCJIT test to pass on
AArch64.

llvm-svn: 181132
2013-05-04 20:14:04 +00:00
Tim Northover
7f0690a028 AArch64: implement first relocation required for MCJIT
R_AARCH64_PCREL32 is present in even trivial .eh_frame sections and so
is required to compile any function without the "nounwind" attribute.

This change implements very basic infrastructure in the RuntimeDyldELF
file and allows (for example) the test-shift.ll MCJIT test to pass
on AArch64.

llvm-svn: 181131
2013-05-04 20:13:59 +00:00
Tim Northover
33a7a57446 Build system changes to enable MCJIT on AArch64
These changes just allow AArch64 to take part in the MCJIT world when
built correctly.

llvm-svn: 181130
2013-05-04 20:13:52 +00:00
Tim Northover
712fae0bf2 AArch64: use __clear_cache under GCCish environments
AArch64 is going to need some kind of cache-invalidation in order to
successfully JIT since it has a weak memory-model. This is provided by
a __clear_cache builtin in libgcc, which acts very much like the
32-bit ARM equivalent (on platforms where it exists).

llvm-svn: 181129
2013-05-04 18:52:44 +00:00
Richard Osborne
49987866b1 Fix buildbot failure on 64 bit linux due to std::max() having different
operand types.

llvm-svn: 181128
2013-05-04 17:41:01 +00:00
Richard Osborne
0eea664ede [XCore] Remove unused operand type.
llvm-svn: 181127
2013-05-04 17:30:05 +00:00
Richard Osborne
9a767b4821 [XCore] Make use of the target independent global address offset folding.
This let us to remove some custom code that matched constant offsets
from globals at instruction selection time as a special addressing mode.
No intended functionality change.

llvm-svn: 181126
2013-05-04 17:24:33 +00:00
Richard Osborne
2935de3971 [XCore] Simplify code that checks for an aligned base plus a constant.
The code now makes use of ComputeMaskedBits,
SelectionDAG::isBaseWithConstantOffset and TargetLowering::isGAPlusOffset
where appropriate reducing the amount of logic needed in XCoreISelLowering.
No intended functionality change.

llvm-svn: 181125
2013-05-04 17:17:10 +00:00
Richard Osborne
22dc54e15d [XCore] Move lowering of thread local storage to a separate pass.
Thread local storage is not supported by the XMOS linker so we handle
thread local variables by lowering the variable to an array of n elements
(where n is the number of hardware threads per core, currently 8
for all XMOS devices) indexed by the the current thread ID.

Previously this lowering was spread across the XCoreISelLowering and the
XCoreAsmPrinter classes. Moving this to a separate pass should be much
cleaner.

llvm-svn: 181124
2013-05-04 17:01:55 +00:00
Tim Northover
9422845262 AArch64: assert code model is small for TLS accesses
Supporting TLS in the large memory model is rather difficult at the
moment, so make sure no-one gets into difficulties by mistake.

llvm-svn: 181121
2013-05-04 16:54:11 +00:00
Tim Northover
d4f2cac7b6 AArch64: support literal pool access in large memory model.
llvm-svn: 181120
2013-05-04 16:54:07 +00:00
Tim Northover
4ef2500d01 AArch64: support large code model for jump-tables
llvm-svn: 181119
2013-05-04 16:54:00 +00:00
Tim Northover
ece66eacb2 AArch64: implement support for blockaddress in large code model
llvm-svn: 181118
2013-05-04 16:53:53 +00:00
Tim Northover
87645e02c0 AArch64: implement large code model access to global variables.
The MOVZ/MOVK instruction sequence may not be the most efficient (a
literal-pool load could be better) but adding that would require
reinstating the ConstantIslands pass.

For now the sequence is correct, and that's enough. Beware, as of
commit GNU ld does not appear to support the relocations needed for
this. Its primary purpose (for now) will be to support JITed code,
since in that case there is no guarantee of where your code will end
up in memory relative to external symbols it references.

llvm-svn: 181117
2013-05-04 16:53:46 +00:00
Richard Osborne
cb8c7c4310 [XCore] Use static relocation model by default.
This allows us to get get rid of a hack in XCoreTargetObjectFile where the
the DataRel* sections were overridden.

llvm-svn: 181116
2013-05-04 16:40:58 +00:00
Tim Northover
f5d9c9ba13 Allow host triple to be correctly overridden in CMake builds
The intended semantics mirror autoconf, where the user is able to
specify a host triple, but if it's left to the build system then
"config.guess" is invoked for the default.

This also renames the LLVM_HOSTTRIPLE define to LLVM_HOST_TRIPLE to
fit in with the style of the surrounding defines.

llvm-svn: 181112
2013-05-04 07:36:23 +00:00
Rafael Espindola
132e6767ff Optimize llvm-link too.
This takes the linking of almost all modules in a clang build from 6:32
to 0:19.

llvm-svn: 181105
2013-05-04 05:30:49 +00:00
Rafael Espindola
f14bf5454c Fix a performance bug in the Linker.
Now that we hava a convinient place to keep it, remeber the set of
identified structs as we merge modules.

This speeds up the linking of all the bitcode files in clang with the
gold plugin and -plugin-opt=emit-llvm (i.e., link only, no codegen) from
5:25 minutes to 13.6 seconds!

Patch by Xiaofei Wan!

llvm-svn: 181104
2013-05-04 05:05:18 +00:00
Rafael Espindola
f41d17e3f1 Implement Linker::LinkModules with Linker::linkInModule.
Flipping which one is the implementation will let us optimize linkInModule.

llvm-svn: 181102
2013-05-04 04:08:02 +00:00
Rafael Espindola
02f1d2a259 Now that Linker.cpp is almost empty, merge it into LinkModules.cpp.
Also remove unused includes.

llvm-svn: 181100
2013-05-04 03:48:37 +00:00
Rafael Espindola
9167321551 Last batch of cleanups to Linker.h.
Update comments, fix * placement, fix method names that are not
used in clang, add a linkInModule that takes a Mode and put it
in Linker.cpp.

llvm-svn: 181099
2013-05-04 03:06:50 +00:00
Rafael Espindola
139524848e Don't construct or delete a module on the Linker.
The linker is now responsible only for actually linking the modules, it
is up to the clients to create and destroy them.

llvm-svn: 181098
2013-05-04 02:43:00 +00:00