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Commit Graph

92119 Commits

Author SHA1 Message Date
Bob Wilson
d5833c69b3 Temporarily disable this test because it is failing when using libc++.
llvm-svn: 182212
2013-05-19 14:59:08 +00:00
Benjamin Kramer
8dd0ad9a55 Move the remaining simplify-libcalls tests to instcombine, merging most of them into a single file.
llvm-svn: 182211
2013-05-19 13:28:39 +00:00
Tim Northover
74519947c0 Print uint64_t -debug text correctly on 32-bit hosts
On 32-bit hosts %p can print garbage when given a uint64_t, we should
use %llx instead. This only affects the output of the debugging text
produced by lli.

llvm-svn: 182209
2013-05-19 09:55:06 +00:00
Renato Golin
f18adf5786 Unsupported remote JIT on ARM
llvm-svn: 182201
2013-05-18 19:42:07 +00:00
David Majnemer
6ffd698570 isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also.
This is useful if something that looks like (x & (1 << y)) ? 64 : 32 is
the divisor in a modulo operation.

llvm-svn: 182200
2013-05-18 19:30:37 +00:00
Arnold Schwaighofer
4a2fd393c6 LoopVectorize: Handle single edge PHIs
We might encouter single edge PHIs - handle them with an identity select.

Fixes PR15990.

llvm-svn: 182199
2013-05-18 18:38:34 +00:00
Dmitri Gribenko
fdcdaef7d6 docs/Passes: fix some typos
Patch by Yacine Belkadi.

llvm-svn: 182197
2013-05-18 18:01:44 +00:00
Benjamin Kramer
08711da7a1 Add basic support for ELF32-ppc relocations to llvm-dwarfdump.
Should help the ppc32 buildbot.

llvm-svn: 182194
2013-05-18 16:00:35 +00:00
Hal Finkel
d4eb9291fa Check InlineAsm clobbers in PPCCTRLoops
We don't need to reject all inline asm as using the counter register (most does
not). Only those that explicitly clobber the counter register need to prevent
the transformation.

llvm-svn: 182191
2013-05-18 09:20:39 +00:00
Tim Northover
5256d08973 AArch64: add CMake dependency to fix very parallel builds
llvm-svn: 182190
2013-05-18 08:17:47 +00:00
David Majnemer
a21386b571 X86: Bad peephole interaction between adc, MOV32r0
The peephole tries to reorder MOV32r0 instructions such that they are
before the instruction that modifies EFLAGS.

The problem is that the peephole does not consider the case where the
instruction that modifies EFLAGS also depends on the previous state of
EFLAGS.

Instead, walk backwards until we find an instruction that has a def for
EFLAGS but does not have a use.
If we find such an instruction, insert the MOV32r0 before it.
If it cannot find such an instruction, skip the optimization.

llvm-svn: 182184
2013-05-18 01:02:03 +00:00
Matt Arsenault
03de9d102f Remove duplicated comment
The same comment is already made in the header

llvm-svn: 182181
2013-05-18 00:24:09 +00:00
Matt Arsenault
118196f0ca Add LLVMContext argument to getSetCCResultType
llvm-svn: 182180
2013-05-18 00:21:46 +00:00
JF Bastien
cbcaf8db77 Support unaligned load/store on more ARM targets
This patch matches GCC behavior: the code used to only allow unaligned
load/store on ARM for v6+ Darwin, it will now allow unaligned load/store
for v6+ Darwin as well as for v7+ on Linux and NaCl.

The distinction is made because v6 doesn't guarantee support (but LLVM
assumes that Apple controls hardware+kernel and therefore have
conformant v6 CPUs), whereas v7 does provide this guarantee (and
Linux/NaCl behave sanely).

The patch keeps the -arm-strict-align command line option, and adds
-arm-no-strict-align. They behave similarly to GCC's -mstrict-align and
-mnostrict-align.

I originally encountered this discrepancy in FastIsel tests which expect
unaligned load/store generation. Overall this should slightly improve
performance in most cases because of reduced I$ pressure.

llvm-svn: 182175
2013-05-17 23:49:01 +00:00
Rafael Espindola
89d64471a3 Fix the configure build.
llvm-svn: 182172
2013-05-17 23:20:58 +00:00
Rafael Espindola
c0de1ee01b Convert obj2yaml to use yamlio.
llvm-svn: 182169
2013-05-17 22:58:42 +00:00
Rafael Espindola
aabd77b198 Fix the build in c++11 mode.
The errors were:

non-constant-expression cannot be narrowed from type 'int64_t' (aka 'long') to 'uint32_t' (aka 'unsigned int') in initializer list

and

non-constant-expression cannot be narrowed from type 'long' to 'uint32_t' (aka 'unsigned int') in initializer list

llvm-svn: 182168
2013-05-17 22:45:52 +00:00
Matt Arsenault
0b9ab072e4 Replace redundant code
Use EVT::changeExtendedVectorElementTypeToInteger instead of doing the
same thing that it does

llvm-svn: 182165
2013-05-17 21:43:43 +00:00
Matt Arsenault
7a573d2632 Add missing -*- C++ -*- to headers
llvm-svn: 182164
2013-05-17 21:43:39 +00:00
Derek Schuff
15609ee438 Add missing verb to comment in PassNameParser.h
Patch by Mark Seaborn.

llvm-svn: 182131
2013-05-17 16:51:32 +00:00
Vincent Lejeune
c8aad4509a R600: Lower int_load_input to copyFromReg instead of Register node
It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.

llvm-svn: 182130
2013-05-17 16:51:06 +00:00
Vincent Lejeune
5a2e018ab6 R600: Use bottom up scheduling algorithm
llvm-svn: 182129
2013-05-17 16:50:56 +00:00
Vincent Lejeune
2bf65b1826 R600: Use depth first scheduling algorithm
It should increase PV substitution opportunities and lower gpr
usage (pending computations path are "flushed" sooner)

llvm-svn: 182128
2013-05-17 16:50:44 +00:00
Vincent Lejeune
a140216a0a R600: Replace big texture opcode switch in scheduler by usesTC/usesVC
llvm-svn: 182127
2013-05-17 16:50:37 +00:00
Vincent Lejeune
152473c61c R600: Relax some vector constraints on Dot4.
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.

llvm-svn: 182126
2013-05-17 16:50:32 +00:00
Vincent Lejeune
0c663b698a R600: Improve texture handling
llvm-svn: 182125
2013-05-17 16:50:20 +00:00
Vincent Lejeune
b57cb76b6d R600: Rename 128 bit registers.
Almost all instructions that takes a 128 bits reg as input (fetch, export...)
have the abilities to swizzle their argument and output. Instead of printing
default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
print potentially optimized swizzles themselves.

llvm-svn: 182124
2013-05-17 16:50:09 +00:00
Vincent Lejeune
d391d51989 R600: Some factorization
llvm-svn: 182123
2013-05-17 16:50:02 +00:00
Vincent Lejeune
bf991c018d R600: Factorize Fetch size limit inside AMDGPUSubTarget
llvm-svn: 182122
2013-05-17 16:49:55 +00:00
Vincent Lejeune
d39a89783b R600: prettier dump of clamp
llvm-svn: 182121
2013-05-17 16:49:49 +00:00
Tom Stellard
a4cc081e08 R600: Fix encoding for R600 family GPUs
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64193
https://bugs.freedesktop.org/show_bug.cgi?id=64257
https://bugs.freedesktop.org/show_bug.cgi?id=64320

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 182113
2013-05-17 15:23:21 +00:00
Tom Stellard
b91da0601d R600: Pass MCSubtargetInfo reference to R600CodeEmitter
llvm-svn: 182112
2013-05-17 15:23:12 +00:00
Venkatraman Govindaraju
989fb74a1c [Sparc] Implements hasReservedCallFrame and hasFP.
This is to generate correct framesetup code when the function
 has variable sized allocas.

llvm-svn: 182108
2013-05-17 15:14:34 +00:00
Benjamin Kramer
e9efb3252f X86: Make shuffle -> shift conversion more aggressive about undefs.
Shuffles that only move an element into position 0 of the vector are common in
the output of the loop vectorizer and often generate suboptimal code when SSSE3
is not available. Lower them to vector shifts if possible.

We still prefer palignr over psrldq because it has higher throughput on
sandybridge.

llvm-svn: 182102
2013-05-17 14:48:34 +00:00
Benjamin Kramer
d1f1dddf9f FileCheckize test.
llvm-svn: 182101
2013-05-17 14:48:25 +00:00
Benjamin Kramer
c08526696f LoopVectorize: Simplify code. No functionality change.
llvm-svn: 182100
2013-05-17 14:48:17 +00:00
David Tweed
83379493c4 r182085 introduced a change that triggered an assertion on ARM. This is an immediate fix
which doesn't resolve the deeper problem.

llvm-svn: 182098
2013-05-17 14:31:59 +00:00
Ulrich Weigand
e299bf2813 [PowerPC] Fix hi/lo encoding in old-style code emitter
This patch implements the equivalent change to r182091/r182092
in the old-style code emitter.  Instead of having two separate
16-bit immediate encoding routines depending on the instruction,
this patch introduces a single encoder that checks the machine
operand flags to decide whether the low or high half of a
symbol address is required.

Since now both encoders make no further distinction between
"symbolLo" and "symbolHi", the .td operand can now use a
single getS16ImmEncoding method.

Tested by running the old-style JIT tests on 32-bit Linux.

llvm-svn: 182097
2013-05-17 14:14:12 +00:00
Ulrich Weigand
24cfcf8f49 [PowerPC] Merge/rename PPC fixup types
Now that fixup_ppc_ha16 and fixup_ppc_lo16 are being treated exactly
the same everywhere, it no longer makes sense to have two fixup types.

This patch merges them both into a single type fixup_ppc_half16,
and renames fixup_ppc_lo16_ds to fixup_ppc_half16ds for consistency.
(The half16 and half16ds names are taken from the description of
relocation types in the PowerPC ABI.)

No change in code generation expected.

llvm-svn: 182092
2013-05-17 12:37:21 +00:00
Ulrich Weigand
89ebba5af6 [PowerPC] Fix processing of ha16/lo16 fixups
The current PowerPC MC back end distinguishes between fixup_ppc_ha16
and fixup_ppc_lo16, which are determined by the instruction the fixup
applies to, and uses this distinction to decide whether a fixup ought
to resolve to the high or the low part of a symbol address.

This isn't quite correct, however.  It is valid -if unusual- assembler
to use, e.g.
  li 1, symbol@ha
or
  lis 1, symbol@l
Whether the high or the low part of the address is used depends solely
on the @ suffix, not on the instruction.

In addition, both
  li 1, symbol
and
  lis 1, symbol
are valid, assuming the symbol address fits into 16 bits; again, both
will then refer to the actual symbol value (so li will load the value
itself, while lis will load the value shifted by 16).


To fix this, two places need to be adapted.  If the fixup cannot be
resolved at assembler time, a relocation needs to be emitted via
PPCELFObjectWriter::getRelocType.  This routine already looks at
the VK_ type to determine the relocation.  The only problem is that
will reject any _LO modifier in a ha16 fixup and vice versa.  This
is simply incorrect; any of those modifiers ought to be accepted
for either fixup type.

If the fixup *can* be resolved at assembler time, adjustFixupValue
currently selects the high bits of the symbol value if the fixup
type is ha16.  Again, this is incorrect; see the above example
  lis 1, symbol

Now, in theory we'd have to respect a VK_ modifier here.  However,
in fact common code never even attempts to resolve symbol references
using any nontrivial VK_ modifier at assembler time; it will always
fall back to emitting a reloc and letting the linker handle it.

If this ever changes, presumably there'd have to be a target callback
to resolve VK_ modifiers.  We'd then have to handle @ha etc. there.

llvm-svn: 182091
2013-05-17 12:36:29 +00:00
Sylvestre Ledru
051e77feb2 Fix a typo (ouput => output)
llvm-svn: 182090
2013-05-17 12:31:43 +00:00
Benjamin Kramer
5781bb221a Don't cast away constness.
llvm-svn: 182086
2013-05-17 11:39:41 +00:00
David Tweed
ccbb603f31 Minor changes to the MCJITTest unittests to use the correct API for finalizing
the JIT object (including XFAIL an ARM test that now needs fixing). Also renames
internal function for consistency.

llvm-svn: 182085
2013-05-17 10:01:46 +00:00
Christian Konig
34f0d6eaf2 R600/SI: return undef instead of null for skipped arguments
This is a candidate for the stable branch.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=64694

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182084
2013-05-17 09:46:48 +00:00
Venkatraman Govindaraju
62af2fad30 [Sparc] Prevent instructions that defines or uses %o7 to be in call's delay slot.
llvm-svn: 182063
2013-05-16 23:53:29 +00:00
Adrian Prantl
b4cf77f945 Generate debug info for by-value struct args even if they are not used.
radar://problem/13865940

llvm-svn: 182062
2013-05-16 23:44:12 +00:00
Ahmed Bougacha
92a36ededf llvm-objdump: Initialize MCDisassembler once instead of for each section.
llvm-svn: 182054
2013-05-16 21:28:23 +00:00
Akira Hatanaka
3848727973 [mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).
Previously, three instructions were needed:

trunc.w.s $f0, $f2
mfc1 $4, $f0
sw $4, 0($2)

Now we need only two:

trunc.w.s $f0, $f2
swc1 $f0, 0($2)

llvm-svn: 182053
2013-05-16 21:17:15 +00:00
Rafael Espindola
21effc7220 Remove addFrameMove.
Now that we have good testing, remove addFrameMove and create cfi
instructions directly.

llvm-svn: 182052
2013-05-16 21:02:15 +00:00
Rafael Espindola
1a64a52101 More test coverage for addFrameMove.
llvm-svn: 182051
2013-05-16 20:50:56 +00:00