1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 03:23:01 +02:00
Commit Graph

19539 Commits

Author SHA1 Message Date
Jim Grosbach
6a932d6ad1 ARM VTBL (one register) assembly parsing and encoding.
llvm-svn: 142441
2011-10-18 23:02:30 +00:00
Bill Wendling
da2d6a83c8 Use the integer compare when the value is small enough. Use the "move into a
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142440
2011-10-18 22:52:20 +00:00
Eric Christopher
4046de9d18 Turn on the vzeroupper pass by default.
I'll remove/rename the option in a few days.

llvm-svn: 142439
2011-10-18 22:50:17 +00:00
Bill Wendling
f200722cbc Use the integer compare when the value is small enough. Use the "move into a
register and then compare against that" method when it's too large. We have to
move the value into the register in the "movw, movt" pair of instructions.

llvm-svn: 142437
2011-10-18 22:49:07 +00:00
Lang Hames
ccf186dd30 Teach fast isel about vector stores, and make DoSelectCall return false when it fails to emit a store. This fixes <rdar://problem/10215997>.
llvm-svn: 142432
2011-10-18 22:11:33 +00:00
Bill Wendling
6900914506 The value we're comparing against may be too large for the ARM CMP
instruction. Move the value into a register and then use that for the CMP.
<rdar://problem/10305266>

llvm-svn: 142431
2011-10-18 22:11:18 +00:00
Bill Wendling
198609713e The immediate may be too large for the CMP instruction. Move it into a register
and use that in the CMP.
<rdar://problem/10305266>

llvm-svn: 142429
2011-10-18 21:55:58 +00:00
Jim Grosbach
d748cf251f Yet more ARM NEON assembly parsing for the lane index operand.
llvm-svn: 142416
2011-10-18 20:21:17 +00:00
Jim Grosbach
ff8c26a53f ARM vmla/vmls assembly parsing for the lane index operand.
llvm-svn: 142413
2011-10-18 20:14:56 +00:00
Jim Grosbach
ed5cb526e2 ARM vmov assembly parsing for the lane index operand.
llvm-svn: 142412
2011-10-18 20:10:47 +00:00
Andrew Trick
1b84db85e7 Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.
Clean up the patterns, fix comments, and avoid confusing both tools
and coders. Note that the special adds/subs SelectionDAG nodes no
longer have the dummy cc_out operand.

llvm-svn: 142397
2011-10-18 19:18:52 +00:00
Bob Wilson
bb191a9fef Use isIntN and isUIntN to check for valid signed/unsigned numbers.
llvm-svn: 142395
2011-10-18 18:46:49 +00:00
Andrew Trick
5e61a8e533 whitespace
llvm-svn: 142394
2011-10-18 18:40:53 +00:00
Bill Wendling
92050387bb A landing pad could have more than one predecessor. In that case, we want that
predecessor to remove the jump to it as well. Delay clearing the 'landing pad'
flag until after the jumps have been removed. (There is an implicit assumption
in several modules that an MBB which jumps to a landing pad has only two
successors.)
<rdar://problem/10304224>

llvm-svn: 142390
2011-10-18 18:30:49 +00:00
Jim Grosbach
988b8dd4ce ARM vmla/vmls assembly parsing for the lane index operand.
llvm-svn: 142389
2011-10-18 18:27:07 +00:00
Jim Grosbach
2752e0b869 ARM vqdmulh assembly parsing for the lane index operand.
llvm-svn: 142386
2011-10-18 18:12:09 +00:00
Jim Grosbach
b56577b650 ARM vmul assembly parsing for the lane index operand.
llvm-svn: 142381
2011-10-18 18:01:52 +00:00
Bruno Cardoso Lopes
edc2e30d42 Final patch that completes old JIT support for Mips:
-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378
2011-10-18 17:50:36 +00:00
Bob Wilson
f78f688c02 Fix incorrect check for sign-extended constant BUILD_VECTOR.
<rdar://problem/10298332>

llvm-svn: 142371
2011-10-18 17:34:51 +00:00
Jim Grosbach
4a138cb8d9 ARM vqdmlal assembly parsing for the lane index operand.
llvm-svn: 142365
2011-10-18 17:16:30 +00:00
Jim Grosbach
5cc37c406d Thumb2 parsing of 'mov.w' gets the cc_out operand wrong. Add an alias for it.
llvm-svn: 142363
2011-10-18 17:09:35 +00:00
Jim Grosbach
031bb99231 ARM assembly parsing and encoding for VMOV.i64.
llvm-svn: 142356
2011-10-18 16:18:11 +00:00
Justin Holewinski
361b3c9ff2 PTX: Fix disabling of MAD instruction selection
llvm-svn: 142352
2011-10-18 13:39:20 +00:00
Duncan Sands
2faab7dd2a Fix a bunch of unused variable warnings when doing a release
build with gcc-4.6.

llvm-svn: 142350
2011-10-18 12:44:00 +00:00
Bill Wendling
aea682a6fe Coding style cleanups. No functionality change.
llvm-svn: 142341
2011-10-18 07:40:22 +00:00
David Meyer
c50cb2f15a Remove NaClMode
llvm-svn: 142338
2011-10-18 05:29:23 +00:00
Chad Rosier
eb469f466b Add support for dynamic stack realignment when in thumb1 mode.
rdar://10288916

llvm-svn: 142337
2011-10-18 05:28:00 +00:00
Joe Abbey
cebf5dc822 Commit test, capitalizing store... keep it simple.
llvm-svn: 142336
2011-10-18 04:44:36 +00:00
Eli Friedman
f43710f4a8 Fix misc warnings. Patch by Joe Abbey.
llvm-svn: 142332
2011-10-18 03:17:34 +00:00
Lang Hames
dfb145da26 Backing out patch. Will refactor to remove the AsmParser dependency on Target.
llvm-svn: 142323
2011-10-18 00:23:49 +00:00
Jim Grosbach
bcfb4ed53c ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
llvm-svn: 142321
2011-10-18 00:22:00 +00:00
Lang Hames
4370882b22 Re-applying the target data layout verification patch from r142288, plus appropriate CMake dependencies.
Thanks to Raphael Espindola for tracking down the CMake issues.

llvm-svn: 142306
2011-10-17 23:24:48 +00:00
Jim Grosbach
1e994e76a7 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
llvm-svn: 142303
2011-10-17 23:09:09 +00:00
Nick Lewycky
c551c1c5f9 Add support for a new extension to the .file directive:
.file filenumber "directory" "filename"

This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.

llvm-svn: 142300
2011-10-17 23:05:28 +00:00
Chad Rosier
ef5ee1892c Add a few FIXME comments.
llvm-svn: 142299
2011-10-17 22:54:23 +00:00
Jim Grosbach
8e9ca16af6 Tidy up.
llvm-svn: 142297
2011-10-17 22:41:42 +00:00
Rafael Espindola
a40b412c70 142288 broke the build:
Linking CXX executable ../../bin/llvm-as
../../lib/libLLVMAsmParser.a(LLParser.cpp.o):/home/espindola/llvm/llvm/lib/AsmParser/LLParser.cpp:function llvm::LLParser::ParseTargetDefinition(): error: undefined reference to 'llvm::TargetData::parseSpecifier(llvm::StringRef, llvm::TargetData*)'
clang-3: error: linker command failed with exit code 1 (use -v to see invocation)

Revert "Validate target data layout strings."

This reverts commit 599d2d4c25d3aee63a21d9c67a88cd43bd971b7e.

llvm-svn: 142296
2011-10-17 22:37:51 +00:00
Bill Wendling
8390d96c1a Now Igor, throw the switch...give my creation life!
Use the custom inserter for the ARM setjmp intrinsics. Instead of creating the
SjLj dispatch table in IR, where it frequently violates serveral assumptions --
in particular assumptions made by the landingpad instruction about what can
branch to a landing pad and what cannot. Performing this in the back-end allows
us to violate these assumptions without the IR getting angry at us.

It also allows us to perform a small optimization. We can shove the address of
the dispatch's basic block into the function context and not have to add code
around the setjmp to check for the return value and jump to the dispatch.

Neat, huh?
<rdar://problem/10116753>

llvm-svn: 142294
2011-10-17 22:26:23 +00:00
Jim Grosbach
f3d495fbbd ARM NEON "vmov.i8" immediate assembly parsing and encoding.
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.

llvm-svn: 142293
2011-10-17 22:26:03 +00:00
Lang Hames
416d4f3f36 Validate target data layout strings.
Invalid strings in asm files will result in parse errors. Invalid string literals passed to TargetData constructors will result in an assertion.

llvm-svn: 142288
2011-10-17 22:05:34 +00:00
Benjamin Kramer
bc2d3cbf7e Use a SmallVector for intrinsic argument types.
llvm-svn: 142259
2011-10-17 21:33:26 +00:00
Bill Wendling
8f01b6c71d Don't renumber the blocks here. This could cause problems later on if another
pass renumbers the blocks again.

llvm-svn: 142258
2011-10-17 21:32:56 +00:00
Cameron Zwarich
4f62e0c1e3 Pseudoinstructions should not be less constrained than the instruction they are
lowered to. This fixes a lot of verifier failures on the test suite.

llvm-svn: 142254
2011-10-17 21:20:13 +00:00
Jim Grosbach
eeb05f7532 Tidy up organization.
llvm-svn: 142248
2011-10-17 21:00:11 +00:00
Bill Wendling
5d4f239d0a Add a call to EmitSjLjDispatchBlock.
Once the intrinsics are marked as having a custom inserter, it will call this
method to emit the dispatch table into the machine function.

llvm-svn: 142245
2011-10-17 20:37:20 +00:00
Jim Grosbach
22167dc73c Fix improperly formed assert() call.
llvm-svn: 142239
2011-10-17 20:22:59 +00:00
Akira Hatanaka
4939842b5a Add definitions of conditional moves with 64-bit operands. Comment out code for
expanding conditional moves, which is not needed since architectures that lack
support for conditional moves have been removed. 

llvm-svn: 142226
2011-10-17 18:53:29 +00:00
Hal Finkel
f61af0e4b0 Revert change to function alignment b/c existing logic was fine
llvm-svn: 142224
2011-10-17 18:53:03 +00:00
Chad Rosier
8247682aba Removed set, but unused variables.
Patch by Joe Abbey <jabbey@arxan.com>.

llvm-svn: 142223
2011-10-17 18:48:30 +00:00
Akira Hatanaka
e8cb50da87 Move class and instruction definitions for conditional moves to a seperate file.
llvm-svn: 142220
2011-10-17 18:43:19 +00:00