Evan Cheng
f3c130a8b6
Enabling new condition code modeling scheme.
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llvm-svn: 42459
2007-09-29 00:00:36 +00:00
Evan Cheng
c2acb6f2e5
Stop inventing new words. :-)
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llvm-svn: 42429
2007-09-28 01:35:02 +00:00
Evan Cheng
d3ff9d3ff7
Pessimisively assume ADJCALLSTACKDOWN / ADJCALLSTACKUP (which becomes sub / add) clobbers EFLAGS.
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llvm-svn: 42426
2007-09-28 01:19:48 +00:00
Evan Cheng
66eeb8440c
Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. Just emit them as pushf and popf.
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llvm-svn: 42371
2007-09-26 21:28:00 +00:00
Evan Cheng
37ee6eba29
Typos: POPQ -> POPFQ, POPD -> POPFD.
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llvm-svn: 42348
2007-09-26 06:38:29 +00:00
Evan Cheng
5cb9dbaaa1
Add pushf{d|q}, popf{d|q} to push and pop EFLAGS register.
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llvm-svn: 42335
2007-09-26 01:29:06 +00:00
Evan Cheng
36b3babfde
Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
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all the kinks are worked out.
llvm-svn: 42285
2007-09-25 01:57:46 +00:00
Dan Gohman
a264777dc1
Fix the syntax for the .loc directive in preparation for using it.
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llvm-svn: 42268
2007-09-24 19:25:06 +00:00
Dale Johannesen
ea6ffa0b36
Fix PR 1681. When X86 target uses +sse -sse2,
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keep f32 in SSE registers and f64 in x87. This
is effectively a new codegen mode.
Change addLegalFPImmediate to permit float and
double variants to do different things.
Adjust callers.
llvm-svn: 42246
2007-09-23 14:52:20 +00:00
Evan Cheng
13797e4a74
Add implicit def of EFLAGS on those instructions that may modify flags.
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llvm-svn: 41962
2007-09-14 21:48:26 +00:00
Evan Cheng
b43255bc68
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
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llvm-svn: 41863
2007-09-11 19:55:27 +00:00
Evan Cheng
65df926ced
TableGen no longer emit CopyFromReg nodes for implicit results in physical
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registers. The scheduler is now responsible for emitting them.
llvm-svn: 41781
2007-09-07 23:59:02 +00:00
Dan Gohman
3bc1bc2590
Avoid storing and reloading zeros and other constants from stack slots
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by flagging the associated instructions as being trivially rematerializable.
llvm-svn: 41775
2007-09-07 21:32:51 +00:00
Evan Cheng
527fe7ab57
Mark load instructions with isLoad = 1.
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llvm-svn: 41595
2007-08-30 05:49:43 +00:00
Dale Johannesen
a85f11d870
Long double patch 4 of N: initial x87 implementation.
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Lots of problems yet but some simple things work.
llvm-svn: 40847
2007-08-05 18:49:15 +00:00
Evan Cheng
3163814591
Switch some multiplication instructions over to the new scheme for testing.
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llvm-svn: 40723
2007-08-02 05:48:35 +00:00
Evan Cheng
0fa6cdbff5
Mac OS X X86-64 low 4G address not available.
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llvm-svn: 40701
2007-08-01 23:45:51 +00:00
Evan Cheng
fb587a3851
Be more precise.
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llvm-svn: 40689
2007-08-01 20:22:37 +00:00
Dan Gohman
e3464e6bec
Change the x86 assembly output to use tab characters to separate the
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mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.
llvm-svn: 40648
2007-07-31 20:11:57 +00:00
Evan Cheng
3493ec0ce1
Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )
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llvm-svn: 40628
2007-07-31 08:04:03 +00:00
Christopher Lamb
919ce03da6
Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource.
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llvm-svn: 40578
2007-07-29 01:24:57 +00:00
Dan Gohman
d3a062f01b
In the .loc directive, print the fields as "debug" fields, so they
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don't get decorated as if for immediate fields for instructions.
llvm-svn: 40529
2007-07-26 15:24:15 +00:00
Evan Cheng
53cb03b583
No more noResults.
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llvm-svn: 40132
2007-07-21 00:34:19 +00:00
Evan Cheng
8312ed6f77
Change instruction description to split OperandList into OutOperandList and
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InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 01:14:50 +00:00
Anton Korobeynikov
5635277c36
Long live the exception handling!
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This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.
In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.
After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be
thought as 'finished': I expect many small and not so small glitches
everywhere.
llvm-svn: 39855
2007-07-14 14:06:15 +00:00
Dan Gohman
9cbc3fb1ab
Revert the earlier change that removed the M_REMATERIALIZABLE machine
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instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).
llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Dan Gohman
b60d8a92c9
Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
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with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.
llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Nate Begeman
f496eb7607
Reference correct header
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llvm-svn: 36834
2007-05-06 04:00:55 +00:00
Bill Wendling
552e4ff1be
Add SSSE3 as a feature of Core2. Add MMX registers to the list of registers
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clobbered by a call.
llvm-svn: 36448
2007-04-25 21:31:48 +00:00
Lauro Ramos Venancio
b75c6c5cbc
X86 TLS: optimize the implementation of "local exec" model.
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llvm-svn: 36359
2007-04-23 01:28:10 +00:00
Lauro Ramos Venancio
b1a101f0e7
X86 TLS: fix and optimize the implementation of "initial exec" model.
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llvm-svn: 36355
2007-04-22 22:50:52 +00:00
Lauro Ramos Venancio
bc32d90b46
Implement "general dynamic", "initial exec" and "local exec" TLS models for
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X86 32 bits.
llvm-svn: 36283
2007-04-20 21:38:10 +00:00
Anton Korobeynikov
9bc4b792bf
Implemented correct stack probing on mingw/cygwin for dynamic alloca's.
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Also, fixed static case in presence of eax livin. This fixes PR331
PS: Why don't we still have push/pop instructions? :)
llvm-svn: 36195
2007-04-17 09:20:00 +00:00
Bill Wendling
3b1189afbf
Add support for our first SSSE3 instruction "pmulhrsw".
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llvm-svn: 35869
2007-04-10 22:10:25 +00:00
Evan Cheng
00a5cbf9e7
Mark re-materializable instructions.
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llvm-svn: 35230
2007-03-21 00:16:56 +00:00
Jim Laskey
23ed7d2625
Make LABEL a builtin opcode.
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llvm-svn: 33537
2007-01-26 14:34:52 +00:00
Chris Lattner
784201d1b9
Fix a misencoding of CBW and CWD. This fixes PR1030.
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llvm-svn: 33486
2007-01-24 18:31:00 +00:00
Evan Cheng
adeea85f7d
- Switch X86-64 JIT to large code size model.
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- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.
llvm-svn: 32238
2006-12-05 19:50:18 +00:00
Evan Cheng
456101ebb9
- Use a different wrapper node for RIP-relative GV, etc.
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- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.
llvm-svn: 32046
2006-11-30 21:55:46 +00:00
Evan Cheng
f968824cdb
Custom lower READCYCLECOUNTER for x86-64.
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llvm-svn: 32017
2006-11-29 08:28:13 +00:00
Chris Lattner
7c265ad682
remove dead/redundant vars
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llvm-svn: 31435
2006-11-03 23:48:56 +00:00
Reid Spencer
db06ed9156
Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4
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generated object modules to be debugged with gdb. Hopefully this helps
pre-release debugging.
llvm-svn: 31299
2006-10-30 22:32:30 +00:00
Evan Cheng
fe5bb5dbe6
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
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llvm-svn: 30945
2006-10-13 21:14:26 +00:00
Chris Lattner
b25677f5ca
Move the Imp tblgen class from the X86 backend to common code.
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llvm-svn: 30907
2006-10-12 17:49:27 +00:00
Chris Lattner
a678c5bac1
Mark ADJCALLSTACKUP/DOWN as clobbering ESP so that virtregmap will notice
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that it can't assume ESP is unmodified across the instrs.
llvm-svn: 30905
2006-10-12 17:42:56 +00:00
Evan Cheng
ca66f49574
Add properties to ComplexPattern.
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llvm-svn: 30891
2006-10-11 21:03:53 +00:00
Evan Cheng
d22f3dd3ed
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
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llvm-svn: 30844
2006-10-09 20:57:25 +00:00
Evan Cheng
02e193e2ff
Delete dead code; fix 80 col violations.
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llvm-svn: 30583
2006-09-22 21:43:59 +00:00
Evan Cheng
cfd7b147cf
X86ISD::CMP now produces a chain as well as a flag. Make that the chain
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operand of a conditional branch to allow load folding into CMP / TEST
instructions.
llvm-svn: 30241
2006-09-11 02:19:56 +00:00
Evan Cheng
15dd42884e
Committing X86-64 support.
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llvm-svn: 30177
2006-09-08 06:48:29 +00:00