Jim Grosbach
53aa92f766
Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned
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llvm-svn: 86425
2009-11-08 00:27:19 +00:00
Evan Cheng
069209cf6b
Refactor code.
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llvm-svn: 86423
2009-11-08 00:15:23 +00:00
Jim Grosbach
7152d0423b
80-column cleanup of file header comments
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llvm-svn: 86408
2009-11-07 22:00:39 +00:00
Jim Grosbach
73c1e315e1
Support alignment specifier for NEON vld/vst instructions
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llvm-svn: 86404
2009-11-07 21:25:39 +00:00
Evan Cheng
f031cd530c
t2ldrpci_pic can be used for blockaddress as well.
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llvm-svn: 86400
2009-11-07 19:40:04 +00:00
Chris Lattner
25421b6954
indicate what the native integer types for the target are.
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Please verify.
llvm-svn: 86397
2009-11-07 19:07:32 +00:00
Anton Korobeynikov
30095499fc
It turns out that the testcase in question uncovered subreg-handling bug.
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Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.
llvm-svn: 86375
2009-11-07 15:20:32 +00:00
Jeffrey Yasskin
502d93267d
Make the need-stub variables accurate and consistent. In the case of
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MachineRelocations, "stub" always refers to a far-call stub or a
load-a-faraway-global stub, so this patch adds "Far" to the term. (Other stubs
are used for lazy compilation and dlsym address replacement.) The variable was
also inconsistent between the positive and negative sense, and the positive
sense ("NeedStub") was more demanding than is accurate (since a nearby-enough
function can be called directly even if the platform often requires a stub).
Since the negative sense causes double-negatives, I switched to
"MayNeedFarStub" globally.
llvm-svn: 86363
2009-11-07 08:51:52 +00:00
Evan Cheng
899d8cb6a0
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
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llvm-svn: 86330
2009-11-07 04:04:34 +00:00
Evan Cheng
8eaaffb9da
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
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except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
llvm-svn: 86328
2009-11-07 03:52:02 +00:00
Ted Kremenek
f8905e9718
Update CMake file.
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llvm-svn: 86325
2009-11-07 03:26:59 +00:00
Johnny Chen
5158450544
My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm
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was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0). The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.
llvm-svn: 86319
2009-11-07 00:54:36 +00:00
Jim Grosbach
71c5411651
80-columns
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llvm-svn: 86310
2009-11-07 00:13:30 +00:00
Evan Cheng
6e3e66375a
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
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load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
llvm-svn: 86304
2009-11-06 23:52:48 +00:00
Anton Korobeynikov
dca40933ee
Honour subreg machine operands during asmprinting
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llvm-svn: 86303
2009-11-06 23:45:15 +00:00
Bob Wilson
e79354a831
Print VMOV (immediate) operands as hexadecimal values. Apple's assembler
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will not accept negative values for these. LLVM's default operand printing
sign extends values, so that valid unsigned values appear as negative
immediates. Print all VMOV immediate operands as hex values to resolve this.
Radar 7372576.
llvm-svn: 86301
2009-11-06 23:33:28 +00:00
Evan Cheng
aaf30ce699
Remove ARMPCLabelIndex from ARMISelLowering. Use ARMFunctionInfo::createConstPoolEntryUId() instead.
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llvm-svn: 86294
2009-11-06 22:24:13 +00:00
Daniel Dunbar
4daaf9d3f4
Pass StringRef by value.
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llvm-svn: 86251
2009-11-06 10:58:06 +00:00
Dan Gohman
ada358e6a2
Factor out the printing of the leading tab into printInlineAsm.
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llvm-svn: 86199
2009-11-06 00:04:54 +00:00
Dan Gohman
eec0f1c506
Remove uninteresting and confusing debug output.
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llvm-svn: 86149
2009-11-05 18:47:09 +00:00
Jim Grosbach
ef37391033
Grammar.
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llvm-svn: 86068
2009-11-04 23:20:40 +00:00
Jim Grosbach
2867641b64
Now that the memory leak from McCat/08-main has been fixed (86056), re-enable
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aggressive testing of dynamic stack alignment.
Note that this is off by default, and enabled for LLCBETA nightly results.
llvm-svn: 86064
2009-11-04 23:11:07 +00:00
Jim Grosbach
c0cabc9119
If a function has no stack frame at all, dynamic realignment isn't necessary.
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llvm-svn: 86057
2009-11-04 22:41:51 +00:00
Jim Grosbach
c8a01556f4
dynamic stack realignment necessitates scanning the floating point callee-
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saved instructions even if no stack adjustment for those saves is needed.
llvm-svn: 86056
2009-11-04 22:41:00 +00:00
Jakob Stoklund Olesen
f775e222e0
Print out an informative comment for KILL instructions.
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The KILL pseudo-instruction may survive to the asm printer pass, just like the IMPLICIT_DEF. Print the KILL as a comment instead of just leaving a blank line in the output.
With -asm-verbose=0, a blank line is printed, like IMPLICIT?DEF.
llvm-svn: 86041
2009-11-04 19:24:37 +00:00
Evan Cheng
22121f4c69
The .n suffix must go after the predicate.
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llvm-svn: 86019
2009-11-04 07:38:48 +00:00
Evan Cheng
1a06b12330
Use ldr.n to workaround a darwin assembler bug.
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llvm-svn: 85980
2009-11-04 00:00:39 +00:00
Evan Cheng
b50510c510
Fix t2Int_eh_sjlj_setjmp. Immediate form of orr is a 32-bit instruction. So it should be 22 bytes instead of 20 bytes long.
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llvm-svn: 85965
2009-11-03 23:13:34 +00:00
Evan Cheng
caab17007b
fconsts / fconstd immediate should be proceeded with #.
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llvm-svn: 85952
2009-11-03 21:59:33 +00:00
Anton Korobeynikov
de7cbab064
Move subtarget check upper for NEON reg-reg fixup pass.
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llvm-svn: 85914
2009-11-03 18:46:11 +00:00
Evan Cheng
1d4575274c
Trim unnecessary include.
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llvm-svn: 85878
2009-11-03 07:08:08 +00:00
Bob Wilson
97331f70ca
For Thumb indirect branches, use "mov pc, reg" which does not switch
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between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.
llvm-svn: 85874
2009-11-03 06:29:56 +00:00
Evan Cheng
ed22395c61
Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.
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llvm-svn: 85871
2009-11-03 05:52:54 +00:00
Evan Cheng
2807af42c0
Clean up copyRegToReg.
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llvm-svn: 85870
2009-11-03 05:51:39 +00:00
Evan Cheng
9bedf1b587
Add QPR_8 as a superreg class of SPR_8 and DPR_8.
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llvm-svn: 85869
2009-11-03 05:50:57 +00:00
Ted Kremenek
a474928cda
Update CMake file.
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llvm-svn: 85861
2009-11-03 04:14:12 +00:00
Anton Korobeynikov
ff29071cc6
Turn neon reg-reg moves fixup code into separate pass. This should reduce the compile time.
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llvm-svn: 85850
2009-11-03 01:04:26 +00:00
Anton Korobeynikov
48b30c79be
Revert r85049, it is causing PR5367
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llvm-svn: 85847
2009-11-03 00:24:48 +00:00
Bob Wilson
7e071e14eb
Revert previous change to a comment. The BlockAddresses go in the
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constant pool so they don't get wrapped separately.
llvm-svn: 85844
2009-11-03 00:02:05 +00:00
Bob Wilson
3144715b53
Put BlockAddresses into ARM constant pools.
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llvm-svn: 85824
2009-11-02 20:59:23 +00:00
Kevin Enderby
633b294095
Fix ARMAsmParser::ParseMemoryOffsetReg() where the parameter OffsetRegNum should
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have been passed as a reference.
llvm-svn: 85823
2009-11-02 20:14:39 +00:00
David Goodwin
9aa890eab6
Fix schedule model for BFC.
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llvm-svn: 85809
2009-11-02 17:28:36 +00:00
Bob Wilson
0c213bed8b
Hyphenate some comments.
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llvm-svn: 85808
2009-11-02 17:10:37 +00:00
Bob Wilson
6eb4f53d90
Add support for BlockAddress values in ARM constant pools.
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llvm-svn: 85806
2009-11-02 16:59:06 +00:00
Bob Wilson
ac53e0c640
Prune unnecessary include.
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llvm-svn: 85805
2009-11-02 16:58:31 +00:00
Evan Cheng
e79ff8a615
These are done / no longer care.
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llvm-svn: 85798
2009-11-02 07:58:25 +00:00
Evan Cheng
532dfd431f
Add an entry.
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llvm-svn: 85797
2009-11-02 07:51:19 +00:00
Evan Cheng
57f7c7c914
Unbreak ARMBaseRegisterInfo::copyRegToReg.
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llvm-svn: 85787
2009-11-02 04:44:55 +00:00
Anton Korobeynikov
09147da530
Handle splats of undefs properly. This includes the testcase for PR5364 as well.
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llvm-svn: 85767
2009-11-02 00:12:06 +00:00
Anton Korobeynikov
9737bfedeb
Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this won't work if it can contain several types. Require explicit result type for the node for now. This fixes PR5364.
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PS: It seems that blackfin usage of copy_to_regclass is completely bogus!
llvm-svn: 85766
2009-11-02 00:11:39 +00:00