Zlatko Buljan
703131e673
[mips][microMIPS] Implement SHLL.PH, SHLL_S.PH, SHLL.QB, SHLLV.PH, SHLLV_S.PH, SHLLV.QB, SHLLV_S.W, SHLL_S.W, SHRA.QB and SHRA_R.QB instructions
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Differential Revision: http://reviews.llvm.org/D13929
llvm-svn: 251098
2015-10-23 06:39:29 +00:00
Daniel Sanders
6fac4ec6e5
[mips][msa] Remove copy_u.d and move copy_u.w to MSA64.
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Summary:
The forwards compatibility strategy employed by MIPS is to consider registers
to be infinitely sign-extended. Then on ISA's with a wider register, the result
of existing instructions are sign-extended to register width and zero-extended
counterparts are added. copy_u.w on MSA32 and copy_u.w on MSA64 violate this
strategy and we have therefore corrected the MSA specs to fix this.
We still keep track of sign/zero-extension during legalization but we now
match copy_s.[wd] where required.
No change required to clang since __builtin_msa_copy_u_[wd] will map to
copy_s.[wd] where appropriate for the target.
Reviewers: vkalintiris
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D13472
llvm-svn: 250887
2015-10-21 09:58:54 +00:00
Zlatko Buljan
56aeea0467
[mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions
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Differential Revision: http://reviews.llvm.org/D13130
llvm-svn: 250685
2015-10-19 07:16:26 +00:00
Zlatko Buljan
51aca82162
[mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions
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Differential Revision: http://reviews.llvm.org/D13721
llvm-svn: 250683
2015-10-19 06:34:44 +00:00
Zlatko Buljan
47bb2beb49
[mips][microMIPS] Implement DPA.W.PH, DPAQ_S.W.PH, DPAQ_SA.L.W, DPAQX_S.W.PH, DPAQX_SA.W.PH, DPAU.H.QBL, DPAU.H.QBR and DPAX.W.PH instructions
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Differential Revision: http://reviews.llvm.org/D13376
llvm-svn: 250382
2015-10-15 08:59:45 +00:00
Zoran Jovanovic
d3024c63d9
[mips][micromips] Initial support for micrmomips DSP instructions and addu.qb implementation
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Differential Revision: http://reviews.llvm.org/D12798
llvm-svn: 250058
2015-10-12 16:07:25 +00:00
Akira Hatanaka
71d4bd4bf0
[mips] Define a pseudo instruction which writes to both the lower and higher
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parts of the accumulators and gets expanded post-RA.
llvm-svn: 192667
2013-10-15 01:48:30 +00:00
Akira Hatanaka
d1a7cbb2fc
[mips] Use predicates to guard instructions using accumulator registers instead
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of relying on AddedComplexity.
llvm-svn: 192665
2013-10-15 01:21:37 +00:00
Akira Hatanaka
64f68981a2
[mips] Rename isel nodes.
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llvm-svn: 192663
2013-10-15 01:12:50 +00:00
Akira Hatanaka
da64382f71
[mips] Fix definition of mfhi and mflo instructions to read from the whole
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accumulator instead of its sub-registers, $hi and $lo.
We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:
mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2 // read lower 32-bit result from $lo.
mtlo $4 // write to $lo. the content of $hi becomes unpredictable.
mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value.
I don't have a test case for this change that reliably reproduces the problem.
llvm-svn: 192119
2013-10-07 18:49:46 +00:00
Akira Hatanaka
c11e303acd
[mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
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into a 5-bit or 6-bit field.
llvm-svn: 190226
2013-09-07 00:02:02 +00:00
Akira Hatanaka
2236f78fa4
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
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Also, fix predicates.
llvm-svn: 189432
2013-08-28 00:55:15 +00:00
Akira Hatanaka
191591d4eb
[mips] Resolve register classes dynamically using ptr_rc to reduce the number of
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load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.
llvm-svn: 188830
2013-08-20 21:08:22 +00:00
Akira Hatanaka
2f7e9a3a07
[mips] Use register operands instead of register classes in DSP instruction
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definitions.
llvm-svn: 188343
2013-08-14 01:02:20 +00:00
Akira Hatanaka
3e7c555daa
[mips] Rename DSPRegs.
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llvm-svn: 188342
2013-08-14 00:53:38 +00:00
Akira Hatanaka
6ac16b554b
[mips] Rename HIRegs and LORegs.
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llvm-svn: 188341
2013-08-14 00:47:08 +00:00
Akira Hatanaka
c05b5c3dae
[mips] Rename accumulator register classes and FP register operands.
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llvm-svn: 188020
2013-08-08 21:54:26 +00:00
Akira Hatanaka
41ad5610bf
[mips] Mark pseudo instructions as code-gen only.
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llvm-svn: 188017
2013-08-08 21:44:39 +00:00
Akira Hatanaka
1290d365ec
[mips] Rename register classes CPURegs and CPU64Regs.
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llvm-svn: 187832
2013-08-06 23:08:38 +00:00
Akira Hatanaka
354394e047
[mips] Replace usages of register classes with register operands. Also, remove
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unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.
llvm-svn: 187821
2013-08-06 22:20:40 +00:00
Akira Hatanaka
5f295bccfc
[mips] Split the DSP control register and define one register for each field of
...
its fields.
This removes false dependencies between DSP instructions which access different
fields of the the control register. Implicit register operands are added to
instructions RDDSP and WRDSP after instruction selection, depending on the
value of the mask operand.
llvm-svn: 181041
2013-05-03 18:37:49 +00:00
Akira Hatanaka
ab6ee99fe0
[mips] Handle reading, writing or copying of ccond field of DSP control
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register.
- Define pseudo instructions which store or load ccond field of the DSP
control register.
- Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack.
- Expand the pseudos before callee-scan save.
- Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs.
llvm-svn: 180969
2013-05-02 23:07:05 +00:00
Akira Hatanaka
f5c940dea8
[mips] Fix handling of instructions which copy to/from accumulator registers.
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Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.
llvm-svn: 180827
2013-04-30 23:22:09 +00:00
Akira Hatanaka
0bca7f3584
[mips] Instruction selection patterns for DSP-ASE vector select and compare
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instructions.
llvm-svn: 180820
2013-04-30 22:37:26 +00:00
Akira Hatanaka
61f007d121
[mips] Clear isCommutable bit of instructions which are not commutable.
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llvm-svn: 180801
2013-04-30 20:40:39 +00:00
Akira Hatanaka
913bf6194a
[mips] In performDSPShiftCombine, check that all elements in the vector are
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shifted by the same amount and the shift amount is smaller than the element
size.
llvm-svn: 180039
2013-04-22 19:58:23 +00:00
Akira Hatanaka
11b4211d68
[mips] Instruction selection patterns for DSP-ASE vector shifts.
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llvm-svn: 179906
2013-04-19 23:21:32 +00:00
Akira Hatanaka
ae4353c654
[mips] DSP-ASE move from HI/LO register instructions.
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llvm-svn: 179739
2013-04-18 00:52:44 +00:00
Akira Hatanaka
e0468ce3e1
[mips] Reapply r179420 and r179421.
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llvm-svn: 179434
2013-04-13 00:55:41 +00:00
Akira Hatanaka
b0b85e00d8
Revert r179420 and r179421.
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llvm-svn: 179422
2013-04-12 22:40:07 +00:00
Akira Hatanaka
737648f84c
[mips] Instruction selection patterns for carry-setting and using add
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instructions.
llvm-svn: 179421
2013-04-12 22:24:52 +00:00
Akira Hatanaka
d809bc8eeb
[mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.
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llvm-svn: 179420
2013-04-12 22:14:24 +00:00
Akira Hatanaka
bc81d23802
[mips] Add patterns for DSP indexed load instructions.
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llvm-svn: 178408
2013-03-30 02:14:45 +00:00
Akira Hatanaka
5ff9493456
[mips] Fix DSP instructions to have explicit accumulator register operands.
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Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.
llvm-svn: 178406
2013-03-30 01:58:00 +00:00
Akira Hatanaka
86302e607d
[mips] Define pseudo instructions for spilling and copying accumulator
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registers.
llvm-svn: 178390
2013-03-30 00:54:52 +00:00
Akira Hatanaka
9ed2d54e79
[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
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parameter.
llvm-svn: 170661
2012-12-20 04:20:09 +00:00
Akira Hatanaka
01e48fccff
[mips] Move class IsCommutable into MipsInstrInfo.td.
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llvm-svn: 170054
2012-12-13 00:32:01 +00:00
Akira Hatanaka
8c74c52ca4
MIPS DSP: other miscellaneous instructions.
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llvm-svn: 164845
2012-09-28 20:50:31 +00:00
Akira Hatanaka
ca62e0c897
MIPS DSP: ADDUH.QB instruction sub-class.
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llvm-svn: 164840
2012-09-28 20:16:04 +00:00
Akira Hatanaka
4282b930ad
MIPS DSP: ABSQ_S.PH instruction sub-class.
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llvm-svn: 164787
2012-09-27 19:09:21 +00:00
Akira Hatanaka
1b01d7ee93
MIPS DSP: SHLL.QB instruction sub-class.
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llvm-svn: 164786
2012-09-27 19:05:08 +00:00
Akira Hatanaka
dbe52eccf8
MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR).
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llvm-svn: 164756
2012-09-27 04:08:42 +00:00
Akira Hatanaka
6ad7cd9351
MIPS DSP: CMPU.EQ.QB instruction sub-class.
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llvm-svn: 164755
2012-09-27 03:58:34 +00:00
Akira Hatanaka
8e6fa1d3a5
MIPS DSP: ADDU.QB instruction sub-class.
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llvm-svn: 164754
2012-09-27 03:13:59 +00:00
Akira Hatanaka
5a5e58b7ab
MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field instruction.
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llvm-svn: 164751
2012-09-27 02:15:57 +00:00
Akira Hatanaka
b33fd0ad28
MIPS DSP: all the remaining instructions which read or write accumulators.
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llvm-svn: 164750
2012-09-27 02:11:20 +00:00
Akira Hatanaka
b2ac1bfabe
MIPS DSP: add support for extract-word instructions.
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llvm-svn: 164749
2012-09-27 02:05:42 +00:00
Akira Hatanaka
882f4d03f6
MIPS DSP: add bitcast patterns between vectors and int.
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No test cases. These patterns will get tested along with dsp intrinsics.
llvm-svn: 164746
2012-09-27 01:56:38 +00:00
Akira Hatanaka
804a9036c3
MIPS DSP: add vector load/store patterns.
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llvm-svn: 164744
2012-09-27 01:50:59 +00:00
Akira Hatanaka
cf8158381d
MIPS DSP: Add immediate leaves.
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llvm-svn: 164435
2012-09-22 00:07:12 +00:00