RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 12:33:33 +02:00
Code Issues Projects Releases Wiki Activity
98,854 Commits 4 Branches 5 Tags 704 MiB
71734d085a
Commit Graph

26680 Commits

Author SHA1 Message Date
Craig Topper
71734d085a Fix ModR/M byte output for 16-bit addressing modes (PR18220) 
Add some tests to validate correct register selection, including a fix
to an existing test which was requiring the *wrong* output.

Patch from David Woodhouse.

llvm-svn: 198566
 2014-01-05 19:40:56 +00:00
Craig Topper
423b149a44 Remove opcode from MOV32r0 that I accidentally left when I converted it to Pseudo. Remove FIXME as well. 
llvm-svn: 198564
 2014-01-05 19:25:13 +00:00
Saleem Abdulrasool
c246705aa9 ARM: style changes to LDRD, STRD definition 
Fix indentation, name registers similar to ARM ARM.

No functionality change!

llvm-svn: 198563
 2014-01-05 16:36:37 +00:00
Elena Demikhovsky
935f81172d AVX-512: changed property name from "neverHasSideEffects=1" to "hasSideEffects=0", added this property to VMOVSS/VMOVSD; 
Optimized a truncate pattern.

llvm-svn: 198562
 2014-01-05 14:21:07 +00:00
Elena Demikhovsky
034a667c24 AVX-512: Added more intrinsics for convert and min/max. 
Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all.

llvm-svn: 198557
 2014-01-05 10:46:09 +00:00
Craig Topper
1ed77cb9d9 Add the other form of movq xmm,xmm for the disassembler. 
llvm-svn: 198551
 2014-01-05 07:16:04 +00:00
Craig Topper
60c74a0e11 Use patterns to remove some duplicate instructions. 
llvm-svn: 198550
 2014-01-05 06:55:48 +00:00
Craig Topper
3ff26e1332 Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack. 
llvm-svn: 198547
 2014-01-05 05:46:38 +00:00
Craig Topper
eea372cfa3 Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches. 
llvm-svn: 198545
 2014-01-05 04:55:55 +00:00
Craig Topper
0b1961cfbc Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack. 
llvm-svn: 198544
 2014-01-05 04:32:42 +00:00
Craig Topper
4a48c26e38 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. 
llvm-svn: 198543
 2014-01-05 04:17:28 +00:00
Venkatraman Govindaraju
7b675d45b0 [Sparc] Add initial implementation of MC Code emitter for sparc. 
llvm-svn: 198533
 2014-01-05 02:13:48 +00:00
Bill Wendling
be9af41475 Emit an error message if the value passed to __builtin_returnaddress isn't a constant 
__builtin_returnaddress requires that the value passed into is be a constant.
However, at -O0 even a constant expression may not be converted to a constant.
Emit an error message intead of crashing.

llvm-svn: 198531
 2014-01-05 01:47:20 +00:00
Craig Topper
83505ed565 Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. 
llvm-svn: 198530
 2014-01-05 01:35:51 +00:00
Craig Topper
0418d1dd5a Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack. 
llvm-svn: 198515
 2014-01-04 22:29:41 +00:00
Venkatraman Govindaraju
25bd5d1ff3 [Sparc] Add the initial implementation of an asm parser for sparc/sparcv9. 
llvm-svn: 198484
 2014-01-04 11:30:13 +00:00
Venkatraman Govindaraju
bfcef24b91 [SparcV9]: Implement RETURNADDR and FRAMEADDR lowering in SPARC64. 
Fixes PR18356.

llvm-svn: 198480
 2014-01-04 07:17:21 +00:00
Craig Topper
4c535886dc Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. 
llvm-svn: 198475
 2014-01-04 05:09:27 +00:00
Rafael Espindola
eae6386a1e Make the llvm mangler depend only on DataLayout. 
Before this patch any program that wanted to know the final symbol name of a
GlobalValue had to link with Target.

This patch implements a compromise solution where the mangler uses DataLayout.
This way, any tool that already links with Target (llc, clang) gets the exact
behavior as before and new IR files can be mangled without linking with Target.

With this patch the mangler is constructed with just a DataLayout and DataLayout
is extended to include the information the Mangler needs.

llvm-svn: 198438
 2014-01-03 19:21:54 +00:00
Ana Pazos
2ad0c92db1 [AArch64][NEON] Added SXTL and SXTL2 instruction aliases 
llvm-svn: 198437
 2014-01-03 19:20:31 +00:00
Hal Finkel
d0f8236add [PPC] Fix comment to match function name 
llvm-svn: 198362
 2014-01-02 22:09:39 +00:00
Hal Finkel
0e77f939b4 [PPC] Fix the scheduling of CR logicals on the P7 
CR logicals (crand, crxor, etc.) on the P7 need to be in the first slot of each
dispatch group. The old itinerary entry was just wrong (but has not mattered
because we don't generate these instructions).

This will matter when, in an upcoming commit, we start generating these
instructions.

llvm-svn: 198359
 2014-01-02 21:38:26 +00:00
Hal Finkel
dc47cd8c25 [PPC] Use the correct immediate operands on 64-bit instructions 
Several of the 64-bit fixed-point instructions with immediate operands were
using the 32-bit (i32) operand nodes instead of the corresponding 64-bit (i64)
operand definitions (u16imm instead of u16imm64, for example).

This error has had no effect so far, but would have caused type-checking
violations with an upcoming change.

llvm-svn: 198356
 2014-01-02 21:26:59 +00:00
Craig Topper
839231f528 Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr. 
llvm-svn: 198336
 2014-01-02 19:12:10 +00:00
Craig Topper
ba17ca1e89 Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder. 
llvm-svn: 198327
 2014-01-02 18:20:48 +00:00
Craig Topper
57b949fa83 Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them. 
llvm-svn: 198323
 2014-01-02 17:28:14 +00:00
Logan Chien
afb46ba663 [arm] Add softvfp to supported FPU names. 
llvm-svn: 198313
 2014-01-02 15:50:02 +00:00
Rafael Espindola
4b38156778 Make the ARM ABI selectable via SubtargetFeature. 
This patch makes it possible to select the ABI with -mattr. It will be used to
forward clang's -target-abi option to llvm's CodeGen.

llvm-svn: 198304
 2014-01-02 13:40:08 +00:00
Rafael Espindola
95d600810f Remove the 's' DataLayout specification 
During the years there have been some attempts at figuring out how to
align byval arguments. A look at the commit log suggests that they
were

* Use the ABI alignment.
* When that was not sufficient for x86-64, I added the 's' specification to
  DataLayout.
* When that was not sufficient Evan added the virtual getByValTypeAlignment.
* When even that was not sufficient, we just got the FE to add the alignment
  to the byval.

This patch is just a simple cleanup that removes my first attempt at fixing the
problem. I also added an AArch64 implementation of getByValTypeAlignment to
make sure this patch is a nop. I also left the 's' parsing for backward
compatibility.

I will send a short email to llvmdev about the change for anyone maintaining
an out of tree target.

llvm-svn: 198287
 2014-01-01 22:29:43 +00:00
Venkatraman Govindaraju
cb22135b23 [Sparc] Handle atomic loads/stores in sparc backend. 
llvm-svn: 198286
 2014-01-01 22:11:54 +00:00
Craig Topper
b3f7e28cb6 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables. 
llvm-svn: 198284
 2014-01-01 21:52:57 +00:00
Venkatraman Govindaraju
e8745ffca1 [SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to __multi3() in correct order. 
llvm-svn: 198281
 2014-01-01 20:22:45 +00:00
Venkatraman Govindaraju
2fc6090f42 [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL does not clear top 32 bit, only SRL does. 
llvm-svn: 198280
 2014-01-01 19:00:10 +00:00
NAKAMURA Takumi
b00497d624 X86Disassembler.cpp: Prune stray @return on translateFPRegister(). [-Wdocumentation] 
llvm-svn: 198279
 2014-01-01 16:19:26 +00:00
Craig Topper
9d2e15270b Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. 
llvm-svn: 198278
 2014-01-01 15:29:32 +00:00
Elena Demikhovsky
7174584583 AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277
 2014-01-01 15:12:34 +00:00
Craig Topper
4454a2fa93 Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
llvm-svn: 198276
 2014-01-01 14:22:37 +00:00
Craig Topper
d0374cb642 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases. 
llvm-svn: 198265
 2013-12-31 17:21:44 +00:00
Craig Topper
21846ff5d8 Remove old comment referring to an argument that no longer exists. 
llvm-svn: 198263
 2013-12-31 15:29:14 +00:00
Mark Seaborn
7efc188252 Fix misaligned indentation in "if" block in MipsMCCodeEmitter.cpp 
llvm-svn: 198262
 2013-12-31 13:05:15 +00:00
Craig Topper
3cf5463c96 Add missing MRM_XX forms to the old JIT emitter for consistency. 
llvm-svn: 198258
 2013-12-31 03:26:24 +00:00
Craig Topper
6d963c8b1f Remove MRMInitReg form now that it's last use is gone. 
llvm-svn: 198257
 2013-12-31 03:19:03 +00:00
Craig Topper
ed98df1d3a Handle MOV32r0 in expandPostRAPseudo instead of MCInst lowering. No functional change intended. 
llvm-svn: 198254
 2013-12-31 03:05:38 +00:00
Craig Topper
16c0ad5809 Merge case statements to remove redundant code. 
llvm-svn: 198241
 2013-12-30 19:47:49 +00:00
Craig Topper
c4a2189f05 Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
llvm-svn: 198238
 2013-12-30 19:16:48 +00:00
Saleem Abdulrasool
b3b5b0ab09 ARM IAS: account for predicated pre-UAL mnemonics 
Checking the trailing letter of the mnemonic is insufficient.  Be more thorough
in the scanning of the instruction to ensure that we correctly work with the
predicated mnemonics.

llvm-svn: 198235
 2013-12-30 18:38:01 +00:00
Bill Wendling
e44a5893b0 Keep comment with 'Subtarget' ivar. 
llvm-svn: 198201
 2013-12-30 05:17:29 +00:00
Jiangning Liu
583b8a7116 For AArch64 Neon, simplify scalar dup by lane0 for fp. 
llvm-svn: 198194
 2013-12-30 02:44:35 +00:00
Hao Liu
ab32d54fad [AArch64]Add code to spill/fill Q register tuples such as QPair/QTriple/QQuad. 
llvm-svn: 198193
 2013-12-30 02:38:12 +00:00
Hao Liu
8bef865160 [AArch64]Can't select shift left 0 of type v1i64 
llvm-svn: 198192
 2013-12-30 02:12:46 +00:00