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1819 Commits

Author SHA1 Message Date
Chris Lattner
9d1e8420ff Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic. 
llvm-svn: 145171
 2011-11-27 06:54:59 +00:00
Wesley Peck
13edec82a8 Add several new instructions supported by the latest MicroBlaze. 
These instructions are not generated by the backend yet, this will come in a later commit.

llvm-svn: 145161
 2011-11-27 05:16:58 +00:00
Bruno Cardoso Lopes
626d04cc6f This patch contains support for encoding FMA4 instructions and 
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.

Patch by Jan Sjodin

llvm-svn: 145133
 2011-11-25 19:33:42 +00:00
Benjamin Kramer
d03fc374bd X86: alias cqo to cqto. 
llvm-svn: 145121
 2011-11-24 12:02:46 +00:00
Jim Grosbach
1b837af2bd Remove obsolete test. 
The PLD encoding is checked via the .s file now.

llvm-svn: 144853
 2011-11-16 22:50:38 +00:00
Jim Grosbach
fe5f0cfa29 Generalize the fixup info for ARM mode. 
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

llvm-svn: 144852
 2011-11-16 22:48:37 +00:00
Jim Grosbach
8fae277866 Update test for r144842. 
llvm-svn: 144851
 2011-11-16 22:46:27 +00:00
Jim Grosbach
044acb8bee ARM assembly parsing for register range syntax for VLD/VST register lists. 
For example,
vld1.f64 {d2-d5}, [r2,:128]!

Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!

It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.

rdar://10451128

llvm-svn: 144727
 2011-11-15 23:19:15 +00:00
Jim Grosbach
b8ebc386df ARM assembly parsing two operand forms for shift instructions. 
llvm-svn: 144713
 2011-11-15 22:27:54 +00:00
Jim Grosbach
4d0ad5a4e0 ARM alternate size suffices for VTRN instructions. 
rdar://10435076

llvm-svn: 144694
 2011-11-15 20:49:46 +00:00
Jim Grosbach
8987b277cb ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. 
Yet more of rdar://10435076.

llvm-svn: 144691
 2011-11-15 20:29:42 +00:00
Jim Grosbach
f0690cd90c ARM assembly parsing for two-operand form of 'mul' instruction. 
rdar://10449856.

llvm-svn: 144689
 2011-11-15 20:14:51 +00:00
Jim Grosbach
8b1d4c989c ARM assembly parsing for two-operand form of 'mul' instruction. 
Ongoing rdar://10435114.

llvm-svn: 144688
 2011-11-15 20:02:06 +00:00
Jim Grosbach
e4933acaa7 Testcase for r144684. 
llvm-svn: 144685
 2011-11-15 19:56:17 +00:00
Owen Anderson
35f049f1fb Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. 
llvm-svn: 144683
 2011-11-15 19:55:00 +00:00
Jim Grosbach
df951fa128 Thumb2 assembly parsing for mul.w in IT block fix. 
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

llvm-svn: 144679
 2011-11-15 19:29:45 +00:00
Jim Grosbach
6846540505 ARM parsing datatype suffix variants for non-writeback VST1 instructions. 
rdar://10435076

llvm-svn: 144593
 2011-11-14 23:43:46 +00:00
Jim Grosbach
a1a28df278 ARM parsing datatype suffix variants for non-writeback VLD1 instructions. 
rdar://10435076

llvm-svn: 144592
 2011-11-14 23:32:59 +00:00
Jim Grosbach
00283a5c8e ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions. 
rdar://10435076

llvm-svn: 144587
 2011-11-14 23:11:19 +00:00
Jim Grosbach
4a2f107b04 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

llvm-svn: 144583
 2011-11-14 23:03:21 +00:00
Jim Grosbach
13b7ab7527 ARM optional size suffix for VLDR/VSTR syntax. 
llvm-svn: 144427
 2011-11-11 23:34:43 +00:00
Jim Grosbach
1d581ecb00 ARM allow Q registers in vldm/vstm register lists. 
rdar://9672822

llvm-svn: 144407
 2011-11-11 21:27:40 +00:00
Jim Grosbach
bd7df609b7 Thumb2 parsing for push/pop w/ hi registers in the reglist. 
rdar://10130228.

llvm-svn: 144331
 2011-11-10 23:17:11 +00:00
Jim Grosbach
c3651cb620 Thumb MUL assembly parsing for 3-operand form. 
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

llvm-svn: 144322
 2011-11-10 22:10:12 +00:00
Jim Grosbach
f5943e4c5e ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

llvm-svn: 144301
 2011-11-10 19:18:01 +00:00
Jim Grosbach
b66dfc2999 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

llvm-svn: 144293
 2011-11-10 16:44:55 +00:00
Jim Grosbach
8591bd2bab Thumb2 assembly parsing STMDB w/ optional .w suffix. 
rdar://10422955

llvm-svn: 144242
 2011-11-09 23:44:23 +00:00
Benjamin Kramer
89ebc7ab4b Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

llvm-svn: 144013
 2011-11-07 21:00:59 +00:00
Owen Anderson
ac9fd95057 Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. 
llvm-svn: 143557
 2011-11-02 18:03:14 +00:00
Kevin Enderby
b5dc88b394 Fixed a bug in the code to create a dwarf file and directory table entires when 
it is separating the directory part from the basename of the FileName.  Noticed 
that this:

  .file 1 "dir/foo"

when assembled got the two parts switched.  Using the Mac OS X dwarfdump tool
it can be seen easily:

% dwarfdump -a a.out
include_directories[  1] = 'foo'
                Dir  Mod Time   File Len   File Name
                ---- ---------- ---------- ---------------------------
file_names[  1]    1 0x00000000 0x00000000 dir
...

Which should be:
...
include_directories[  1] = 'dir'
                Dir  Mod Time   File Len   File Name
                ---- ---------- ---------- ---------------------------
file_names[  1]    1 0x00000000 0x00000000 foo

llvm-svn: 143521
 2011-11-01 23:39:05 +00:00
Owen Anderson
0d69f6aa51 Fix disassembly of some VST1 instructions. 
llvm-svn: 143507
 2011-11-01 22:18:13 +00:00
Rafael Espindola
dd7a1f625b Move test to the X86 directory, note the PR number and only run MC once. 
llvm-svn: 143352
 2011-10-31 17:23:09 +00:00
Owen Anderson
d7700cb13f More not-crashing NEON disassembly updates for the vld refactoring. 
llvm-svn: 143351
 2011-10-31 17:17:32 +00:00
Jim Grosbach
f3285dba99 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm". 
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224

llvm-svn: 143235
 2011-10-28 22:36:30 +00:00
Owen Anderson
9e033c5b03 Fix illegal disassembly testcase. 
llvm-svn: 143231
 2011-10-28 21:45:09 +00:00
Owen Anderson
3dd6c949a5 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. 
llvm-svn: 143208
 2011-10-28 18:02:13 +00:00
Jim Grosbach
72ab459378 Thumb2 ADD/SUB instructions encoding selection outside IT block. 
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481

llvm-svn: 143201
 2011-10-28 16:57:07 +00:00
NAKAMURA Takumi
2ea569c7e0 test/MC/AsmParser/2011-09-06-NoNewline.s: Add explicit -mtriple=i386. It uses X86 instruction. 
FIXME: Would it be reproduced without target-specific operands?
FIXME: Why run llvm-mc as the same input by 3 times?
llvm-svn: 143195
 2011-10-28 14:12:30 +00:00
Jim Grosbach
dac7815a91 ARM Allow 'q' registers in VLD/VST vector lists. 
Just treat it as if the constituent D registers where specified.

rdar://10348896

llvm-svn: 143167
 2011-10-28 00:06:50 +00:00
Owen Anderson
f22cd77ceb Add testcase for r143162. 
llvm-svn: 143163
 2011-10-27 22:54:14 +00:00
Kevin Enderby
837c1d56a2 Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and 
not depend on In32BitMode.  Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode.  rdar://9738584

llvm-svn: 143112
 2011-10-27 17:40:41 +00:00
Jim Grosbach
4f7964293a Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix. 
rdar://10348844

llvm-svn: 143110
 2011-10-27 17:33:59 +00:00
Jim Grosbach
e1ec953149 Thumb2 t2MVNi assembly parsing to recognize ".w" suffix. 
rdar://10348584

llvm-svn: 143108
 2011-10-27 17:16:55 +00:00
Jim Grosbach
e3c6fa663f Thumb2 ldr pc-relative encoding fixes. 
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.

More of rdar://10348687

llvm-svn: 143068
 2011-10-26 22:22:01 +00:00
Jim Grosbach
fabe0f2f0b ARM assembly parsing and encoding for VLD1 with writeback. 
Four entry register lists.

llvm-svn: 142882
 2011-10-25 00:14:01 +00:00
Jim Grosbach
688186941f ARM assembly parsing and encoding for VLD1 w/ writeback. 
Three entry register list variation.

llvm-svn: 142876
 2011-10-24 23:26:05 +00:00
Jim Grosbach
cf4fba1dd0 ARM assembly parsing and encoding for VLD1 w/ writeback. 
One and two length register list variants.

llvm-svn: 142861
 2011-10-24 22:16:58 +00:00
Owen Anderson
b0e09258e7 Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. 
llvm-svn: 142817
 2011-10-24 18:04:29 +00:00
Jim Grosbach
0bb9a86fc7 Update test for r142801. 
llvm-svn: 142806
 2011-10-24 17:26:26 +00:00
Craig Topper
3cb62dca0f Add X86 SARX, SHRX, and SHLX instructions. 
llvm-svn: 142779
 2011-10-23 22:18:24 +00:00