1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 19:42:54 +02:00
Commit Graph

15922 Commits

Author SHA1 Message Date
Kevin Enderby
74a2614673 Yet another tweak to X86 instructions to add ud2a as an alias to ud2
(still to add ud2b).

llvm-svn: 117435
2010-10-27 03:01:02 +00:00
Kevin Enderby
d22f3b9de7 Another tweak to X86 instructions to add the missing flex instruction (without
the wait prefix).

llvm-svn: 117434
2010-10-27 02:53:04 +00:00
Kevin Enderby
e812b356cc Tweaks to X86 instructions to allow the 'w' suffix in places it makes
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
2010-10-27 02:32:19 +00:00
Jim Grosbach
5ccda16fe2 LDRi12 machine instructions handle negative offset operands normally (simple
integer values), not with the addrmode2 encoding.

llvm-svn: 117429
2010-10-27 01:19:41 +00:00
Kevin Enderby
d5235bb45c Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
2010-10-27 00:59:28 +00:00
Jim Grosbach
6453c7cdf9 One more spot where the new arm mode LDR instruction representation
doesn't need the additional addrmode2 register operand. Missed it the first
time around.

llvm-svn: 117421
2010-10-27 00:38:16 +00:00
Wesley Peck
854507453a Adding disassembler to the MicroBlaze backend.
llvm-svn: 117420
2010-10-27 00:23:01 +00:00
Jim Grosbach
4d4caf1384 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
rdar://8477752.

llvm-svn: 117419
2010-10-27 00:19:44 +00:00
Jim Grosbach
625e128d29 Since I parameterized this bit, I should probably actually use said parameter.
llvm-svn: 117418
2010-10-26 23:58:04 +00:00
Dale Johannesen
e7f07349e4 Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet).  No functional change except
for dump output.

llvm-svn: 117413
2010-10-26 23:11:10 +00:00
Owen Anderson
1dc05f20e2 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
llvm-svn: 117411
2010-10-26 22:50:46 +00:00
Jim Grosbach
30f6744f05 First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
2010-10-26 22:37:02 +00:00
Owen Anderson
55c0bad37d Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
llvm-svn: 117402
2010-10-26 21:58:41 +00:00
Owen Anderson
570a4cdc45 Simplify classes for shift instructions, which are never commutable.
llvm-svn: 117398
2010-10-26 21:13:59 +00:00
Owen Anderson
0cecbd810e Provide correct NEON encodings for vshl, register and immediate forms.
llvm-svn: 117394
2010-10-26 20:56:57 +00:00
Jim Grosbach
04cd5e5841 Grammar.
llvm-svn: 117388
2010-10-26 19:34:41 +00:00
Jim Grosbach
db5b1d93c2 Nuke extraneous comment. It's applicable elsewhere, but not in this func.
llvm-svn: 117387
2010-10-26 19:22:23 +00:00
Owen Anderson
d8e5d26a56 Add correct NEON encoding for vpadal.
llvm-svn: 117380
2010-10-26 18:18:03 +00:00
Rafael Espindola
adaf2ea5c6 handle X86::EH_RETURN64 and X86::EH_RETURN.
llvm-svn: 117378
2010-10-26 18:09:55 +00:00
Owen Anderson
b7618a821f Add NEON encodings for vmov and vmvn of immediates.
llvm-svn: 117374
2010-10-26 17:40:54 +00:00
Rafael Espindola
e38790534e Implement some relaxations for arithmetic instructions. The limitation
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.

llvm-svn: 117364
2010-10-26 14:09:12 +00:00
Kalle Raiskila
64680cd5b8 Change v64 datalayout in SPU.
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays, 
we use array alignment for v64 too. This makes the 
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.

This also makes an "unaligned store" test to be 
aligned, with different (but functionally equivalent)
code generated.

llvm-svn: 117360
2010-10-26 10:45:47 +00:00
Evan Cheng
324e678bb7 Use instruction itinerary to determine what instructions are 'cheap'.
llvm-svn: 117348
2010-10-26 02:08:50 +00:00
Evan Cheng
59acb7e4cf NEON vmov's are in Neon domain.
llvm-svn: 117347
2010-10-26 02:03:05 +00:00
Bob Wilson
abe62128b5 Tidy up redundant check.
llvm-svn: 117331
2010-10-26 00:02:19 +00:00
Rafael Espindola
5fecad6a27 Produce the headers directly in the Finish method. This allows us to use
the existing streamer methods that are endian safe.

llvm-svn: 117323
2010-10-25 22:26:55 +00:00
Dale Johannesen
2566d39d07 An stdcall function calling a non-stdcall function
cannot use tailcall.  PR 8461.

llvm-svn: 117322
2010-10-25 22:17:05 +00:00
Owen Anderson
e5e0dcd665 Add correct encodings for NEON vabal.
llvm-svn: 117315
2010-10-25 21:29:04 +00:00
Owen Anderson
3eff0b86a5 Add correct NEON encodings for vaba.
llvm-svn: 117309
2010-10-25 20:52:57 +00:00
Owen Anderson
61f5b3f2dc Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
llvm-svn: 117294
2010-10-25 20:17:22 +00:00
Owen Anderson
072692331e Provide correct NEON encodings for vbsl.
llvm-svn: 117293
2010-10-25 20:13:13 +00:00
Jim Grosbach
1a13b873e7 imm12 operands aren't Thumb2 only, so rename the printer helper function.
llvm-svn: 117291
2010-10-25 20:00:01 +00:00
Owen Anderson
59e85cbd66 Add correct instruction encodings for vbic, vorn, and vmvn.
llvm-svn: 117282
2010-10-25 18:43:52 +00:00
Rafael Espindola
7f67e5ad77 Add a virtual destructor.
llvm-svn: 117280
2010-10-25 18:38:32 +00:00
Owen Anderson
2824342fac Provide correct NEON encodings for vand, veor, and vorr.
llvm-svn: 117279
2010-10-25 18:28:30 +00:00
Owen Anderson
ba261b092c Add NEON encoding tests for vcgt and vacgt.
llvm-svn: 117276
2010-10-25 18:03:59 +00:00
Rafael Espindola
5748458e7d Add support for emitting ARM file attributes.
llvm-svn: 117275
2010-10-25 17:50:35 +00:00
Owen Anderson
3a5f798790 Add tests for NEON encodings of vcge and vacge.
llvm-svn: 117274
2010-10-25 17:49:32 +00:00
Owen Anderson
757022131f Add a warning about our inability to test the encoding of vceq with immediate zero.
llvm-svn: 117273
2010-10-25 17:33:02 +00:00
Rafael Espindola
c6e7790c4b Add X86::reloc_global_offset_table and use it to have a single place where
we check for _GLOBAL_OFFSET_TABLE_.

llvm-svn: 117241
2010-10-24 17:35:42 +00:00
Eric Christopher
0dab5810aa Move rejection of NEON parameters earlier in fast isel call processing,
note that we can actually handle some f64 arguments.

llvm-svn: 117209
2010-10-23 09:37:17 +00:00
Benjamin Kramer
ed68a7877c Make the disassembler tables const so they end up in read-only memory.
llvm-svn: 117206
2010-10-23 09:10:44 +00:00
Michael J. Spencer
87c8212d41 X86: Emit _fltused instead of __fltused on Windows x64.
llvm-svn: 117205
2010-10-23 09:06:59 +00:00
Chandler Carruth
7dd652736f Move the remaining attribute macros to systematic names based on the attribute
name and prefixed with 'LLVM_'.

llvm-svn: 117203
2010-10-23 08:40:19 +00:00
Chandler Carruth
ea67aaa252 Remove a define which is never referenced.
llvm-svn: 117202
2010-10-23 08:25:16 +00:00
Chandler Carruth
7799a873bb Switch attribute macros to use 'LLVM_' as a prefix. We retain the old names
until other LLVM projects using these are cleaned up.

llvm-svn: 117200
2010-10-23 08:10:43 +00:00
Evan Cheng
71b2f935db Enable ARM fastcc.
llvm-svn: 117194
2010-10-23 02:19:37 +00:00
Evan Cheng
132906a2d3 Latency between CPSR def and branch is zero.
llvm-svn: 117192
2010-10-23 02:04:38 +00:00
Jim Grosbach
6d65ad0408 Trailing whitespace.
llvm-svn: 117188
2010-10-22 23:48:29 +00:00
Gabor Greif
6e58dbc9e4 fix memory-layout assumption which only holds on little-endian systems
llvm-svn: 117176
2010-10-22 23:16:11 +00:00