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Author SHA1 Message Date
Akira Hatanaka
6454b0ffc1 Expand 64-bit CTPOP and CTTZ. 
llvm-svn: 147021
 2011-12-21 00:14:05 +00:00
Akira Hatanaka
0cc0498ea1 Expand 64-bit atomic load and store. 
llvm-svn: 147019
 2011-12-21 00:02:58 +00:00
Akira Hatanaka
fb94688c7a Test case for r147017. 
llvm-svn: 147018
 2011-12-20 23:58:36 +00:00
Akira Hatanaka
2d293d2f4c Add definition of DSBH (Double Swap Bytes within Halfwords) and 
DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017
 2011-12-20 23:56:43 +00:00
Akira Hatanaka
fa96454cb4 Add definition of WSBH (Word Swap Bytes within Halfwords), which is an 
instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
 
WSBW is removed since it is not an instruction the current architectures
support.

llvm-svn: 147015
 2011-12-20 23:47:44 +00:00
Akira Hatanaka
6f31d220e7 64-bit uint-fp conversion nodes are expanded. 
llvm-svn: 147014
 2011-12-20 23:40:56 +00:00
Akira Hatanaka
02fe8adb97 Enable custom lowering DYNAMIC_STACKALLOC nodes. 
llvm-svn: 147013
 2011-12-20 23:35:46 +00:00
Akira Hatanaka
507cdacdde Set the correct stack pointer register that should be saved or restored. 
llvm-svn: 147012
 2011-12-20 23:28:36 +00:00
Jim Grosbach
0768f2c420 Enable and fix a test. 
llvm-svn: 147011
 2011-12-20 23:20:00 +00:00
Chris Lattner
4ed5f7791d Fix a nasty bug in the type remapping stuff that I added that is breaking kc++ on 
the build bot in some cases.  The basic issue happens when a source module contains
both a "%foo" type and a "%foo.42" type.  It will see the later one, check to see if
the destination module contains a "%foo" type, and it will return true... because
both the source and destination modules are in the same LLVMContext.  We don't want
to map source types to other source types, so don't do the remapping if the mapped
type came from the source module.

Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is 
pretty great that way.

llvm-svn: 147010
 2011-12-20 23:14:57 +00:00
Jim Grosbach
7baaa0fc64 ARM .req register name aliases are case insensitive, just like regnames. 
llvm-svn: 147009
 2011-12-20 23:11:00 +00:00
Akira Hatanaka
2e4f1786b1 Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates 
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.

llvm-svn: 147008
 2011-12-20 23:10:57 +00:00
Akira Hatanaka
8e3e6b14c8 Fix indentation. 
llvm-svn: 147007
 2011-12-20 22:58:01 +00:00
Akira Hatanaka
f728a1b2c5 64-bit data directive. 
llvm-svn: 147005
 2011-12-20 22:52:19 +00:00
Akira Hatanaka
ad193d95ae 32-to-64-bit sext_inreg pattern. 
llvm-svn: 147004
 2011-12-20 22:40:40 +00:00
Akira Hatanaka
13f23f5895 Add 64-bit extload patterns. 
llvm-svn: 147003
 2011-12-20 22:36:08 +00:00
Akira Hatanaka
ed1a29d5c2 Add patterns for matching extloads with 64-bit address. The patterns are enabled 
only when the target ABI is N64.

llvm-svn: 147001
 2011-12-20 22:33:53 +00:00
Jim Grosbach
ff31b81fe2 Move comment to appropriate place. 
llvm-svn: 147000
 2011-12-20 22:26:38 +00:00
Akira Hatanaka
8728f4ed69 Add code in MipsDAGToDAGISel for selecting constant +0.0. 
MIPS64 can generate constant +0.0 with a single DMTC1 instruction. 

llvm-svn: 146999
 2011-12-20 22:25:50 +00:00
Jakob Stoklund Olesen
2b24e1eac4 Heed spill slot alignment on ARM. 
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.

Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack.  Don't use aligned spill code in that case.

llvm-svn: 146997
 2011-12-20 22:15:04 +00:00
Akira Hatanaka
1af9c41014 Revert part of r146995 that was accidentally commmitted. 
llvm-svn: 146996
 2011-12-20 22:09:36 +00:00
Akira Hatanaka
9c5e4d3b90 32-to-64-bit sign extension pattern. 
llvm-svn: 146995
 2011-12-20 22:06:20 +00:00
Akira Hatanaka
dba6358adc Add a pattern for matching zero-store with 64-bit address. The pattern is enabled 
only when the target ABI is N64. 

llvm-svn: 146992
 2011-12-20 21:50:49 +00:00
Jim Grosbach
8978194025 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
llvm-svn: 146990
 2011-12-20 20:46:29 +00:00
Lang Hames
843255f890 Fix assert condition. 
llvm-svn: 146987
 2011-12-20 20:23:40 +00:00
Jakub Staszak
6f3beda2b4 Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo. 
llvm-svn: 146986
 2011-12-20 20:03:10 +00:00
Jim Grosbach
3f48367a1b ARM enable a few more tests. 
llvm-svn: 146985
 2011-12-20 20:03:00 +00:00
Devang Patel
a57e0b8f49 Add support to add named metadata operand. 
Patch by Andrew Wilkins!

llvm-svn: 146984
 2011-12-20 19:29:36 +00:00
Jim Grosbach
8156a5dcee ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
llvm-svn: 146983
 2011-12-20 19:21:26 +00:00
Evan Cheng
46b085721a ARM target code clean up. Check for iOS, not Darwin where it makes sense. 
llvm-svn: 146981
 2011-12-20 18:26:50 +00:00
Jason W Kim
139dd49440 First steps in ARM AsmParser support for .eabi_attribute and .arch 
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)

llvm-svn: 146977
 2011-12-20 17:38:12 +00:00
Elena Demikhovsky
b37883fe87 This is the second fix related to VZEXT_MOVL node. 
The failure that I see in the current version is:

LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
  0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
    0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
      0x18b9870: v4i64 = undef [ID=4]
      0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
        0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
          0x18b9770: i32 = TargetConstant<0> [ID=6]
      0x18b9970: i32 = Constant<0> [ID=3]
    0x18b9170: v2i64 = undef [ORD=1] [ID=1]
    0x18b9570: i32 = Constant<2> [ID=5]

llvm-svn: 146975
 2011-12-20 13:34:28 +00:00
Chandler Carruth
7564e8371a Begin teaching the X86 target how to efficiently codegen patterns that 
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.

The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.

llvm-svn: 146974
 2011-12-20 11:19:37 +00:00
Manuel Klimek
94bfd4f3fc Fixes a potential compilation error. 
Pulling the template implementation into the header to guarantee
that it's visible to all possible instantiations.

llvm-svn: 146973
 2011-12-20 11:04:23 +00:00
Manuel Klimek
9661304f32 Pulls the implementation of skip() into JSONParser. 
This is the first step towards migrating more of the parser
implementation into the parser class.

llvm-svn: 146971
 2011-12-20 10:42:52 +00:00
Manuel Klimek
8c643f1ae2 Fixing option for JSON benchmark broken since the change to size_t. 
llvm-svn: 146970
 2011-12-20 10:34:29 +00:00
Manuel Klimek
e08a021292 Addressing style issues in JSON parser. 
llvm-svn: 146968
 2011-12-20 09:26:26 +00:00
Chandler Carruth
1663697160 Fix up the CMake build for the new files added in r146960, they're 
likely to stay either way that discussion ends up resolving itself.

llvm-svn: 146966
 2011-12-20 08:42:11 +00:00
David Blaikie
0c4ffec904 Revert pragma clang suppressions that confuse GCC. (I'll worry about how to suppress/fix these problems properly when we figure out how to keep LLVM -Wweak-vtables clean) 
llvm-svn: 146965
 2011-12-20 08:22:49 +00:00
Nadav Rotem
682f1c2187 Add a few lines to the release notes: 
1. pointer-vector
2. type legalizer changes and vector-select
3. X86 ISA changes.

llvm-svn: 146964
 2011-12-20 08:02:50 +00:00
David Blaikie
576aba04f1 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 
llvm-svn: 146960
 2011-12-20 02:50:00 +00:00
Andrew Trick
a1c4f73f87 Unit test for r146950: LSR postinc expansion, PR11571. 
llvm-svn: 146951
 2011-12-20 01:43:20 +00:00
Andrew Trick
a2555fd695 LSR: Fix another corner case in expansion of postinc users. 
Fixes PR11571: Instruction does not dominate all uses

llvm-svn: 146950
 2011-12-20 01:42:24 +00:00
Bob Wilson
8439df9506 Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930. 
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers.  But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore.  Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early.  This also more accurately reflects
when the registers are clobbered.

llvm-svn: 146949
 2011-12-20 01:29:27 +00:00
Chris Lattner
f60c5dadf8 fix typo 
llvm-svn: 146940
 2011-12-20 01:11:37 +00:00
Dan Gohman
80dc86c550 Add a line to ReleaseNotes for half float. 
llvm-svn: 146939
 2011-12-20 01:10:56 +00:00
Jim Grosbach
3f5493c136 ARM assembly shifts by zero should be plain 'mov' instructions. 
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.

rdar://10604663

llvm-svn: 146937
 2011-12-20 00:59:38 +00:00
Chris Lattner
c1d9c0a2a3 Now that PR11464 is fixed, reapply the patch to fix PR11464, 
merging types by name when we can.  We still don't guarantee type name linkage
but we do it when obviously the right thing to do.  This makes LTO type names 
easier to read, for example.

llvm-svn: 146932
 2011-12-20 00:12:26 +00:00
Chris Lattner
998998b3e7 fix PR11464 by preventing the linker from mapping two different struct types from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all. 
llvm-svn: 146929
 2011-12-20 00:03:52 +00:00
Chris Lattner
151b0ec955 add a method to improve compatibility with SmallVector. 
llvm-svn: 146928
 2011-12-20 00:03:41 +00:00