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1784 Commits

Author SHA1 Message Date
Owen Anderson
3dd6c949a5 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. 
llvm-svn: 143208
 2011-10-28 18:02:13 +00:00
Jim Grosbach
72ab459378 Thumb2 ADD/SUB instructions encoding selection outside IT block. 
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481

llvm-svn: 143201
 2011-10-28 16:57:07 +00:00
NAKAMURA Takumi
2ea569c7e0 test/MC/AsmParser/2011-09-06-NoNewline.s: Add explicit -mtriple=i386. It uses X86 instruction. 
FIXME: Would it be reproduced without target-specific operands?
FIXME: Why run llvm-mc as the same input by 3 times?
llvm-svn: 143195
 2011-10-28 14:12:30 +00:00
Jim Grosbach
dac7815a91 ARM Allow 'q' registers in VLD/VST vector lists. 
Just treat it as if the constituent D registers where specified.

rdar://10348896

llvm-svn: 143167
 2011-10-28 00:06:50 +00:00
Owen Anderson
f22cd77ceb Add testcase for r143162. 
llvm-svn: 143163
 2011-10-27 22:54:14 +00:00
Kevin Enderby
837c1d56a2 Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and 
not depend on In32BitMode.  Use the sysexitq mnemonic for the version with the
REX.W prefix and only allow it only In64BitMode.  rdar://9738584

llvm-svn: 143112
 2011-10-27 17:40:41 +00:00
Jim Grosbach
4f7964293a Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix. 
rdar://10348844

llvm-svn: 143110
 2011-10-27 17:33:59 +00:00
Jim Grosbach
e1ec953149 Thumb2 t2MVNi assembly parsing to recognize ".w" suffix. 
rdar://10348584

llvm-svn: 143108
 2011-10-27 17:16:55 +00:00
Jim Grosbach
e3c6fa663f Thumb2 ldr pc-relative encoding fixes. 
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.

More of rdar://10348687

llvm-svn: 143068
 2011-10-26 22:22:01 +00:00
Jim Grosbach
fabe0f2f0b ARM assembly parsing and encoding for VLD1 with writeback. 
Four entry register lists.

llvm-svn: 142882
 2011-10-25 00:14:01 +00:00
Jim Grosbach
688186941f ARM assembly parsing and encoding for VLD1 w/ writeback. 
Three entry register list variation.

llvm-svn: 142876
 2011-10-24 23:26:05 +00:00
Jim Grosbach
cf4fba1dd0 ARM assembly parsing and encoding for VLD1 w/ writeback. 
One and two length register list variants.

llvm-svn: 142861
 2011-10-24 22:16:58 +00:00
Owen Anderson
b0e09258e7 Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. 
llvm-svn: 142817
 2011-10-24 18:04:29 +00:00
Jim Grosbach
0bb9a86fc7 Update test for r142801. 
llvm-svn: 142806
 2011-10-24 17:26:26 +00:00
Craig Topper
3cb62dca0f Add X86 SARX, SHRX, and SHLX instructions. 
llvm-svn: 142779
 2011-10-23 22:18:24 +00:00
Craig Topper
0e63b4485c Add X86 RORX instruction 
llvm-svn: 142741
 2011-10-23 07:34:00 +00:00
Craig Topper
7019cf1b80 Add X86 MULX instruction for disassembler. 
llvm-svn: 142738
 2011-10-23 00:33:32 +00:00
Jim Grosbach
d964cf8939 Assembly parsing for 4-register sequential variant of VLD2. 
llvm-svn: 142704
 2011-10-21 23:58:57 +00:00
Jim Grosbach
a6e536367e Assembly parsing for 2-register sequential variant of VLD2. 
llvm-svn: 142691
 2011-10-21 22:21:10 +00:00
Jim Grosbach
68dfc88f95 Assembly parsing for 4-register variant of VLD1. 
llvm-svn: 142682
 2011-10-21 20:35:01 +00:00
Jim Grosbach
2c1ca90ac9 Assembly parsing for 3-register variant of VLD1. 
llvm-svn: 142675
 2011-10-21 20:02:19 +00:00
Jim Grosbach
6bb38d0e97 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
 2011-10-21 18:54:25 +00:00
Owen Anderson
2021ad2133 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 
llvm-svn: 142626
 2011-10-20 22:23:58 +00:00
Owen Anderson
8067075218 Fix decoding tests for fixed MSR encodings. 
llvm-svn: 142624
 2011-10-20 22:01:48 +00:00
Owen Anderson
ffca195c01 Fix tests for corrected MSR encodings. 
llvm-svn: 142622
 2011-10-20 21:53:19 +00:00
Jim Grosbach
e9d1df8266 ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
llvm-svn: 142583
 2011-10-20 15:04:25 +00:00
Jim Grosbach
954465d59a Tidy up formatting. 
llvm-svn: 142582
 2011-10-20 14:57:47 +00:00
Jim Grosbach
972f26d936 ARM VTBX (one register) assembly parsing and encoding. 
llvm-svn: 142581
 2011-10-20 14:48:50 +00:00
Rafael Espindola
01d11bcdf0 Fix parsing of a line with only a # in it. 
llvm-svn: 142537
 2011-10-19 18:48:52 +00:00
Craig Topper
b1fa647871 Rename PEXTR to PEXT. Add intrinsics for BMI instructions. 
llvm-svn: 142480
 2011-10-19 07:48:35 +00:00
Jim Grosbach
6110df7008 Tidy up formatting. 
llvm-svn: 142422
 2011-10-18 21:09:01 +00:00
Jim Grosbach
de82cec744 Tidy up formatting. 
llvm-svn: 142421
 2011-10-18 21:08:16 +00:00
Jim Grosbach
f0d2d6bfc1 Enable more encoded immediate tests. 
llvm-svn: 142415
 2011-10-18 20:20:51 +00:00
Jim Grosbach
8c1298946c More vmov lane testcases. 
llvm-svn: 142414
 2011-10-18 20:19:48 +00:00
Jim Grosbach
ff8c26a53f ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142413
 2011-10-18 20:14:56 +00:00
Jim Grosbach
ed5cb526e2 ARM vmov assembly parsing for the lane index operand. 
llvm-svn: 142412
 2011-10-18 20:10:47 +00:00
Jim Grosbach
988b8dd4ce ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142389
 2011-10-18 18:27:07 +00:00
Owen Anderson
39a3d3305a Another failing encoding. 
llvm-svn: 142388
 2011-10-18 18:23:03 +00:00
Jim Grosbach
de8f8bec78 Fix NEON mul encoding tests. Wrong file contents previously. 
llvm-svn: 142387
 2011-10-18 18:14:55 +00:00
Jim Grosbach
2752e0b869 ARM vqdmulh assembly parsing for the lane index operand. 
llvm-svn: 142386
 2011-10-18 18:12:09 +00:00
Jim Grosbach
d2162f8c95 Remove duplicate test. 
llvm-svn: 142383
 2011-10-18 18:05:50 +00:00
Jim Grosbach
86d53ed3d4 Tidy up formatting. 
llvm-svn: 142382
 2011-10-18 18:05:16 +00:00
Jim Grosbach
b56577b650 ARM vmul assembly parsing for the lane index operand. 
llvm-svn: 142381
 2011-10-18 18:01:52 +00:00
Jim Grosbach
93213f0ca9 Tidy up. 
llvm-svn: 142380
 2011-10-18 18:01:09 +00:00
Owen Anderson
593bfe68d2 Add a few more testcases. 
llvm-svn: 142379
 2011-10-18 17:57:31 +00:00
Owen Anderson
77f405511d Add several FIXME cases for ARM encodings. 
llvm-svn: 142377
 2011-10-18 17:50:22 +00:00
Jim Grosbach
8c454cac49 Tests for 142365. 
llvm-svn: 142368
 2011-10-18 17:23:34 +00:00
Jim Grosbach
df6fb84ea5 Tidy up formatting. 
llvm-svn: 142367
 2011-10-18 17:22:53 +00:00
Jim Grosbach
031bb99231 ARM assembly parsing and encoding for VMOV.i64. 
llvm-svn: 142356
 2011-10-18 16:18:11 +00:00
Jim Grosbach
bcfb4ed53c ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
llvm-svn: 142321
 2011-10-18 00:22:00 +00:00