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199 Commits

Author SHA1 Message Date
Arnold Schwaighofer
0bfbfaf7e6 ARM sched model: Add divsion, loads, branches, vfp cvt 
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

Reapply of r183257. (Removed empty InstRW for division on swift)

llvm-svn: 183319
 2013-06-05 16:06:11 +00:00
Arnold Schwaighofer
59cf81c2e1 Revert series of sched model patches until I figure out what is going on. 
llvm-svn: 183273
 2013-06-04 22:35:17 +00:00
Arnold Schwaighofer
fe141a11f4 ARM sched model: Add divsion, loads, branches, vfp cvt 
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

llvm-svn: 183257
 2013-06-04 22:15:46 +00:00
Tim Northover
2a437cba0e ARM: add fstmx and fldmx instructions for assembly 
These instructions are deprecated oddities, but we still need to be able to
disassemble (and reassemble) them if and when they're encountered.

Patch by Amaury de la Vieuville.

llvm-svn: 183011
 2013-05-31 15:55:51 +00:00
Bob Wilson
ee6a40c517 Add LLVM support for Swift. 
llvm-svn: 164899
 2012-09-29 21:43:49 +00:00
Anton Korobeynikov
c0e610e681 fp16-to-fp32 conversion instructions are available in Thumb mode as well. 
Make sure the generic pattern is used.

llvm-svn: 162170
 2012-08-18 13:08:43 +00:00
Evan Cheng
625c0ca5ee Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows unaligned access. rdar://12091029 
llvm-svn: 161962
 2012-08-15 17:44:53 +00:00
Anton Korobeynikov
d13403fbd1 The names of VFP variants of half-to-float conversion instructions were 
reversed. This leads to wrong codegen for float-to-half conversion
intrinsics which are used to support storage-only fp16 type.
NEON variants of same instructions are fine.

llvm-svn: 161907
 2012-08-14 23:36:01 +00:00
Richard Barton
2bacde8589 Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time! 
llvm-svn: 159989
 2012-07-10 12:51:09 +00:00
Chad Rosier
b986265e3b Revert r159938 (and r159945) to appease the buildbots. 
llvm-svn: 159960
 2012-07-09 20:43:34 +00:00
Richard Barton
cb28956a79 Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) 
llvm-svn: 159938
 2012-07-09 16:41:33 +00:00
Lang Hames
662801dbc8 Add a missing llvm.fma -> VFNMS pattern to the ARM backend. 
llvm-svn: 158902
 2012-06-21 06:10:00 +00:00
Lang Hames
7d83af4ed0 Fix the order of the operands in the llvm.fma intrinsic patterns for ARM, 
<rdar://problem/11325085>.

llvm-svn: 155724
 2012-04-27 18:51:24 +00:00
Jim Grosbach
66edf44403 Tidy up. 80 columns, whitespace, et. al. 
llvm-svn: 155399
 2012-04-23 22:04:10 +00:00
Jim Grosbach
c935649d5c ARM some VFP tblgen'erated two-operand aliases. 
llvm-svn: 155178
 2012-04-20 00:15:00 +00:00
Evan Cheng
f138fb4599 Add more fused mul+add/sub patterns. rdar://10139676 
llvm-svn: 154484
 2012-04-11 06:59:47 +00:00
Evan Cheng
f9baff015d Clean up ARM fused multiply + add/sub support some more: rename some isel 
predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?

rdar://10139676

llvm-svn: 154480
 2012-04-11 05:33:07 +00:00
Evan Cheng
b5291aea18 Match (fneg (fma) to vfnma. rdar://10139676 
llvm-svn: 154469
 2012-04-11 01:21:25 +00:00
Evan Cheng
f9617f7f54 Handle llvm.fma.* intrinsics. rdar://10914096 
llvm-svn: 154439
 2012-04-10 21:40:28 +00:00
Jim Grosbach
99aef428f3 ARM divided syntax fmrx/fmxr mnemonics. 
llvm-svn: 152946
 2012-03-16 21:06:13 +00:00
Jim Grosbach
77151885af ARM vmrs system registers mvfr0 and mvfr1 handling. 
rdar://11058464

llvm-svn: 152881
 2012-03-16 00:27:18 +00:00
Jim Grosbach
3812c82b92 ARM case-insensitive checking for APSR_nzcv. 
rdar://11056591

llvm-svn: 152846
 2012-03-15 21:34:14 +00:00
Jim Grosbach
04f671dced ARM aliases for pre-unified syntax fcmpz[sd] mnemonics. 
rdar://11056647

llvm-svn: 152834
 2012-03-15 20:48:18 +00:00
Kristof Beyls
5f7d669c67 Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton. 
llvm-svn: 152814
 2012-03-15 17:50:29 +00:00
Lang Hames
a49054ac9c Split fpscr into two registers: FPSCR and FPSCR_NZCV. 
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.

llvm-svn: 152076
 2012-03-06 00:19:55 +00:00
Jim Grosbach
91314c2db6 ARM vpush/vpop assembler mnemonics accept an optional size suffix. 
rdar://10988114

llvm-svn: 152068
 2012-03-05 23:16:31 +00:00
Sebastian Pop
e6eeed8151 updated patch for the ARM fused multiply add/sub 
In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.

Patch by Ana Pazos <apazos@codeaurora.org>

llvm-svn: 152036
 2012-03-05 17:39:52 +00:00
Jia Liu
b077b6085d Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Anton Korobeynikov
76b0745f6c Add fused multiple+add instructions from VFPv4. 
Patch by Ana Pazos!

llvm-svn: 148658
 2012-01-22 12:07:33 +00:00
Jim Grosbach
a678ad9ecc ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). 
rdar://10558523

llvm-svn: 147189
 2011-12-22 22:19:05 +00:00
Jim Grosbach
5824007e4d Remove some bogus comments. 
llvm-svn: 147169
 2011-12-22 19:45:01 +00:00
Jim Grosbach
970c4cab9e ARM pre-UAL aliases. fcmp[sd]. 
llvm-svn: 147158
 2011-12-22 19:20:45 +00:00
Jim Grosbach
7d31680e2d ARM VFP optional data type on VMOV GPR<-->SPR. 
llvm-svn: 147104
 2011-12-21 23:24:15 +00:00
Jim Grosbach
f9910809c5 ARM VFP pre-UAL mnemonic aliases for fmul[sd]. 
llvm-svn: 146892
 2011-12-19 19:43:50 +00:00
Jim Grosbach
6e9471925b ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd]. 
llvm-svn: 146887
 2011-12-19 19:02:41 +00:00
Jim Grosbach
dfec87fe2f ARM NEON two-operand aliases for VQDMULH. 
llvm-svn: 146514
 2011-12-13 20:40:37 +00:00
Jim Grosbach
1738a66371 ARM add some more pre-UAL VFP mnemonics for convenience when porting old code. 
llvm-svn: 146508
 2011-12-13 20:13:48 +00:00
Jim Grosbach
9e5ef02adb ARM add more 'gas' compatibility aliases for NEON instructions. 
llvm-svn: 146507
 2011-12-13 20:08:32 +00:00
Jim Grosbach
ece09e5e6b ARM add some more pre-UAL VFP mnemonics for convenience when porting old code. 
llvm-svn: 146300
 2011-12-10 00:01:02 +00:00
Jim Grosbach
2356c1f141 ARM add some pre-UAL VFP mnemonics for convenience when porting old code. 
llvm-svn: 146296
 2011-12-09 23:34:09 +00:00
Jim Grosbach
5f3c519248 ARM convenience aliases for VSQRT. 
llvm-svn: 146201
 2011-12-08 22:51:25 +00:00
Jim Grosbach
597cb99d62 ARM VFP support 'fmrs/fmsr' aliases for 'vldr' 
llvm-svn: 146116
 2011-12-08 00:52:55 +00:00
Jim Grosbach
fa73a483a9 ARM VFP support 'flds/fldd' aliases for 'vldr' 
llvm-svn: 146115
 2011-12-08 00:49:29 +00:00
Jim Grosbach
a740cc6bc9 ARM tidy up and remove no longer needed InstAlias definitions. 
The TokenAlias handling of data type suffices renders these unnecessary.

llvm-svn: 146010
 2011-12-07 01:50:36 +00:00
Jim Grosbach
d573473cb8 ARM VFP assembly parsing for VADD and VSUB two-operand forms. 
llvm-svn: 144710
 2011-11-15 22:15:10 +00:00
Jim Grosbach
3c205132ff ARM size suffix on VFP single-precision 'vmov' is optional. 
rdar://10435114

llvm-svn: 144698
 2011-11-15 21:18:35 +00:00
Jim Grosbach
8987b277cb ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. 
Yet more of rdar://10435076.

llvm-svn: 144691
 2011-11-15 20:29:42 +00:00
Jim Grosbach
f0690cd90c ARM assembly parsing for two-operand form of 'mul' instruction. 
rdar://10449856.

llvm-svn: 144689
 2011-11-15 20:14:51 +00:00
Jim Grosbach
4a2f107b04 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

llvm-svn: 144583
 2011-11-14 23:03:21 +00:00
Jim Grosbach
009733c9e4 ARM assembly parsing type suffix options for VLDR/VSTR. 
rdar://10435076

llvm-svn: 144575
 2011-11-14 22:28:39 +00:00