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Commit Graph

168707 Commits

Author SHA1 Message Date
Sid Manning
7b4c6df667 Revert [Hexagon] Add support for getRegisterByName.
Support required to build the Hexagon Linux kernel.

llvm-svn: 341331
2018-09-03 17:59:10 +00:00
Florian Hahn
dc2cbc6f8d [SLC] Support expanding pow(x, n+0.5) to x * x * ... * sqrt(x)
Reviewers: evandro, efriedma, spatel

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D51435

llvm-svn: 341330
2018-09-03 17:37:39 +00:00
Brian Gesiak
edc222b081 Re-push "[Option] Fix PR37006 prefix choice in findNearest"
Summary:
Original changeset (https://reviews.llvm.org/D46776) by @modocache. It was
reverted after the PS4 bot failed.

The issue has been determined to be with the way the PS4 SDK handles this
particular option. https://reviews.llvm.org/D50410 removes this test, so we
can push this again.

Patch by Arnaud Coomans!

Reviewers: cfe-commits, modocache

Reviewed By: modocache

Differential Revision: https://reviews.llvm.org/D50515

llvm-svn: 341329
2018-09-03 17:30:57 +00:00
Andrea Di Biagio
98fc61c0dc [X86] Remove wrong ReadAdvance from multiclass sse_fp_unop_s.
A ReadAdvance was incorrectly added to the SchedReadWrite list associated with
the following SSE instructions:

sqrtss
sqrtsd
rsqrtss
rcpss

As a consequence, a wrong operand latency was computed for the register operand
used as the base address of the folded load operand.

This patch removes the wrong ReadAdvance, and updates the llvm-mca test cases.
There is still a problem with correctly modeling partial register writes on XMM
registers This other problem is currently tracked here:
https://bugs.llvm.org/show_bug.cgi?id=38813

Differential Revision: https://reviews.llvm.org/D51542

llvm-svn: 341326
2018-09-03 16:47:34 +00:00
Argyrios Kyrtzidis
048516922a Add header guards to some headers that are missing them
Also adjust some of dsymutil's headers to put the header guards at the top,
otherwise the compiler will not recognize them as header guards.

llvm-svn: 341323
2018-09-03 16:22:05 +00:00
Matt Arsenault
a4c1394dea DAG: Handle extract_vector_elt in isKnownNeverNaN
llvm-svn: 341317
2018-09-03 14:01:03 +00:00
Nico Weber
ec4bd508f5 Rename a few unittests/.../Foo.cpp files to FooTest.cpp
The convention for unit test sources is that they're called FooTest.cpp.

No behavior change.
https://reviews.llvm.org/D51579

llvm-svn: 341313
2018-09-03 12:43:26 +00:00
Jonas Devlieghere
77cd9699b3 [DebugInfo] Have the verifier accept missing linkage names.
According to the standard, for the .debug_names (the "dwarf accelerator
tables"):

> If a subprogram or inlined subroutine is included, and has a
> DW_AT_linkage_name attribute, there will be an additional index entry
> for the linkage name.

For Swift we generate DW_structure_types with a linkage name and the
verifier was incorrectly rejecting this. This patch fixes that by only
considering the linkage name in those particular cases. The test is the
"reduced" debug info of the failing swift test on swift.org.

Differential revision: https://reviews.llvm.org/D51420

llvm-svn: 341311
2018-09-03 12:12:17 +00:00
Martin Storsjo
92f0889ba0 [AArch64] Simplify code in LowerGlobalAddress. NFCI.
When initial support for dllimport was added for aarch64 in
SVN r316555, ClassifyGlobalReference didn't set the MO_DLLIMPORT
flag - that was only completed in SVN r323810. Reuse the return
value from ClassifyGlobalReference for this purpose as well.

llvm-svn: 341310
2018-09-03 11:59:23 +00:00
Daniel Cederman
02244eb251 [Sparc] allow tls_add/tls_call syntax in assembler parser
Summary: Removing unneeded isCodeGenOnly from tls-specific
instructions - TLS_ADD/TLS_LD/TLS_LDX/TLS_CALL.

Author: fedor.sergeev

Reviewers: jyknight, fedor.sergeev

Reviewed By: jyknight

Subscribers: dcederman, brad, llvm-commits

Differential Revision: https://reviews.llvm.org/D36463

llvm-svn: 341308
2018-09-03 10:38:12 +00:00
Sander de Smalen
1aab3dec99 Fix issue introduced by r341301 that broke buildbot.
A condition in isSpillInstruction() updates a small vector rather
than the 'FI' by-ref parameter, which was used in a subsequent
call to 'isSpillSlotObjectIndex()'. This patch fixes the condition
to check the FIs in the vector instead.

llvm-svn: 341305
2018-09-03 10:23:34 +00:00
Simon Pilgrim
9b5b83cbbe Remove unnecessary semicolon to silence -Wpedantic warning. NFCI.
llvm-svn: 341303
2018-09-03 10:17:25 +00:00
Carlos Alberto Enciso
134a70e24b Test commit.
Revert change done in r341297. NFC.

Differential Revision: https://reviews.llvm.org/D51583

llvm-svn: 341302
2018-09-03 09:41:43 +00:00
Sander de Smalen
9de07a620d Extend hasStoreToStackSlot with list of FI accesses.
For instructions that spill/fill to and from multiple frame-indices
in a single instruction, hasStoreToStackSlot and hasLoadFromStackSlot
should return an array of accesses, rather than just the first encounter
of such an access.

This better describes FI accesses for AArch64 (paired) LDP/STP
instructions.

Reviewers: t.p.northover, gberry, thegameg, rengolin, javed.absar, MatzeB

Reviewed By: MatzeB

Differential Revision: https://reviews.llvm.org/D51537

llvm-svn: 341301
2018-09-03 09:15:58 +00:00
Carlos Alberto Enciso
cb0fa9d8de Test commit - adding a new line.
llvm-svn: 341297
2018-09-03 08:26:37 +00:00
Kristina Brooks
f396ffd72d [MC] - ConstantPools.cpp: Style consistency, remove redundant braces. NFC.
Remove braces around two, single statement "if" blocks in line with rest 
of the file and the general LLVM code style. NFC, testing commit access.

llvm-svn: 341294
2018-09-03 03:48:39 +00:00
QingShan Zhang
089a27de75 [PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8
When doing some instruction scheduling work, we noticed some missing itineraries.
Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, 
because we can still get same latency due to default values.

With machine scheduler, however, itineraries will have impact to scheduling.
eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class.
And most of the instruction class with itineraries will have NumMicroOps default to 1.

This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, 
then causing different scheduling or suboptimal scheduling further.

Patch by jsji (Jinsong Ji)
Differential Revision: https://reviews.llvm.org/D51506

llvm-svn: 341293
2018-09-03 03:14:29 +00:00
Sanjay Patel
0fbf3b3c47 [InstCombine] allow not+sub fold for arbitrary vector constants
The fold was implemented for the general case but use-limitation,
but the later constant version which didn't check uses was only
matching splat constants.

llvm-svn: 341292
2018-09-02 19:31:45 +00:00
Sanjay Patel
baac80eea8 [InstCombine] move/add tests for not+sub; NFC
llvm-svn: 341291
2018-09-02 19:18:13 +00:00
Hsiangkai Wang
03ff0042c1 Revert "[DebugInfo] Fix bug in LiveDebugVariables."
This reverts commit 8f548ff2a1819e1bc051e8218584f1a3d2cf178a.

buildbot failure in LLVM on clang-ppc64be-linux
http://lab.llvm.org:8011/builders/clang-ppc64le-linux/builds/19765

llvm-svn: 341290
2018-09-02 16:35:42 +00:00
Hsiangkai Wang
45bb59e001 [DebugInfo] Fix bug in LiveDebugVariables.
In lib/CodeGen/LiveDebugVariables.cpp, it uses std::prev(MBBI) to
get DebugValue's SlotIndex. However, the previous instruction may be
also a debug instruction. It could not use a debug instruction to query
SlotIndex in mi2iMap.

Scan all debug instructions and use the first debug instruction to query
SlotIndex for following debug instructions. Only handle DBG_VALUE in
handleDebugValue().

Differential Revision: https://reviews.llvm.org/D50621

llvm-svn: 341289
2018-09-02 15:57:22 +00:00
Sanjay Patel
bee81c359d [Reassociate] swap binop operands to increase factoring potential
If we have a pair of binops feeding another pair of binops, rearrange the operands so 
the matching pair are together because that allows easy factorization folds to happen 
in instcombine:
((X << S) & Y) & (Z << S) --> ((X << S) & (Z << S)) & Y (reassociation)

--> ((X & Z) << S) & Y (factorize shift from 'and' ops optimization)

This is part of solving PR37098:
https://bugs.llvm.org/show_bug.cgi?id=37098

Note that there's an instcombine version of this patch attached there, but we're trying
to make instcombine have less responsibility to improve compile-time efficiency.

For reasons I still don't completely understand, reassociate does this kind of transform
sometimes, but misses everything in my motivating cases.

This patch on its own is gluing an independent cleanup chunk to the end of the existing 
RewriteExprTree() loop. We can build on it and do something stronger to better order the 
full expression tree like D40049. That might be an alternative to the proposal to add a 
separate reassociation pass like D41574.

Differential Revision: https://reviews.llvm.org/D45842

llvm-svn: 341288
2018-09-02 14:22:54 +00:00
Roman Lebedev
713057a782 [DAGCombine] optimizeSetCCOfSignedTruncationCheck(): handle inverted pattern
Summary:
A follow-up for D49266 / rL337166 + D49497 / rL338044.

This is still the same pattern to check for the [lack of]
signed truncation, but in this case the constants and the predicate
are negated.

https://rise4fun.com/Alive/BDV
https://rise4fun.com/Alive/n7Z

Reviewers: spatel, craig.topper, RKSimon, javed.absar, efriedma, dmgreen

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D51532

llvm-svn: 341287
2018-09-02 13:56:22 +00:00
Lang Hames
1be900b4ae clang-format r341282.
llvm-svn: 341283
2018-09-02 01:29:29 +00:00
Lang Hames
2bc712fec3 [ORC] Tidy up JITSymbolFlags to remove the need for some explicit static_casts.
Removes the implicit conversion to the underlying type for
JITSymbolFlags::FlagNames and replaces it with some bitwise and comparison
operators.

llvm-svn: 341282
2018-09-02 01:28:26 +00:00
Matt Davis
864546a86b [llvm-mca] Fix typo in debug output. NFC.
llvm-svn: 341281
2018-09-01 18:32:33 +00:00
Sanjay Patel
4811bf5b98 [InstCombine] simplify code for 'or' fold
This is no-outwardly-visible-change intended, so no test.
But the code is smaller and more efficient. The check for
a 'not' op is intended to avoid the expensive value tracking
call when it should not be necessary, and it might prevent
infinite looping when we resurrect:
rL300977

llvm-svn: 341280
2018-09-01 15:08:59 +00:00
Dylan McKay
da766b82ec [AVR] Redefine the 'LSL' instruction as an alias of 'ADD'
The 'LSL Rd' instruction is equivalent to 'ADD Rd, Rd'.

llvm-svn: 341278
2018-09-01 12:23:00 +00:00
Dylan McKay
6b46fe6f7f [AVR] Redefine the 'SBR' instruction as an alias
This fixes a TableGen warning about duplicate bit patterns.

SBR
===

This is an alias of 'ORI Rd, K'.

llvm-svn: 341277
2018-09-01 12:22:54 +00:00
Dylan McKay
797d2851fb [AVR] Define the TST instruction as an alias of AND
The 'tst Rd' instruction is equivalent to 'and Rd, Rd'.

llvm-svn: 341276
2018-09-01 12:22:50 +00:00
Dylan McKay
57df109cc6 [AVR] Define the ROL instruction as an alias of ADC
The 'rol Rd' instruction is equivalent to 'adc Rd'.

This caused compile warnings from tablegen because of conflicting bits
shared between each instruction.

llvm-svn: 341275
2018-09-01 12:22:07 +00:00
Tom Stellard
a32bb80a83 AMDGPU/GlobalISel: Define instruction mapping for G_SELECT
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D49737

llvm-svn: 341271
2018-09-01 02:41:19 +00:00
Sanjin Sijaric
1c37809eaa Make HasWinCFI a plain bool instead of Optional<bool>
Summary:
Reid suggested making HasWinCFI a plain bool defaulting to false in D50288.

It's needed in order to add HasWinCFI to MIRPrinter.  Otherwise, we'll get the
assertion:

HasWinCFI.hasValue() && "HasWinCFI not set yet!"'

Also, a few ARM64 Windows test cases will fail with the same assert if the ARM64
MCLayer part of EH work (D50166) goes in before the frame lowering part that
sets HasWinCFI (D50288 as of now).

Reviewers: rnk, mstorsjo, hans, javed.absar

Reviewed By: rnk

Subscribers: kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D51560

llvm-svn: 341270
2018-09-01 00:33:43 +00:00
Zhaoshi Zheng
4e2657ae57 [Constant Hoisting] Hoisting Constant GEP Expressions
Leverage existing logic in constant hoisting pass to transform constant GEP
expressions sharing the same base global variable. Multi-dimensional GEPs are
rewritten into single-dimensional GEPs.

Differential Revision: https://reviews.llvm.org/D51396

llvm-svn: 341269
2018-09-01 00:04:56 +00:00
Jessica Paquette
a683ce17f2 Fix typo in size remarks for module passes
ModuleCount = InstrCount was incorrect. It should have been
InstrCount = ModuleCount. This was making it emit an extra, incorrect remark
for Print Module IR.

The test didn't catch this, because it didn't ensure that the only remark
output was from the desired pass. So, it was possible to have an extra remark
come through and not fail. Updated the test so that we ensure that the last
remark that's output comes from the desired pass. This is done by ensuring
that whatever is being read after the last remark is YAML output rather than
some incorrect garbage.

llvm-svn: 341267
2018-08-31 22:43:41 +00:00
Stanislav Mekhanoshin
cca54c5f90 [AMDGPU] Split v32i32 loads
Differential Revision: https://reviews.llvm.org/D51555

llvm-svn: 341266
2018-08-31 22:43:36 +00:00
Krzysztof Parzyszek
15030e916f [Hexagon] Don't access non-existent instructions
llvm-svn: 341264
2018-08-31 22:10:04 +00:00
Matthias Braun
fd5877ed05 Revamp test-suite documentation
- Remove duplication: Both TestingGuide and TestSuiteMakefileGuide
  would give a similar overview over the test-suite.
- Present cmake/lit as the default/normal way of running the test-suite:
- Move information about the cmake/lit testsuite into the new
  TestSuiteGuide.rst file. Mark the remaining information in
  TestSuiteMakefilesGuide.rst as deprecated.
- General simplification and shorting of language.
- Remove paragraphs about tests known to fail as everything should pass
  nowadays.
- Remove paragraph about zlib requirement; it's not required anymore
  since we copied a zlib source snapshot into the test-suite.
- Remove paragraph about comparison with "native compiler". Correctness is
  always checked against reference outputs nowadays.
- Change cmake/lit quickstart section to recommend `pip` for installing
  lit and use `CMAKE_C_COMPILER` and a cache file in the example as that
  is what most people will end up doing anyway. Also a section about
  compare.py to quickstart.
- Document `Bitcode` and `MicroBenchmarks` directories.
- Add section with commonly used cmake configuration options.
- Add section about showing and comparing result files via compare.py.
- Add section about using external benchmark suites.
- Add section about using custom benchmark suites.
- Add section about profile guided optimization.
- Add section about cross-compilation and running on external devices.

Differential Revision: https://reviews.llvm.org/D51465

llvm-svn: 341260
2018-08-31 21:47:01 +00:00
Craig Topper
9c66dc8201 [X86] Add intrinsics for KTEST instructions.
These intrinsics use the same implementation as PTEST intrinsics, but use vXi1 vectors.

New clang builtins will be accompanying them shortly.

llvm-svn: 341259
2018-08-31 21:31:53 +00:00
Jessica Paquette
77c57aa86c [NFC] Optionally pass a function to emitInstrCountChangedRemark
In basic block, loop, and function passes, we already have a function that
we can use to emit optimization remarks. We can use that instead of searching
the module for the first suitable function (that is, one that contains at
least one basic block.)

llvm-svn: 341253
2018-08-31 20:54:37 +00:00
Jessica Paquette
7550fc6490 [NFC] Check if P is a pass manager on entry to emitInstrCountChangedRemark
There's no point in finding a function to use for remark output when we're
not going to emit anything.

llvm-svn: 341252
2018-08-31 20:51:54 +00:00
Jessica Paquette
203bc40494 [NFC] Pass the instruction delta to emitInstrCountChangedRemark
Instead of counting the size of the entire module every time we run a pass,
pass along a delta instead and use that to emit the remark.

This means we only have to use (on average) smaller IR units to calculate
instruction counts. E.g, in a BB pass, we only need to look at the delta of
the BB instead of the delta of the entire module.

6/6

(This improved compile time for size remarks on sqlite3 + O2 significantly)

llvm-svn: 341250
2018-08-31 20:20:57 +00:00
Jessica Paquette
055a51b8ad [NFC] Pre-calculate SCC IR counts in size remarks.
Same vein as the previous commits. Pre-calculate the size of
the module and use that to decide if we're going to emit a
remark.

This one comes with a FIXME and TODO. First off, CallGraphSCC
and CallGraphNode don't have a getInstructionCount function. So,
for now, we do the same thing as in a module pass.

Second off, we're not really saving anything here yet, because
as before, I need to change emitInstrCountChangedRemark to take
in a delta. Keeping the patches small though, so that's coming up
next.

5/6

llvm-svn: 341249
2018-08-31 20:20:56 +00:00
Jessica Paquette
2db1350557 [NFC] Pre-calculate module IR counts in size remarks.
Same as the previous NFC commits in the same vein.

This one introduces a TODO. I'm going to change emitInstrCountChangedRemark
so that it takes in a delta. Since the delta isn't necessary yet, it's not
there. For now, this means that we're calculating the size of the module
twice.

Just done separately to keep the patches small.

4/6

llvm-svn: 341248
2018-08-31 20:20:55 +00:00
Jessica Paquette
19d95db4ce [NFC] Pre-calculate loop IR counts in size remarks.
Another commit reducing compile time in size remarks.

Cache the size of the module and loop, and update values based
off of deltas instead. Avoid recalculating the size of the
whole module whenever possible.

3/6

llvm-svn: 341247
2018-08-31 20:20:54 +00:00
Jessica Paquette
8e00273b91 [NFC] Pre-calculate basic block IR counts in size remarks.
Size remarks are slow due to lots of recalculation of the module.

This is similar to the previous commit. Cache the size of the module and
update counts in basic block passes based off a less-expensive delta.

2/6

llvm-svn: 341246
2018-08-31 20:20:53 +00:00
Jessica Paquette
576c480097 [NFC] Pre-calculate function IR counts in size remarks.
Size remarks are slow due to lots of recalculation of the module.

Pre-calculate the module size and initial function size for a remark. Use
deltas calculated using the less-expensive function IR count to update the
module counts for Function passes.

1/6

llvm-svn: 341245
2018-08-31 20:19:41 +00:00
Tom Stellard
ef5a14b22c lit: Use sys.executable for executing builtin commands
Summary:
The python executable may not exist on all systems so use sys.executable
instead.

Reviewers: ddunbar, stella.stamenova

Subscribers: delcypher, llvm-commits

Differential Revision: https://reviews.llvm.org/D51511

llvm-svn: 341244
2018-08-31 20:15:31 +00:00
Dean Michael Berris
a648d5fa32 [XRay] Update RecordInitializer for PIDRecord
Since we changed the storage for the PID in PIDRecord instances, we need
to also update the way we load the data from a DataExtractor through the
RecordInitializer.

llvm-svn: 341243
2018-08-31 20:02:55 +00:00
Dean Michael Berris
5bd013d85b [XRay] Use correct type for PID records
Previously we've been reading and writing the wrong types which only
worked in little endian implementations. This time we're writing the
same typed values the runtime is using, and reading them appropriately
as well.

llvm-svn: 341241
2018-08-31 19:32:46 +00:00