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6018 Commits

Author SHA1 Message Date
Silviu Baranga
7bdfb9e34d Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM 
llvm-svn: 153251
 2012-03-22 13:24:43 +00:00
Silviu Baranga
c03971d4b1 Added soft fail cases for the disassembler when decoding MUL instructions on ARM. 
llvm-svn: 153250
 2012-03-22 13:14:39 +00:00
Kevin Enderby
e64335b34a Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test 
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .

llvm-svn: 153218
 2012-03-21 20:54:32 +00:00
Evan Cheng
4dfb298aac Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and t2PseudoExpand. 
llvm-svn: 153135
 2012-03-20 21:28:05 +00:00
Matt Beaumont-Gay
0702af872e remove unused variable 
llvm-svn: 153116
 2012-03-20 19:52:05 +00:00
Bob Wilson
52b3ad9532 Require a base pointer for stack realignment when SP may vary dynamically. 
ARMBaseRegisterInfo::canRealignStack was checking for variable-sized objects
but not for stack adjustments around calls.  Use hasReservedCallFrame() to
check for both.  The hasBasePointer function was already correctly checking
both conditions, so the effect of this was that a base pointer would be used
without checking whether the base pointer register could be reserved. I don't
have a small testcase for this.

<rdar://problem/11075906>

llvm-svn: 153110
 2012-03-20 19:28:25 +00:00
Bob Wilson
4fb4d4c6e0 Remove some redundant checks. 
ARMFrameLowering::hasReservedCallFrame is already checking for variable
sized objects, so there's no point in checking it twice.

llvm-svn: 153109
 2012-03-20 19:28:22 +00:00
Kevin Enderby
b87e1e0bfd Fix assembling ARM vst2 instructions with double-spaced registers. 
llvm-svn: 153099
 2012-03-20 17:41:51 +00:00
Jim Grosbach
b562c4f2fa ARM non-scattered MachO relocations for movw/movt. 
Needed when building -mdynamic-no-pic code.

rdar://10459256

llvm-svn: 153097
 2012-03-20 17:25:45 +00:00
Silviu Baranga
d20ed770e5 The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 
llvm-svn: 153089
 2012-03-20 15:54:56 +00:00
Richard Barton
25f44c807b Test Commit - add a newline 
llvm-svn: 153083
 2012-03-20 10:50:35 +00:00
Jim Grosbach
0ca6b4a15d ARM branch relaxation for unconditional t1 branches. 
rdar://11059157

llvm-svn: 153055
 2012-03-19 21:32:32 +00:00
Jim Grosbach
65c7d4dab9 ARM assembly, accept optional '#' on lane index number. 
rdar://11057160

llvm-svn: 153053
 2012-03-19 20:39:53 +00:00
Anton Korobeynikov
ccc669ff8f Perform mul combine when multiplying wiht negative constants. 
Patch by Weiming Zhao!
This fixes PR12212

llvm-svn: 153049
 2012-03-19 19:19:50 +00:00
Craig Topper
0534d071b7 Reorder includes to match coding standards. Fix an issue or two exposed by that. 
llvm-svn: 152978
 2012-03-17 07:33:42 +00:00
Bill Wendling
b427a9f177 Check if we can handle the arguments of a call (and therefore the call) in 
fast-isel before emitting code. If the program bails after code was emitted,
then it could lead to the stack being adjusted more than once (two
CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This
leads to general badness and gnashing of teeth.
<rdar://problem/11050630>

llvm-svn: 152959
 2012-03-16 23:11:07 +00:00
Jim Grosbach
7ab12a079f ARM fix silly typo in optional operand alias. 
rdar://11065671

llvm-svn: 152954
 2012-03-16 22:18:29 +00:00
Jim Grosbach
99aef428f3 ARM divided syntax fmrx/fmxr mnemonics. 
llvm-svn: 152946
 2012-03-16 21:06:13 +00:00
Jim Grosbach
af19922301 ARM ldm/stm register lists can be out of order. 
It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.

rdar://11064740

llvm-svn: 152943
 2012-03-16 20:48:38 +00:00
Jim Grosbach
a5d57ea09e ARM optional operand on MRC/MCR assembly instructions. 
rdar://11058464

llvm-svn: 152883
 2012-03-16 00:45:58 +00:00
Jim Grosbach
77151885af ARM vmrs system registers mvfr0 and mvfr1 handling. 
rdar://11058464

llvm-svn: 152881
 2012-03-16 00:27:18 +00:00
Jim Grosbach
e821ce3e5f Remove inadvertant commit. 
llvm-svn: 152870
 2012-03-15 23:00:30 +00:00
Chad Rosier
e007850778 [fast-isel] Address Eli's comments for r152847. Specifically, add a test case 
and still allow immediate encoding, just not with cmn.
rdar://11038907

llvm-svn: 152869
 2012-03-15 22:54:20 +00:00
Chad Rosier
103b276e74 [fast-isel] Don't try to encode LONG_MIN using cmn instructions. 
rdar://11038907

llvm-svn: 152847
 2012-03-15 21:40:23 +00:00
Jim Grosbach
3812c82b92 ARM case-insensitive checking for APSR_nzcv. 
rdar://11056591

llvm-svn: 152846
 2012-03-15 21:34:14 +00:00
Jim Grosbach
04f671dced ARM aliases for pre-unified syntax fcmpz[sd] mnemonics. 
rdar://11056647

llvm-svn: 152834
 2012-03-15 20:48:18 +00:00
Lang Hames
7918b0b225 Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints on 
register allocation by allowing all 32 D-registers to be used. Patch by Cameron
Zwarich.

llvm-svn: 152824
 2012-03-15 18:49:02 +00:00
Kristof Beyls
5f7d669c67 Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton. 
llvm-svn: 152814
 2012-03-15 17:50:29 +00:00
Bob Wilson
a0d2185fe0 Switch to unified syntax for VFP instructions in inline assembly. 
<rdar://problem/11024696>

llvm-svn: 152548
 2012-03-12 06:15:36 +00:00
Craig Topper
df2bf795d6 Convert more static tables of registers used by calling convention to uint16_t to reduce space. 
llvm-svn: 152538
 2012-03-11 07:57:25 +00:00
Craig Topper
c83a2b1ac0 Use uint16_t to store registers and opcode in static tables in the target specific backends. 
llvm-svn: 152537
 2012-03-11 07:16:55 +00:00
Craig Topper
79f1e75059 Use uint16_t to store instruction implicit uses and defs. Reduces static data. 
llvm-svn: 152301
 2012-03-08 08:22:45 +00:00
Jim Grosbach
6c4a2c8050 ARM don't use MCRelaxAll, as it's not safe on ARM. 
The ARM code generator makes aggressive assumptions about the encodings
being selected for branches which MCRelaxAll invalidates.

rdar://11006355

llvm-svn: 152268
 2012-03-08 00:07:52 +00:00
Chad Rosier
07b6e758e1 [fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point 
condition flags to CPSR.  This allows us to simplify SelectCmp.
Patch by Zonr Chang <zonr.xchg@gmail.com>.

llvm-svn: 152243
 2012-03-07 20:59:26 +00:00
Jim Grosbach
d0770582f9 ARM pre-v6 assembly parsing for umull/smull. 
llvm-svn: 152188
 2012-03-07 01:09:17 +00:00
Jim Grosbach
dbeec050c2 ARM pre-v6 alias for 'nop' to 'mov r0, r0' 
llvm-svn: 152185
 2012-03-07 00:52:41 +00:00
Jim Grosbach
9ef7f069b5 Tidy up. Remove dead code that slipped into previous commit. 
llvm-svn: 152184
 2012-03-07 00:52:39 +00:00
Jim Grosbach
3b5f99f716 ARM more NEON VLD/VST composite physical register refactoring. 
Register pair, all lanes subscripting.

llvm-svn: 152157
 2012-03-06 23:10:38 +00:00
Jim Grosbach
a3eeee8a91 ARM refactor more NEON VLD/VST instructions to use composite physregs 
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.

llvm-svn: 152150
 2012-03-06 22:01:44 +00:00
Jim Grosbach
63e971ffae Tidy up. Kill some dead code. 
llvm-svn: 152131
 2012-03-06 18:59:19 +00:00
Jakob Stoklund Olesen
f772e5e379 Allow the same types in DPair as in QPR. 
llvm-svn: 152129
 2012-03-06 18:44:11 +00:00
Kevin Enderby
64d11852dd Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. 
llvm-svn: 152127
 2012-03-06 18:33:12 +00:00
Jakob Stoklund Olesen
d4e1cb591a Add <imp-def> operands when reloading into physregs. 
When an instruction only writes sub-registers, it is still necessary to
add an <imp-def> operand for the super-register.  When reloading into a
virtual register, rewriting will add the operand, but when loading
directly into a virtual register, the <imp-def> operand is still
necessary.

llvm-svn: 152095
 2012-03-06 02:48:17 +00:00
Lang Hames
a49054ac9c Split fpscr into two registers: FPSCR and FPSCR_NZCV. 
The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.

llvm-svn: 152076
 2012-03-06 00:19:55 +00:00
Jim Grosbach
91314c2db6 ARM vpush/vpop assembler mnemonics accept an optional size suffix. 
rdar://10988114

llvm-svn: 152068
 2012-03-05 23:16:31 +00:00
Jim Grosbach
a6b09b4691 ARM Refactor VLD/VST spaced pair instructions. 
Use the new composite physical registers.

llvm-svn: 152063
 2012-03-05 21:43:40 +00:00
Jim Grosbach
d0fb2e7c99 ARM Remove a bit of dead code. 
llvm-svn: 152061
 2012-03-05 21:09:58 +00:00
Jim Grosbach
fdfaed95ae ARM refactor away a bunch of VLD/VST pseudo instructions. 
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.

llvm-svn: 152045
 2012-03-05 19:33:30 +00:00
Jim Grosbach
2eea383b12 Make MCRegisterInfo available to the the MCInstPrinter. 
Used to allow context sensitive printing of super-register or sub-register
references.

llvm-svn: 152043
 2012-03-05 19:33:20 +00:00
Sebastian Pop
e6eeed8151 updated patch for the ARM fused multiply add/sub 
In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.

Patch by Ana Pazos <apazos@codeaurora.org>

llvm-svn: 152036
 2012-03-05 17:39:52 +00:00