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Author SHA1 Message Date
Rafael Espindola
b2e09adc62 Merge IsFixupFullyResolved and IsSymbolRefDifferenceFullyResolved. We now 
have a single point where targets test if a relocation is needed.

llvm-svn: 122549
 2010-12-24 21:22:02 +00:00
Benjamin Kramer
49e40d4c4b MemCpyOpt: Turn memcpys from a constant into a memset if possible. 
This allows us to compile "int cst[] = {-1, -1, -1};" into
  movl  $-1, 16(%rsp)
  movq  $-1, 8(%rsp)
instead of
  movl  _cst+8(%rip), %eax
  movl  %eax, 16(%rsp)
  movq  _cst(%rip), %rax
  movq  %rax, 8(%rsp)

llvm-svn: 122548
 2010-12-24 21:17:12 +00:00
Daniel Dunbar
592854a10a MC/Mach-O/ARM: Start handling some Thumb branches. 
llvm-svn: 122547
 2010-12-24 16:41:46 +00:00
Andrew Trick
dfa31b1cf9 Minor cleanup related to my latest scheduler changes. 
llvm-svn: 122545
 2010-12-24 07:10:19 +00:00
Andrew Trick
c926e98fc7 Fix a few cases where the scheduler is not checking for phys reg copies. The scheduling node may have a NULL DAG node, yuck. 
llvm-svn: 122544
 2010-12-24 06:46:50 +00:00
Jim Grosbach
ad1b872c44 Trailing whitespace. 
llvm-svn: 122542
 2010-12-24 05:06:32 +00:00
Andrew Trick
134b2a5907 Various bits of framework needed for precise machine-level selection 
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.

llvm-svn: 122541
 2010-12-24 05:03:26 +00:00
Andrew Trick
53f4556c64 whitespace 
llvm-svn: 122539
 2010-12-24 04:28:06 +00:00
Cameron Zwarich
a7ad357a13 Simplify a check for implicit defs and remove a FIXME. 
llvm-svn: 122537
 2010-12-24 03:09:36 +00:00
Kevin Enderby
ff7e68c5e7 In llvm-mc parse a Hash token as a full line comment. Allows handling of 
preprocessed .s files and matches darwin gas.  rdar://8798690
Also fix a comment on the next line of AsmParser.cpp after this new code.

llvm-svn: 122531
 2010-12-24 00:12:02 +00:00
Jim Grosbach
7fc4f99084 Use a StringSwitch<> instead of a manually constructed string matcher. 
llvm-svn: 122530
 2010-12-24 00:03:39 +00:00
Owen Anderson
6afd90810e When determining if we can fold (x >> C1) << C2, the bits that we need to verify are zero 
are not the low bits of x, but the bits that WILL be the low bits after the operation completes.

llvm-svn: 122529
 2010-12-23 23:56:24 +00:00
Evan Cheng
ea28d16e36 Code clean up. No functionality change. 
llvm-svn: 122528
 2010-12-23 23:54:17 +00:00
Jim Grosbach
03a39130cb Remove dead patterns. 
llvm-svn: 122524
 2010-12-23 23:20:13 +00:00
Jim Grosbach
14f46d80df Recognize a few more documented register name aliases for ARM in the asm lexer. 
llvm-svn: 122523
 2010-12-23 23:19:54 +00:00
Bob Wilson
85dbc89f44 Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions. 
If the basic block containing the BCCi64 (or BCCZi64) instruction ends with
an unconditional branch, that branch needs to be deleted before appending
the expansion of the BCCi64 to the end of the block.

llvm-svn: 122521
 2010-12-23 22:45:49 +00:00
Oscar Fuentes
55b9ff9dd9 Do not re-test for the existence of pthread.h. 
It was causing problems on the MinGW build. See PR8849.

llvm-svn: 122518
 2010-12-23 21:27:22 +00:00
Torok Edwin
cfd30fdf42 XFAIL vg_leak the new test as the rest. 
llvm-svn: 122517
 2010-12-23 21:22:09 +00:00
Owen Anderson
be8084acdd It is possible for SimplifyCFG to cause PHI nodes to become redundant too late in the optimization 
pipeline to be caught by instcombine, and it's not feasible to catch them in SimplifyCFG because the
use-lists are in an inconsistent state at the point where it could know that it need to simplify them.
Instead, have CodeGenPrepare look for trivially redundant PHIs as part of its general cleanup effort.

llvm-svn: 122516
 2010-12-23 20:57:35 +00:00
Chris Lattner
01e8c46349 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Chris Lattner
b607e7deda flags -> glue for selectiondag 
llvm-svn: 122509
 2010-12-23 17:24:32 +00:00
Chris Lattner
fb9ff7a4ff sdisel flag -> glue. 
llvm-svn: 122507
 2010-12-23 17:13:18 +00:00
Chris Lattner
15e8133b87 continue renaming flag -> glue. 
llvm-svn: 122506
 2010-12-23 17:03:20 +00:00
Torok Edwin
2acdd67db2 Fix OCaml bindings crash, PR8847. 
See http://caml.inria.fr/mantis/view.php?id=4166
If we call only external functions from a module, then its 'let _' bindings
don't get executed, which means that the exceptions don't get registered for use
in the C code.
This in turn causes llvm_raise to call raise_with_arg() with a NULL pointer and
cause a segmentation fault.

The workaround is to declare all 'external' functions as 'val' in these .mli
files.

Also added a separate testcase (the testcase must call only external functions
for the bug to occur).

llvm-svn: 122497
 2010-12-23 15:49:26 +00:00
Benjamin Kramer
0a0e2c55c4 Remove/fix invalid README entries. The well thought out strcpy function doesn't return a pointer to the end of the string. 
llvm-svn: 122496
 2010-12-23 15:32:07 +00:00
Benjamin Kramer
b21118c91b Remove some obsolete README items, add a new one off the top of my head. 
llvm-svn: 122495
 2010-12-23 15:07:02 +00:00
Andrew Trick
ca2e267ddc Reorganize ListScheduleBottomUp in preparation for modeling machine cycles and instruction issue. 
llvm-svn: 122491
 2010-12-23 05:42:20 +00:00
Andrew Trick
c046a115d4 Converted LiveRegCycles to LiveRegGens. It's easier to work with and allows multiple nodes per cycle. 
llvm-svn: 122474
 2010-12-23 04:16:14 +00:00
Andrew Trick
e48d5d8395 In CheckForLiveRegDef use TRI->getOverlaps. 
llvm-svn: 122473
 2010-12-23 03:43:21 +00:00
Andrew Trick
cc701bcfdc Fixes PR8823: add-with-overflow-128.ll 
In the bottom-up selection DAG scheduling, handle two-address
instructions that read/write unspillable registers. Treat
the entire chain of two-address nodes as a single live range.

llvm-svn: 122472
 2010-12-23 03:15:51 +00:00
Mon P Wang
eb2ae28352 Preserve the address space when generating bitcasts for MemTransferInst in ConvertToScalarInfo 
llvm-svn: 122462
 2010-12-23 01:41:32 +00:00
Jeffrey Yasskin
a199652a3e Change all self assignments X=X to (void)X, so that we can turn on a 
new gcc warning that complains on self-assignments and
self-initializations.

llvm-svn: 122458
 2010-12-23 00:58:24 +00:00
Bill Wendling
f897a6bb16 Default to armv7 instead of armv6. 
llvm-svn: 122457
 2010-12-23 00:49:18 +00:00
Jim Grosbach
b0e9926c33 Trailing whitespace. 
llvm-svn: 122456
 2010-12-22 23:26:02 +00:00
Benjamin Kramer
49942a90b7 DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is illegal. The latter usually compiles into smaller code. 
example code:
unsigned foo(unsigned x, unsigned y) {
  if (x != 0) y--;
  return y;
}

before:
  _foo:                           ## @foo
    cmpl  $1, 4(%esp)             ## encoding: [0x83,0x7c,0x24,0x04,0x01]
    sbbl  %eax, %eax              ## encoding: [0x19,0xc0]
    notl  %eax                    ## encoding: [0xf7,0xd0]
    addl  8(%esp), %eax           ## encoding: [0x03,0x44,0x24,0x08]
    ret                           ## encoding: [0xc3]

after:
  _foo:                           ## @foo
    cmpl  $1, 4(%esp)             ## encoding: [0x83,0x7c,0x24,0x04,0x01]
    movl  8(%esp), %eax           ## encoding: [0x8b,0x44,0x24,0x08]
    adcl  $-1, %eax               ## encoding: [0x83,0xd0,0xff]
    ret                           ## encoding: [0xc3]

llvm-svn: 122455
 2010-12-22 23:17:45 +00:00
Benjamin Kramer
27d13684f5 InstCombine: creating selects from -1 and 0 is fine, they combine into a sext from i1. 
llvm-svn: 122453
 2010-12-22 23:12:15 +00:00
Benjamin Kramer
d8387aa9bd X86: Lower a select directly to a setcc_carry if possible. 
int test(unsigned long a, unsigned long b) { return -(a < b); }
compiles to
  _test:                              ## @test
    cmpq  %rsi, %rdi                  ## encoding: [0x48,0x39,0xf7]
    sbbl  %eax, %eax                  ## encoding: [0x19,0xc0]
    ret                               ## encoding: [0xc3]
instead of
  _test:                              ## @test
    xorl  %ecx, %ecx                  ## encoding: [0x31,0xc9]
    cmpq  %rsi, %rdi                  ## encoding: [0x48,0x39,0xf7]
    movl  $-1, %eax                   ## encoding: [0xb8,0xff,0xff,0xff,0xff]
    cmovael %ecx, %eax                ## encoding: [0x0f,0x43,0xc1]
    ret                               ## encoding: [0xc3]

llvm-svn: 122451
 2010-12-22 23:09:28 +00:00
Rafael Espindola
9e462b3734 Add r122359 back now that the bug in MCDwarfLineAddrFragment fragment has been 
fixed.

llvm-svn: 122448
 2010-12-22 22:16:24 +00:00
Dan Gohman
db69a33d9f Constify. 
llvm-svn: 122447
 2010-12-22 22:10:08 +00:00
Rafael Espindola
3897d5e658 Assert that the AddrDelta expression is really constant and wrap it in a set 
if we have a lame assembler.

llvm-svn: 122446
 2010-12-22 22:04:28 +00:00
Jakob Stoklund Olesen
f761c75efb When RegAllocGreedy decides to spill the interferences of the current register, 
pick the victim with the lowest total spill weight.

llvm-svn: 122445
 2010-12-22 22:01:30 +00:00
Jakob Stoklund Olesen
71e527ef4b Include a shadow of the original CFG edges in the edge bundle graph. 
llvm-svn: 122444
 2010-12-22 22:01:28 +00:00
Rafael Espindola
81ac7c5fad Rename NeedsSetToChangeDiffSize to HasAggressiveSymbolFolding which is a much 
better name and matches what is used in the MachO writer.

llvm-svn: 122443
 2010-12-22 21:51:29 +00:00
Daniel Dunbar
e6ec0e7149 MC/Mach-O/ARM: Don't try to use scattered relocs for BR24 fixups. 
llvm-svn: 122441
 2010-12-22 21:26:43 +00:00
Rafael Espindola
5004de4d8b Add reduced test from 8845. 
llvm-svn: 122438
 2010-12-22 21:15:13 +00:00
Rafael Espindola
6baac40d13 Revert r122359 while I debug PR8845. 
llvm-svn: 122427
 2010-12-22 19:05:49 +00:00
Matt Beaumont-Gay
2a54f466cf Fix another conditional expression mismatched enum type warning. 
llvm-svn: 122419
 2010-12-22 18:25:55 +00:00
Duncan Sands
68d969c2f5 When determining whether the new instruction was already present in 
the original instruction, half the cases were missed (making it not
wrong but suboptimal).  Also correct a typo (A <-> B) in the second
chunk. 

llvm-svn: 122414
 2010-12-22 17:15:25 +00:00
Duncan Sands
e1522867e6 Make this test not depend on how the variable is named. 
llvm-svn: 122413
 2010-12-22 17:08:04 +00:00
Daniel Dunbar
cb8ac619a2 MC/Mach-O/ARM: We always use the SECTDIFF reloc type on ARM, which is 
esp. important given that the LOCAL_SECTDIFF enumeration got redefined.

llvm-svn: 122412
 2010-12-22 16:52:19 +00:00