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Commit Graph

4281 Commits

Author SHA1 Message Date
Clement Courbet
ec243f03b8 [MC][TableGen] Fix r329675.
Caught by bots with -Wmissing-braces.

llvm-svn: 329676
2018-04-10 08:43:46 +00:00
Clement Courbet
221e6ccd99 [MC][TableGen] Add optional libpfm counter names for ProcResUnits.
Summary:
Subtargets can define the libpfm counter names that can be used to
measure cycles and uops issued on ProcResUnits.
This allows making llvm-exegesis available on more targets.
Fixes PR36984.

Reviewers: gchatelet, RKSimon, andreadb, craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45360

llvm-svn: 329675
2018-04-10 08:16:37 +00:00
Sameer AbuAsal
9cc166efe6 [RISCV] Tablegen-driven Instruction Compression.
Summary:

    This patch implements a tablegen-driven Instruction Compression
    mechanism for generating RISCV compressed instructions
    (C Extension) from the expanded instruction form.

    This tablegen backend processes CompressPat declarations in a
    td file and generates all the compile-time and runtime checks
    required to validate the declarations, validate the input
    operands and generate correct instructions.

    The checks include validating register operands, immediate
    operands, fixed register operands and fixed immediate operands.

    Example:
      class CompressPat<dag input, dag output> {
        dag Input  = input;
        dag Output    = output;
        list<Predicate> Predicates = [];
      }

      let Predicates = [HasStdExtC] in {
      def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
                        (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
      }

    The result is an auto-generated header file
    'RISCVGenCompressEmitter.inc' which exports two functions for
    compressing/uncompressing MCInst instructions, plus
    some helper functions:

      bool compressInst(MCInst& OutInst, const MCInst &MI,
                        const MCSubtargetInfo &STI,
                        MCContext &Context);

      bool uncompressInst(MCInst& OutInst, const MCInst &MI,
                          const MCRegisterInfo &MRI,
                          const MCSubtargetInfo &STI);

    The clients that include this auto-generated header file and
    invoke these functions can compress an instruction before emitting
    it, in the target-specific ASM or ELF streamer, or can uncompress
    an instruction before printing it, when the expanded instruction
    format aliases is favored.

    The following clients were added to implement compression\uncompression
    for RISCV:

    1) RISCVAsmParser::MatchAndEmitInstruction:
       Inserted a call to compressInst() to compresses instructions
       parsed by llvm-mc coming from an ASM input.
    2) RISCVAsmPrinter::EmitInstruction:
       Inserted a call to compressInst() to compress instructions that
       were lowered from Machine Instructions (MachineInstr).
    3) RVInstPrinter::printInst:
       Inserted a call to uncompressInst() to print the expanded
       version of the instruction instead of the compressed one (e.g,
       add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
       is not passed.

This patch squashes D45119, D42780 and D41932. It was reviewed in  smaller patches by
asb, efriedma, apazos and mgrang.

Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal

Reviewed By: sabuasal

Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng

Differential Revision: https://reviews.llvm.org/D45385

llvm-svn: 329455
2018-04-06 21:07:05 +00:00
Mandeep Singh Grang
aa9538aa70 [TableGen] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.

Reviewers: stoklund, kparzysz, dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45144

llvm-svn: 329451
2018-04-06 20:18:05 +00:00
Craig Topper
dbad6a134b [X86] Disassembler support for having an ADSIZE prefix affect instructions with 0xf2 and 0xf3 prefixes.
Needed to support umonitor from D45253.

llvm-svn: 329327
2018-04-05 18:20:14 +00:00
Andrea Di Biagio
d84c17dd93 Fix the buildbots after r329304.
llvm-svn: 329306
2018-04-05 15:53:31 +00:00
Andrea Di Biagio
01d033c489 [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca.
This patch adds the ability to describe properties of the hardware retire
control unit.

Tablegen class RetireControlUnit has been added for this purpose (see
TargetSchedule.td).

A RetireControlUnit specifies the size of the reorder buffer, as well as the
maximum number of opcodes that can be retired every cycle.

A zero (or negative) value for the reorder buffer size means: "the size is
unknown". If the size is unknown, then llvm-mca defaults it to the value of
field SchedMachineModel::MicroOpBufferSize.  A zero or negative number of
opcodes retired per cycle means: "there is no restriction on the number of
instructions that can be retired every cycle".

Models can optionally specify an instance of RetireControlUnit. There can only
be up-to one RetireControlUnit definition per scheduling model.

Information related to the RCU (RetireControlUnit) is stored in (two new fields
of) MCExtraProcessorInfo.  llvm-mca loads that information when it initializes
the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp).

This patch fixes PR36661.

Differential Revision: https://reviews.llvm.org/D45259

llvm-svn: 329304
2018-04-05 15:41:41 +00:00
Andrea Di Biagio
217b1ab970 [MC] Fix spaces between values printed by EmitRegisterFileInfo.
llvm-svn: 329284
2018-04-05 13:59:52 +00:00
Simon Pilgrim
ae3b946d06 [SchedModel] Complete models shouldn't match against itineraries when they don't use them (PR35639)
For schedule models that don't use itineraries, checkCompleteness still checks that an instruction has a matching itinerary instead of skipping and going straight to matching the InstRWs. That doesn't seem to match what happens in TargetSchedule.cpp

This patch causes problems for a number of models that had been incorrectly flagged as complete.

Differential Revision: https://reviews.llvm.org/D43235

llvm-svn: 329280
2018-04-05 13:11:36 +00:00
Andrea Di Biagio
2c2840f2eb [Tablegen] Slightly refactor method SubtargetEmitter::EmitExtraProcessorInfo.
This patch moves most of the logic from EmitExtraProcessorInfo to a couple of
helper functions. No functional change intended.

llvm-svn: 329173
2018-04-04 11:53:13 +00:00
Andrea Di Biagio
f425ba9f0f [MC][Tablegen] Allow the definition of processor register files in the scheduling model for llvm-mca
This patch allows the description of register files in processor scheduling
models. This addresses PR36662.

A new tablegen class named 'RegisterFile' has been added to TargetSchedule.td.
Targets can optionally describe register files for their processors using that
class. In particular, class RegisterFile allows to specify:
 - The total number of physical registers.
 - Which target registers are accessible through the register file.
 - The cost of allocating a register at register renaming stage.

Example (from this patch - see file X86/X86ScheduleBtVer2.td)

  def FpuPRF : RegisterFile<72, [VR64, VR128, VR256], [1, 1, 2]>

Here, FpuPRF describes a register file for MMX/XMM/YMM registers. On Jaguar
(btver2), a YMM register definition consumes 2 physical registers, while MMX/XMM
register definitions only cost 1 physical register.

The syntax allows to specify an empty set of register classes.  An empty set of
register classes means: this register file models all the registers specified by
the Target.  For each register class, users can specify an optional register
cost. By default, register costs default to 1.  A value of 0 for the number of
physical registers means: "this register file has an unbounded number of
physical registers".

This patch is structured in two parts.

* Part 1 - MC/Tablegen *

A first part adds the tablegen definition of RegisterFile, and teaches the
SubtargetEmitter how to emit information related to register files.

Information about register files is accessible through an instance of
MCExtraProcessorInfo.
The idea behind this design is to logically partition the processor description
which is only used by external tools (like llvm-mca) from the processor
information used by the llvm machine schedulers.
I think that this design would make easier for targets to get rid of the extra
processor information if they don't want it.

* Part 2 - llvm-mca related *

The second part of this patch is related to changes to llvm-mca.

The main differences are:
 1) class RegisterFile now needs to take into account the "cost of a register"
when allocating physical registers at register renaming stage.
 2) Point 1. triggered a minor refactoring which lef to the removal of the
"maximum 32 register files" restriction.
 3) The BackendStatistics view has been updated so that we can print out extra
details related to each register file implemented by the processor.

The effect of point 3. is also visible in tests register-files-[1..5].s.

Differential Revision: https://reviews.llvm.org/D44980

llvm-svn: 329067
2018-04-03 13:36:24 +00:00
Craig Topper
80960a2e45 [X86] Reduce number of OpPrefix bits in TSFlags to 2. NFCI
TSFlag doesn't need to disambiguate NoPrfx from PS. So shift the encodings so PS is NoPrfx|0x4.

llvm-svn: 329049
2018-04-03 06:37:04 +00:00
Craig Topper
cc790d7e91 [X86][TableGen] Add a missing error check to make sure EVEX instructions use one PS/PD/XS/XD prefixes.
llvm-svn: 329048
2018-04-03 06:37:01 +00:00
Craig Topper
a9aa267569 [TableGen] Use llvm::cast instead of static_cast so that the cast will be checked. NFC
llvm-svn: 329045
2018-04-03 05:10:12 +00:00
Nicolai Haehnle
eacc62ef10 TableGen: Support Intrinsic values in SearchableTable
Summary:
We will use this in the AMDGPU backend in a subsequent patch
in the stack to lookup target-specific per-intrinsic information.

The generic CodeGenIntrinsic machinery is used to ensure that,
even though we don't calculate actual enum values here, we do
get the intrinsics in the right order for the binary search
index.

Change-Id: If61cd5587963a4c5a1cc53df1e59c5e4dec1f9dc

Reviewers: arsenm, rampitec, b-sumner

Subscribers: wdng, tpr, llvm-commits

Differential Revision: https://reviews.llvm.org/D44935

llvm-svn: 328937
2018-04-01 17:08:58 +00:00
Nicolai Haehnle
896493fd3f TableGen: More helpful error messages
Summary: Change-Id: I3c23f6f6597912423762780cd8c5315870412bbe

Reviewers: arsenm, rampitec, b-sumner

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D44936

Change-Id: Ie62614a3e2d7774f46e4034478b28f57100a2c92
llvm-svn: 328936
2018-04-01 17:08:49 +00:00
Fangrui Song
cd23b12dcc Fix a bunch of typoes. NFC
llvm-svn: 328907
2018-03-30 22:22:31 +00:00
David Blaikie
2d78e78856 Add missing dependency (headers are included from MC, so a link dependency could exist easily enough)
llvm-svn: 328743
2018-03-29 00:29:43 +00:00
Simon Pilgrim
529713cc08 [SchedModel] Remove instregex entries that don't match any instructions
This patch throws a fatal error if an instregex entry doesn't actually match any instructions. This is part of the work to reduce the compile time impact of increased instregex usage (PR35955), although the x86 models seem to be relatively clean.

All the cases I encountered have now been fixed in trunk and this will ensure they don't get reintroduced.

Differential Revision: https://reviews.llvm.org/D44687

llvm-svn: 328459
2018-03-25 19:20:08 +00:00
Craig Topper
b21c0d4930 [SchedModel] Remove an unneeded temporary vector.
llvm-svn: 328442
2018-03-24 22:58:03 +00:00
Craig Topper
7d4e499d01 [SchedModel] Use std::move in a couple places to reduce copying
llvm-svn: 328441
2018-03-24 22:58:02 +00:00
Craig Topper
ac1997833d [SchedModel] Use std::move to replace a vector instead of vector::swap
We don't really care about the old vector value so we don't care to swap it.

llvm-svn: 328440
2018-03-24 22:58:00 +00:00
Craig Topper
9c9ba2b75e [SchedModel] Remove std::vectors that were created with 1 element and then passed to an ArrayRef parameter.
ArrayRef can capture a single element. We don't need a vector for that.

llvm-svn: 328438
2018-03-24 21:57:35 +00:00
Simon Pilgrim
6b345575c4 [SchedModel] Record::getName() returns StringRef - avoid std::string creation. NFCI.
llvm-svn: 328437
2018-03-24 21:22:32 +00:00
Simon Pilgrim
6305ab4346 [SchedModel] Avoid std::string creation for instregex patterns that don't contain regex metas. NFCI.
llvm-svn: 328436
2018-03-24 21:04:20 +00:00
Craig Topper
16ecfc9764 [X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an attribute.
This reduces the size of llvm-mc by at least 150k since we no longer have to multiply the attribute across 7 tables.

llvm-svn: 328416
2018-03-24 07:48:54 +00:00
Craig Topper
55eeee33ff [X86] Use unique_ptr to simplify memory management. NFC
llvm-svn: 328413
2018-03-24 07:15:47 +00:00
Craig Topper
95db0c2905 [X86] Use X86_INSTR_MRM_MAPPING macro instead of listing all MRM_C0-MRM_FF format encodings. NFC
llvm-svn: 328412
2018-03-24 07:15:46 +00:00
Craig Topper
f87f8c91fd [X86] Remove an unnecessary switch around two other switches. NFC
The outer switch only had one valid block so didn't provide any value.

llvm-svn: 328411
2018-03-24 07:15:45 +00:00
Craig Topper
abad09f7ae [X86] Merge the Has3DNow0F0FOpcode TSFlag into the OpMap encoding. NFC
The 3DNow instructions are encoded a little weird, but we can still represent it as an opcode map.

llvm-svn: 328410
2018-03-24 06:04:12 +00:00
David Blaikie
257beb78b0 Fix layering of CodeGen/TargetOpcodes.def by moving it to Support
It's also used by utils/TableGen so needs to reside somewhere common to
TableGen and CodeGen.

llvm-svn: 328396
2018-03-23 23:58:27 +00:00
David Blaikie
938d7fe477 Fix layering of MachineValueType.h by moving it from CodeGen to Support
This is used by llvm tblgen as well as by LLVM Targets, so the only
common place is Support for now. (maybe we need another target for these
sorts of things - but for now I'm at least making them correct & we can
make them better if/when people have strong feelings)

llvm-svn: 328395
2018-03-23 23:58:25 +00:00
David Blaikie
a2dec6ab6b Fix layering by moving X86DisassemblerDecoderCommon to Support
This is used from llvm tblgen and the X86Disassembler - the only common
library (apart from TableGen, which probably doesn't make sense to have
as a dependency from a release tool (rather than a use-while-building-llvm
tool) of LLVM)

llvm-svn: 328393
2018-03-23 23:58:20 +00:00
Craig Topper
3e660340e7 [TableGen] Don't capture returned std::vectors by const reference.
The full vector is being returned not a reference. So the reference was just a to a temporary.

llvm-svn: 328275
2018-03-23 00:02:45 +00:00
Craig Topper
e9a8982ac5 [X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and VROUNDPDY*. Fix itinerary mistake on all memory forms of VROUNDPD
This makes the Y position consistent with other instructions.

This should have been NFC, but while refactoring the multiclass I noticed that VROUNDPD memory forms were using the register itinerary.

llvm-svn: 328254
2018-03-22 21:55:20 +00:00
Craig Topper
deea9c98af [TableGen] Use empty emplace_back to add defaulted constructed objects to vectors to avoid using resize(size()+1). NFC
llvm-svn: 328184
2018-03-22 06:15:10 +00:00
Craig Topper
37c4011b10 [TableGen] Add a non-default constructor to CodeGenSchedClass and use it via emplace_back to create new SchedClasses instead of using resize(size+1)
llvm-svn: 328183
2018-03-22 06:15:08 +00:00
Craig Topper
2f62f3c646 [TableGen] Hoist the code for copying InstRWs from an old scheduling class to a new one out of the loop that assigns instructions to the new class. NFCI
We already know all the of instructions we're processing in the instruction loop belong to no class or all to the same class. So we only have to worry about remapping one class. So hoist it all out and remove the SmallPtrSet that tracked which class we'd already remapped.

I had to introduce new instruction loop inside this code to print an error message, but that only occurs on the error path.

llvm-svn: 328142
2018-03-21 19:52:13 +00:00
Craig Topper
52fa6a5a33 [TableGen] Remove unnecessary map lookup and shadowing of a variable. NFCI
We already have an OldSCIdx variable in the outer loop here. And we already did the map lookup in the loop that populated ClassInstrs. And the outer OldSCIdx got it from ClassInstrs.

llvm-svn: 328139
2018-03-21 19:30:33 +00:00
Craig Topper
9761fb8516 [TableGen] Use range-based for loops. NFC
llvm-svn: 328138
2018-03-21 19:30:31 +00:00
Craig Topper
415d067062 [TableGen] Use count_if instead of a manual loop. NFC
llvm-svn: 328137
2018-03-21 19:30:30 +00:00
Simon Pilgrim
198d5bb786 [SchedModel] Use CodeGenSchedClass::getSchedClassIdx helper directly. NFCI.
llvm-svn: 328128
2018-03-21 18:09:34 +00:00
Simon Pilgrim
1fa3b68443 [SchedModel] Use CodeGenSchedClass::isKeyEqual instead of duplicating code. NFCI.
llvm-svn: 328126
2018-03-21 17:57:21 +00:00
Craig Topper
73d813ea79 [TableGen] Remove a defaulted function argument that is never called with another value. NFC
llvm-svn: 328075
2018-03-21 05:13:04 +00:00
Craig Topper
fa8cad1ef4 [TableGen] Move a function from llvm namespace and make it a static function. NFC
It's only called from one place and is defined just above that use.

llvm-svn: 328074
2018-03-21 05:13:01 +00:00
Craig Topper
95614d111e [TableGen] Use SmallMapVector to simplify some code that was trying to keep a vector unique
Summary:
This code previously had a SmallVector of std::pairs containing an unsigned and another SmallVector. The outer vector was using the unsigned effectively as a key to decide which SmallVector to add into. So each time something new needed to be added the out vector needed to be scanned. If it wasn't found a new entry needed to be added to be added. This sounds very much like a map, but the next loop iterates over the outer vector to get a deterministic order.

We can simplify this code greatly if use SmallMapVector instead. This uses more stack space since we now have a vector and a map, but the searching and creating new entries all happens behind the scenes. It should also make the search more efficient though usually there are only a few entries so that doesn't matter much.

We could probably get determinism by just using std::map which would iterate over the unsigned key, but that would generate different output from what we get with the current implementation.

Reviewers: RKSimon, dblaikie

Reviewed By: dblaikie

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44711

llvm-svn: 328070
2018-03-21 02:48:34 +00:00
Simon Pilgrim
84260d43c8 [SchedModel] Simplify InstRegexOp::apply. NFCI.
As discussed on D44687, there was no need for 2 separate for loops for collecting the Regex and then matching against instructions.

llvm-svn: 328052
2018-03-20 22:20:28 +00:00
Craig Topper
a9d0df59b5 [TableGen] Use range based for loop. NFC
llvm-svn: 328034
2018-03-20 20:24:16 +00:00
Craig Topper
bed356482a [TableGen] Use vector::append instead of looping and calling push_back. NFC
Both vectors contain unsigned so we can just use append to do the copying. Not only is this shorter, but it should be able to predict the final size and only grow the vector once if needed.

llvm-svn: 328033
2018-03-20 20:24:14 +00:00
Craig Topper
c83ae95df5 [TableGen] Use llvm::transform to simplify some loops. NFCI
llvm-svn: 328032
2018-03-20 20:24:12 +00:00