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Author SHA1 Message Date
Dan Gohman
8385890394 Move the setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand) and 
the check to see if the assembler supports .loc from X86TargetLowering
into the superclass TargetLowering.

llvm-svn: 42297
 2007-09-25 15:10:49 +00:00
Evan Cheng
36b3babfde Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after 
all the kinks are worked out.

llvm-svn: 42285
 2007-09-25 01:57:46 +00:00
Dale Johannesen
5ea6a9bc3a When mixing SSE and x87 codegen, it's possible to 
have situations where an SSE instruction turns into
multiple blocks, with the live range of an x87
register crossing them.  To do this correctly make
sure we examine all blocks when inserting
FP_REG_KILL.  PR 1697.  (This was exposed by my
fix for PR 1681, but the same thing could happen
mixing x87 long double with SSE.)

llvm-svn: 42281
 2007-09-24 22:52:39 +00:00
Dan Gohman
96d5f979bc Add support on x86 for having Legalize lower ISD::LOCATION to ISD::DEBUG_LOC 
instead of ISD::LABEL with a manual .debug_line entry when the assembler
supports .file and .loc directives.

llvm-svn: 42278
 2007-09-24 21:54:14 +00:00
Dan Gohman
a264777dc1 Fix the syntax for the .loc directive in preparation for using it. 
llvm-svn: 42268
 2007-09-24 19:25:06 +00:00
Dan Gohman
32b1df2aa3 The code that used the StartLabelId label was removed, so remove the 
code that creates the label too.

llvm-svn: 42265
 2007-09-24 16:44:26 +00:00
Chris Lattner
594d3aa066 claim that "st" is from the 80-bit register file. This causes x87-using inline 
asm to die with:

ScheduleDAG.cpp:269: failed assertion `false && "Couldn't find the register class"'

instead of:
failed assertion `RegMap->getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"'

yay.

llvm-svn: 42259
 2007-09-24 05:27:37 +00:00
Dale Johannesen
ea6ffa0b36 Fix PR 1681. When X86 target uses +sse -sse2, 
keep f32 in SSE registers and f64 in x87.  This
is effectively a new codegen mode.
Change addLegalFPImmediate to permit float and
double variants to do different things.
Adjust callers.

llvm-svn: 42246
 2007-09-23 14:52:20 +00:00
Rafael Espindola
11ee0898b9 Don't add a default STACK_ALIGN (use the generic ABI alignment) 
Implement calls to functions with byval arguments on X86

llvm-svn: 42192
 2007-09-21 15:50:22 +00:00
Rafael Espindola
b0b536b597 small cleanup: use LowerMemArgument in LowerFastCCArguments also 
llvm-svn: 42189
 2007-09-21 14:55:38 +00:00
Evan Cheng
d675ed5400 Honor user-defined section specification of a global, ignores whether its initializer is null. 
llvm-svn: 42182
 2007-09-21 00:41:19 +00:00
Dan Gohman
eb622df2ef Fix several more entries in the x86 reload/remat folding tables. 
llvm-svn: 42162
 2007-09-20 14:17:21 +00:00
Dale Johannesen
ab5a68edd5 another long double buglet 
llvm-svn: 42159
 2007-09-20 01:27:54 +00:00
Dale Johannesen
04682bdc81 More long double fixes. x86_64 should build now. 
llvm-svn: 42155
 2007-09-19 23:55:34 +00:00
Evan Cheng
ec83699473 PSHUFDmi, etc. are actually folding a load, not a store. 
llvm-svn: 42147
 2007-09-19 19:02:47 +00:00
Evan Cheng
8e459700fe Set CCR (EFLAGS) copy cost to -1, i.e. extremely expensive to copy. 
llvm-svn: 42124
 2007-09-19 01:36:39 +00:00
Dan Gohman
be3b005b2d Move the entries for 64-bit CMP, IMUL, and a few others into the correct 
tables so that they are eligible for reload/remat folding. And add
entries for JMP and CALL.

llvm-svn: 42094
 2007-09-18 14:59:14 +00:00
Dale Johannesen
46adce144c Remove RSTRegClass case from loadRegFromStackSlot 
and storeRegToStackSlot.  Evan and I concluded this
should never be needed and it appears to be true.
(It if is needed, adjustment would be needed for
long double to work.)

llvm-svn: 42049
 2007-09-17 20:15:38 +00:00
Evan Cheng
d7742e7939 X86ISD::TEST is dead. 
llvm-svn: 42037
 2007-09-17 17:42:53 +00:00
Dan Gohman
b096221b3e Add 64-bit jmp instructions to the list of instructions that 
can terminate a block with no fall-through.

llvm-svn: 42029
 2007-09-17 15:19:08 +00:00
Dan Gohman
41a6dea029 Use xorl instead of xorq to enter a zero into a 64-bit register. 
llvm-svn: 42027
 2007-09-17 14:55:08 +00:00
Dan Gohman
1aeaeec570 Emit integer x<1 as x<=0, as comparisons with zero (now includeing 
64-bit) can use test instead of cmp with an immediate.

llvm-svn: 42026
 2007-09-17 14:49:27 +00:00
Dan Gohman
b9449c9118 Use "test reg,reg" in place of "cmp reg,0" for 64-bit operands. This was 
previously only done for 32-bit and smaller operands.

llvm-svn: 42024
 2007-09-17 14:35:24 +00:00
Bill Wendling
f1335f46d4 Follow-up to patch r41999. Make the conditional that emits the personality stub 
match the conditional that turns on exception handling emittion in the asm
printer.

llvm-svn: 42008
 2007-09-16 19:21:08 +00:00
Bill Wendling
7932341cef Only emit the personality function as a global value if the backend actually 
supports it. This solves this error on the Darwin x86-64 platform:

$ cat testcase.ii
struct A {
  A();
};

A *bork() {
  return new A;
}
$ llvm-g++ -arch x86_64 -c testcase.ii
/var/tmp//cc3U8fd8.s:52:unknown section type: non_lazy_symbol_pointers
/var/tmp//cc3U8fd8.s:52:Rest of line ignored. 1st junk character valued 76 (L).
/var/tmp//cc3U8fd8.s:53:Unknown pseudo-op: .indirect_symbol
/var/tmp//cc3U8fd8.s:53:Rest of line ignored. 1st junk character valued 95 (_).

llvm-svn: 41999
 2007-09-16 10:36:17 +00:00
Dan Gohman
df419c2b4f Add patterns for SHLD64* and SHRD64*. 
llvm-svn: 41975
 2007-09-14 23:17:45 +00:00
Dale Johannesen
575bd6070a Remove the assumption that FP's are either float or 
double from some of the many places in the optimizers
it appears, and do something reasonable with x86
long double.
Make APInt::dump() public, remove newline, use it to
dump ConstantSDNode's.
Allow APFloats in FoldingSet.
Expand X86 backend handling of long doubles (conversions
to/from int, mostly).

llvm-svn: 41967
 2007-09-14 22:26:36 +00:00
Evan Cheng
13797e4a74 Add implicit def of EFLAGS on those instructions that may modify flags. 
llvm-svn: 41962
 2007-09-14 21:48:26 +00:00
Dan Gohman
fb60c0dfed Remove isReg, isImm, and isMBB, and change all their users to use 
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958
 2007-09-14 20:33:02 +00:00
Rafael Espindola
5d8b225881 Add support for functions with byval arguments on x86 
llvm-svn: 41953
 2007-09-14 15:48:13 +00:00
Evan Cheng
b43255bc68 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Evan Cheng
ce8087de3e Added status flags register: EFLAGS. 
llvm-svn: 41862
 2007-09-11 19:53:28 +00:00
Dale Johannesen
7bc3969cea Add APInt interfaces to APFloat (allows directly 
access to bits).  Use them in place of float and
double interfaces where appropriate.
First bits of x86 long double constants handling 
(untested, probably does not work).

llvm-svn: 41858
 2007-09-11 18:32:33 +00:00
Bill Wendling
74888e63e7 Add a bool to indicate if we should set the "indirect encoding" bit in the Dwarf 
information for EH.

llvm-svn: 41852
 2007-09-11 17:20:55 +00:00
Duncan Sands
c358890f73 Fold the adjust_trampoline intrinsic into 
init_trampoline.  There is now only one
trampoline intrinsic.

llvm-svn: 41841
 2007-09-11 14:10:23 +00:00
Duncan Sands
8640185d45 My compiler warns about the semicolon. 
llvm-svn: 41840
 2007-09-11 12:30:25 +00:00
Bill Wendling
3c6a8b2814 The personality function on Darwin needs a global stub. We then refer to 
that global stub instead of doing the ".set" thingy we were doing before.

llvm-svn: 41838
 2007-09-11 08:27:17 +00:00
Evan Cheng
b639648fc5 New entry. 
llvm-svn: 41810
 2007-09-10 22:16:37 +00:00
Chris Lattner
d4602cc0e7 Add some notes about better flag handling. 
llvm-svn: 41808
 2007-09-10 21:43:18 +00:00
Evan Cheng
4715ccb29c It's not safe to rematerialize MOV32r0 etc. by simply cloning the original 
instruction. These are implemented with xor which will modify the conditional
code. They should be rematerialized as move instructions.

llvm-svn: 41802
 2007-09-10 20:48:53 +00:00
Evan Cheng
65df926ced TableGen no longer emit CopyFromReg nodes for implicit results in physical 
registers. The scheduler is now responsible for emitting them.

llvm-svn: 41781
 2007-09-07 23:59:02 +00:00
Dan Gohman
3bc1bc2590 Avoid storing and reloading zeros and other constants from stack slots 
by flagging the associated instructions as being trivially rematerializable.

llvm-svn: 41775
 2007-09-07 21:32:51 +00:00
Dale Johannesen
783215c630 Apply feedback from previous patch. 
llvm-svn: 41774
 2007-09-07 21:07:57 +00:00
Rafael Espindola
8c57e70f93 Add support for having different alignment for objects on call frames. 
The x86-64 ABI states that objects passed on the stack have
8 byte alignment. Implement that.

llvm-svn: 41768
 2007-09-07 14:52:14 +00:00
Owen Anderson
4b71e55287 Add lengthof and endof templates that hide a lot of sizeof computations. 
Patch by Sterling Stein!

llvm-svn: 41758
 2007-09-07 04:06:50 +00:00
Dale Johannesen
86f367a6b7 Next round of APFloat changes. 
Use APFloat in UpgradeParser and AsmParser.
Change all references to ConstantFP to use the
APFloat interface rather than double.  Remove
the ConstantFP double interfaces.
Use APFloat functions for constant folding arithmetic
and comparisons.
(There are still way too many places APFloat is
just a wrapper around host float/double, but we're
getting there.)

llvm-svn: 41747
 2007-09-06 18:13:44 +00:00
Evan Cheng
896c1ed385 Fix a bug in X86InstrInfo::convertToThreeAddress that caused it to codegen: 
leal    (,%rcx,8), %rcx
It should be
leal    (,%rcx,8), %ecx

llvm-svn: 41735
 2007-09-06 00:14:41 +00:00
Evan Cheng
4cae11d569 Mac OS X X86-64 ABI is same as the standard. 
llvm-svn: 41700
 2007-09-04 16:44:41 +00:00
Anton Korobeynikov
cf91be2c79 Reapply r41578 with proper fix 
llvm-svn: 41680
 2007-09-03 00:36:06 +00:00
Rafael Espindola
4ddaad4de0 Initial support for calling functions with byval arguments on x86-64 
llvm-svn: 41643
 2007-08-31 15:06:30 +00:00
Rafael Espindola
aa7930b4f0 Align i64 and f64 at 8 byte on x86-64. 
This is mandated table 3.1 at
http://www.x86-64.org/documentation/abi.pdf

llvm-svn: 41642
 2007-08-31 12:23:58 +00:00
Dale Johannesen
81d6ecb886 Enhance APFloat to retain bits of NaNs (fixes oggenc). 
Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.

llvm-svn: 41632
 2007-08-31 04:03:46 +00:00
Evan Cheng
cb317912b2 Added support to fold X86 load / store instructions. This allow rematerialized loads to be folded into their uses. 
llvm-svn: 41599
 2007-08-30 05:54:07 +00:00
Evan Cheng
527fe7ab57 Mark load instructions with isLoad = 1. 
llvm-svn: 41595
 2007-08-30 05:49:43 +00:00
Dale Johannesen
e91a908971 Change LegalFPImmediates to use APFloat. 
Add APFloat interfaces to ConstantFP, SelectionDAG.
Fix integer bit in double->APFloat conversion.
Convert LegalizeDAG to use APFloat interface in
ConstantFPSDNode uses.

llvm-svn: 41587
 2007-08-30 00:23:21 +00:00
Duncan Sands
26ef2a1767 Move getX86RegNum into X86RegisterInfo and use it 
in the trampoline lowering.  Lookup the jump and
mov opcodes for the trampoline rather than hard
coding them.

llvm-svn: 41577
 2007-08-29 19:01:20 +00:00
Rafael Espindola
dc5450f7fb Add a comment about using libc memset/memcpy or generating inline code. 
llvm-svn: 41502
 2007-08-27 17:48:26 +00:00
Rafael Espindola
3d52fe3ef3 call libc memcpy/memset if array size is bigger then threshold. 
Coping 100MB array (after a warmup) shows that glibc 2.6.1 implementation on
x86-64 (core 2) is 30% faster (from 0.270917s to 0.188079s)

llvm-svn: 41479
 2007-08-27 10:18:20 +00:00
Chris Lattner
1e089aac3a rename isOperandValidForConstraint to LowerAsmOperandForConstraint, 
changing the interface to allow for future changes.

llvm-svn: 41384
 2007-08-25 00:47:38 +00:00
Chris Lattner
4c84c39666 add a note 
llvm-svn: 41359
 2007-08-24 15:17:59 +00:00
Chris Lattner
9b22d7527c add some notes on really poor codegen. 
llvm-svn: 41319
 2007-08-23 15:22:07 +00:00
Bill Wendling
dd451b602a Add the PCSymbol for Darwin x86 platforms. 
llvm-svn: 41284
 2007-08-22 18:44:05 +00:00
Anton Korobeynikov
f942eb0c45 Use only 1 knob to enable exceptions on Darwin :). 
llvm-svn: 41208
 2007-08-21 00:31:30 +00:00
Rafael Espindola
68d95ff2b1 Partial implementation of calling functions with byval arguments: 
*) The needed information is propagated to the DAG
 *) The X86-64 backend detects it and aborts

llvm-svn: 41179
 2007-08-20 15:18:24 +00:00
Chris Lattner
fdb4d38108 add a note 
llvm-svn: 41178
 2007-08-20 02:14:33 +00:00
Anton Korobeynikov
3094846993 Move ReturnAddrIndex variable to X86MachineFunctionInfo structure. This fixed 
hard to catch bugs with retaddr lowering

llvm-svn: 41104
 2007-08-15 17:12:32 +00:00
Chris Lattner
9fd664292f add a note. 
llvm-svn: 41103
 2007-08-15 16:58:38 +00:00
Evan Cheng
eef13203e7 Fix a typo pointd out by Maarten ter Huurne. 
llvm-svn: 41059
 2007-08-13 23:27:11 +00:00
Dan Gohman
2390ff5060 When x86 addresses matching exceeds its recursion limit, check to 
see if the base register is already occupied before assuming it can be
used. This fixes bogus code generation in the accompanying testcase.

llvm-svn: 41049
 2007-08-13 20:03:06 +00:00
Chris Lattner
7dfec1ee54 Fix PR1607 
llvm-svn: 41048
 2007-08-13 18:42:37 +00:00
Chris Lattner
fedbfd5f47 expand a note 
llvm-svn: 41021
 2007-08-11 18:19:07 +00:00
Chris Lattner
5f098dbbe5 With evan's explicit flag representation, hopefully we will finally be 
able to 3-addressify away stuff like this:

        movl    %ecx, %eax
        decl    %eax

llvm-svn: 41020
 2007-08-11 18:16:46 +00:00
Bill Wendling
e611c96a3c 64-bit SSSE3 ops that use MMX registers don't require 16-byte alignment. 
Make a 'memop' pattern just for them.

llvm-svn: 41017
 2007-08-11 09:52:53 +00:00
Christopher Lamb
7e52a97df5 Use subregs to improve any_extend code generation when feasible. 
llvm-svn: 41013
 2007-08-10 22:22:41 +00:00
Christopher Lamb
450f6815b9 Increase efficiency of sign_extend_inreg by using subregisters for truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)). 
llvm-svn: 41010
 2007-08-10 21:48:46 +00:00
Christopher Lamb
4e6cae3eae Edit README in light of previous LEA16 commit. 
llvm-svn: 41009
 2007-08-10 21:29:05 +00:00
Christopher Lamb
7196f0d724 Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled. 
llvm-svn: 41007
 2007-08-10 21:18:25 +00:00
Rafael Espindola
b20b9e985a propagate struct size and alignment of byval arguments to the DAG 
llvm-svn: 40986
 2007-08-10 14:44:42 +00:00
Bill Wendling
d0bee665d3 For kicks, I though it would be fun to use the correct opcode. 
llvm-svn: 40985
 2007-08-10 09:00:17 +00:00
Bill Wendling
55c3dc2409 Adding SSSE3 intrinsics. 
llvm-svn: 40982
 2007-08-10 06:22:27 +00:00
Evan Cheng
3fae8e1c4a Temporarily backing out this change until we know why some dejagnu tests are failing. 
llvm-svn: 40973
 2007-08-09 22:25:35 +00:00
Evan Cheng
a58ebc46dd divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead. 
llvm-svn: 40972
 2007-08-09 21:59:35 +00:00
Evan Cheng
a822456bed GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_. 
llvm-svn: 40970
 2007-08-09 18:05:17 +00:00
Dale Johannesen
79551baaad long double 9 of N. This finishes up the X86-32 bits 
(constants are still not handled).  Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).

llvm-svn: 40958
 2007-08-09 01:04:01 +00:00
Dale Johannesen
6b8e91e7e3 Long double patch 8 of N: make it partially work in 
SSE mode (all but conversions <-> other FP types, I think):
>>Do not mark all-80-bit operations as "Requires[FPStack]"
(which really means "not SSE").
>>Refactor load-and-extend to facilitate this.
>>Update comments.
>>Handle long double in SSE when computing FP_REG_KILL.

llvm-svn: 40906
 2007-08-07 20:29:26 +00:00
Dale Johannesen
2c35d56edd Long double patch 7 of N, unless I lost count:). 
Last x87 bits for full functionality (not
thoroughly tested, and long doubles do not work
in SSE modes at all - use -mcpu=i486 for now)

llvm-svn: 40886
 2007-08-07 01:17:37 +00:00
Dale Johannesen
92be0d49fb Replace 4-line function with 10-line version per review comment. 
llvm-svn: 40881
 2007-08-06 22:10:35 +00:00
Dale Johannesen
4df87d9305 Move lengthy conditional down 1 level per review comment. 
llvm-svn: 40878
 2007-08-06 21:48:35 +00:00
Dale Johannesen
3ea9879011 Get X86 long double calling convention to work 
(on Darwin, anyway).  Fix some table omissions for
LD arithmetic.

llvm-svn: 40877
 2007-08-06 21:31:06 +00:00
Dale Johannesen
e3f1d06ca0 Make 80-bit store maintain simulated FP stack correctly. 
llvm-svn: 40868
 2007-08-06 19:50:32 +00:00
Dale Johannesen
a85f11d870 Long double patch 4 of N: initial x87 implementation. 
Lots of problems yet but some simple things work.

llvm-svn: 40847
 2007-08-05 18:49:15 +00:00
Chandler Carruth
00e56b0e81 This is the patch to provide clean intrinsic function overloading support in LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. 
This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported.

llvm-svn: 40807
 2007-08-04 01:51:18 +00:00
Dale Johannesen
c8462173c5 Make x86 long double alignment 32 for everything but 
Darwin (which makes size within a struct==96)

llvm-svn: 40796
 2007-08-03 22:46:15 +00:00
Dale Johannesen
4b91728849 long double patch 2 of N. Handle it in TargetData. 
(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)

llvm-svn: 40792
 2007-08-03 20:20:50 +00:00
Chris Lattner
a9026e5f12 add an observation 
llvm-svn: 40772
 2007-08-03 00:17:42 +00:00
Dan Gohman
352de5aeb9 More explicit keywords. 
llvm-svn: 40757
 2007-08-02 21:21:54 +00:00
Dan Gohman
1afde4166e Fix the alignment requirements of several unpck and shuf instructions. 
Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.

llvm-svn: 40756
 2007-08-02 21:17:01 +00:00
Dan Gohman
7d1e35e6d1 Fix pastos in vector arithmetic intrinsics. 
llvm-svn: 40754
 2007-08-02 21:06:40 +00:00
Dan Gohman
a599a813d5 Mark the SSE and MMX load instructions that 
X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle
with the isReMaterializable flag so that it is given a chance to handle
them. Without hoisting constant-pool loads from loops this isn't very
visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from
making a copy of the constant pool on the stack.

llvm-svn: 40736
 2007-08-02 14:27:55 +00:00
Evan Cheng
3163814591 Switch some multiplication instructions over to the new scheme for testing. 
llvm-svn: 40723
 2007-08-02 05:48:35 +00:00
Evan Cheng
019ecf3b91 Can't handle offset and scale if rip-relative addressing is to be used. 
llvm-svn: 40703
 2007-08-01 23:46:47 +00:00
Evan Cheng
69bbf3ed2a Mac OS X X86-64 low 4G address not available. 
llvm-svn: 40702
 2007-08-01 23:46:10 +00:00
Evan Cheng
0fa6cdbff5 Mac OS X X86-64 low 4G address not available. 
llvm-svn: 40701
 2007-08-01 23:45:51 +00:00
Evan Cheng
defb3b8389 Missing Requires. 
llvm-svn: 40691
 2007-08-01 21:42:24 +00:00
Evan Cheng
fb587a3851 Be more precise. 
llvm-svn: 40689
 2007-08-01 20:22:37 +00:00
Dan Gohman
8e7234519e Change a .size directive to use a tab instead of a space, for consistency. 
llvm-svn: 40672
 2007-08-01 14:42:30 +00:00
Dan Gohman
e3464e6bec Change the x86 assembly output to use tab characters to separate the 
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.

llvm-svn: 40648
 2007-07-31 20:11:57 +00:00
Evan Cheng
3493ec0ce1 Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) 
llvm-svn: 40628
 2007-07-31 08:04:03 +00:00
Evan Cheng
e90ad40aa1 This isn't safe when there are uses of load's chain result. 
llvm-svn: 40617
 2007-07-31 06:21:44 +00:00
Dan Gohman
32ff2ca8a0 Use tabs more consistently in assembler pseudo-ops. 
llvm-svn: 40594
 2007-07-30 15:08:02 +00:00
Christopher Lamb
919ce03da6 Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource. 
llvm-svn: 40578
 2007-07-29 01:24:57 +00:00
Christopher Lamb
4120412f3e Add register info needed to use subreg sets on X86. 
llvm-svn: 40572
 2007-07-28 19:03:30 +00:00
Duncan Sands
35a77d857b Trampoline codegen support for X86-32. 
llvm-svn: 40566
 2007-07-27 20:02:49 +00:00
Dan Gohman
0252aa07ee Re-apply 40504, but with a fix for the segfault it caused in oggenc: 
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.

llvm-svn: 40555
 2007-07-27 17:16:43 +00:00
Evan Cheng
cb8f08ebca Reverting 40504 for now. It's breaking oggenc. 
llvm-svn: 40547
 2007-07-27 01:37:47 +00:00
Evan Cheng
ffa8cbd22b Make sure epilogue esp adjustment is placed before any terminator and pop instructions. 
llvm-svn: 40538
 2007-07-26 17:45:41 +00:00
Evan Cheng
ea037bffd2 Don't pollute the meaning of isUnpredicatedTerminator. 
llvm-svn: 40537
 2007-07-26 17:32:14 +00:00
Evan Cheng
9802b13b38 Minor bug. 
llvm-svn: 40535
 2007-07-26 17:02:45 +00:00
Dan Gohman
d3a062f01b In the .loc directive, print the fields as "debug" fields, so they 
don't get decorated as if for immediate fields for instructions.

llvm-svn: 40529
 2007-07-26 15:24:15 +00:00
Dan Gohman
1bfc3f0d09 Fix a whitespace difference between CMPSSrr and CMPSDrr. 
llvm-svn: 40528
 2007-07-26 15:11:50 +00:00
Evan Cheng
413d222576 Same goes for constantpool, etc. 
llvm-svn: 40517
 2007-07-26 07:35:15 +00:00
Dan Gohman
513dcba4f8 Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the 
x86 target, replacing them with the new alignment attributes on memory
references.

llvm-svn: 40504
 2007-07-26 00:31:09 +00:00
Evan Cheng
9588231d34 Mac OS X x86-64 lower 4G address is not available. 
llvm-svn: 40502
 2007-07-25 23:41:36 +00:00
Evan Cheng
75b396c3c9 Mac OS X should use 0x90 to fill in gaps to satisfy function alignment requirements. 
llvm-svn: 40501
 2007-07-25 23:36:05 +00:00
Evan Cheng
f34a0509c2 Functions with LinkOnce and weak linkage still need to be aligned. Doh. 
llvm-svn: 40499
 2007-07-25 22:28:16 +00:00
Dan Gohman
0fc4e0cf47 Don't ignore the return value of AsmPrinter::doInitialization and 
AsmPrinter::doFinalization.

llvm-svn: 40487
 2007-07-25 19:33:14 +00:00
Anton Korobeynikov
e0344393bb Minor cleanup: 
- Split EH and debug infiormation
 - Make DwarfWriter more verbose in some cases

llvm-svn: 40481
 2007-07-25 00:06:28 +00:00
Dan Gohman
1444c5840b Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask. 
llvm-svn: 40480
 2007-07-24 23:00:27 +00:00
Dan Gohman
a2e07a38bc Use movaps to load a v4f32 build_vector of all-constant values into a 
register instead of loading each element individually.

llvm-svn: 40478
 2007-07-24 22:55:08 +00:00
Anton Korobeynikov
e8170a07f8 Heal EH handling stuff by emitting correct offsets to callee-saved registers. 
Pretty hackish, but code itself is dirty mess, so we won't make anything worse. :)

llvm-svn: 40472
 2007-07-24 21:07:39 +00:00
Dan Gohman
54b8032d64 Fix some uses of dyn_cast to be uses of cast. 
llvm-svn: 40443
 2007-07-23 20:24:29 +00:00
Dan Gohman
e2dcfd1516 Delete the svn:executable property on these files, which aren't executable. 
llvm-svn: 40441
 2007-07-23 19:26:08 +00:00
Bill Wendling
97342a9b0c Add missing SSE builtins: 
__builtin_ia32_cvtss2si64
    __builtin_ia32_cvttss2si64
    __builtin_ia32_cvtsi642ss
    __builtin_ia32_cvtsd2si64
    __builtin_ia32_cvttsd2si64
    __builtin_ia32_cvtsi642sd

llvm-svn: 40411
 2007-07-23 03:07:27 +00:00
Evan Cheng
53cb03b583 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng
cdb4e7949f Added -print-emitted-asm to print out JIT generated asm to cerr. 
llvm-svn: 40123
 2007-07-20 21:56:13 +00:00
Evan Cheng
ac92a8149e Because we promote SSE logical ops and loads to v2i64, we often end up generate 
code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.

llvm-svn: 40076
 2007-07-20 00:27:43 +00:00
Evan Cheng
ba990bbc3f Fix custom lowering of SSE FXOR. 
llvm-svn: 40071
 2007-07-19 23:36:01 +00:00
Evan Cheng
f11cf2cad8 Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)). 
llvm-svn: 40070
 2007-07-19 23:34:10 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Evan Cheng
30e121adf6 Only adjust esp around calls in presence of alloca. 
llvm-svn: 40028
 2007-07-19 00:42:05 +00:00
Evan Cheng
6a4fb5d62b Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in. 
llvm-svn: 40018
 2007-07-18 21:26:06 +00:00
Dan Gohman
2fc9d5171e Implement initial memory alignment awareness for SSE instructions. Vector loads 
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.

llvm-svn: 40015
 2007-07-18 20:23:34 +00:00
Evan Cheng
cee32b53a4 New entry. 
llvm-svn: 39998
 2007-07-18 08:21:49 +00:00
Evan Cheng
cf0fdbc249 Fold prologue esp update when possible. 
llvm-svn: 39984
 2007-07-17 21:26:42 +00:00
Evan Cheng
26f6d71d26 Make sure not to break eh_return. 
llvm-svn: 39978
 2007-07-17 18:40:47 +00:00
Evan Cheng
70b79bfa0e Update. 
llvm-svn: 39977
 2007-07-17 18:39:45 +00:00
Evan Cheng
46a48c5c3e Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan. 
llvm-svn: 39974
 2007-07-17 18:03:34 +00:00
Evan Cheng
532b73311e Use push / pop for prologues and epilogues. 
llvm-svn: 39967
 2007-07-17 07:59:08 +00:00
Anton Korobeynikov
5635277c36 Long live the exception handling! 
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855
 2007-07-14 14:06:15 +00:00
Chris Lattner
7eea439048 another missed SSE optimization 
llvm-svn: 39772
 2007-07-12 06:31:38 +00:00
Dale Johannesen
ecef839eaa Fix fp_constant_op failure. 
llvm-svn: 38514
 2007-07-10 21:53:30 +00:00
Dale Johannesen
7325a82196 fix 80 columnn violations, increasing the world's 
pedantic satisfaction level.

llvm-svn: 38512
 2007-07-10 20:53:41 +00:00
Chris Lattner
abcdeef610 add a note 
llvm-svn: 38507
 2007-07-10 20:03:50 +00:00
Dan Gohman
928144b051 Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp, 
in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.

llvm-svn: 38478
 2007-07-10 00:05:58 +00:00
Chris Lattner
4810c53b05 The various "getModuleMatchQuality" implementations should return 
zero if they see a target triple they don't understand.

llvm-svn: 38463
 2007-07-09 17:25:29 +00:00
Evan Cheng
88acbacd35 isUnpredicatedTerminator should treat conditional branches as unpredicated terminator. 
llvm-svn: 37960
 2007-07-06 23:22:03 +00:00
Rafael Espindola
7b3de98989 Add the byval attribute 
llvm-svn: 37940
 2007-07-06 10:57:03 +00:00
Anton Korobeynikov
e8215d1780 Proper flag __alloca call 
llvm-svn: 37923
 2007-07-05 20:36:08 +00:00
Gabor Greif
5f705671e4 Here is the bulk of the sanitizing. 
Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913
 2007-07-05 17:07:56 +00:00
Dale Johannesen
9072b65b0b Refactor X87 instructions. As a side effect, all 
their names are changed.

llvm-svn: 37876
 2007-07-04 21:07:47 +00:00
Bill Wendling
2e66551f22 Support generation of GR64 to MMX code in the JIT. 
llvm-svn: 37866
 2007-07-04 01:29:22 +00:00
Bill Wendling
3600c7a835 Allow a GR64 to be moved into an MMX register via the "movd" instruction. 
Still need to have JIT generate this code.

llvm-svn: 37863
 2007-07-04 00:19:54 +00:00
Dale Johannesen
0db4ba9f8a Some spacing fixes. Cosmetic. 
llvm-svn: 37853
 2007-07-03 17:07:33 +00:00
Dale Johannesen
7af19491d3 Fix for PR 1505 (and 1489). Rewrite X87 register 
model to include f32 variants.  Some factoring
improvments forthcoming.

llvm-svn: 37847
 2007-07-03 00:53:03 +00:00
Dan Gohman
eb46e6e629 Vector results may be returned in XMM0 and XMM1, not just XMM0. With 
the recent lowering changes, this allows types like <4 x double> to
be returned, using two vector registers.

llvm-svn: 37844
 2007-07-02 16:21:53 +00:00
John Criswell
57e5ed4b5a Convert .cvsignore files 
llvm-svn: 37801
 2007-06-29 16:35:07 +00:00
Evan Cheng
992f296a71 No vector fneg. 
llvm-svn: 37786
 2007-06-29 00:18:15 +00:00
Evan Cheng
e233ec5e46 Type of vector extract / insert index operand should be iPTR. 
llvm-svn: 37784
 2007-06-29 00:01:20 +00:00
Dan Gohman
ce1bca0bf9 Remove a redundant newline in the asm output for ELF .rodata sections. 
llvm-svn: 37756
 2007-06-27 15:09:47 +00:00
Dan Gohman
9cbc3fb1ab Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
 2007-06-26 00:48:07 +00:00
Dan Gohman
354f02e03d Generalize MVT::ValueType and associated functions to be able to represent 
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.

llvm-svn: 37719
 2007-06-25 16:23:39 +00:00
Dan Gohman
dc8a1730f7 Make minor adjustments to whitespace and comments to reduce differences 
between SSE1 instructions and their respective SSE2 analogues.

llvm-svn: 37718
 2007-06-25 15:44:19 +00:00
Dan Gohman
f40db01c32 Fix loadv2i32 to be loadv4i32, though it isn't actually used anywhere yet. 
llvm-svn: 37717
 2007-06-25 15:19:03 +00:00
Dan Gohman
d3b3703430 Say AT&T instead of Intel in the comments for AT&T support. 
llvm-svn: 37716
 2007-06-25 15:11:25 +00:00
Dan Gohman
a62327ea40 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from 
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
 2007-06-22 14:59:07 +00:00
Dale Johannesen
e1c767df50 Quote complex names for Darwin X86 and ARM. 
llvm-svn: 37700
 2007-06-22 00:54:56 +00:00
Dan Gohman
b60d8a92c9 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
 2007-06-19 01:48:05 +00:00
Chris Lattner
e13fac05d7 If a function is vararg, never pass inreg arguments in registers. Thanks to 
Anton for half of this patch.

llvm-svn: 37641
 2007-06-19 00:13:10 +00:00
Evan Cheng
80f0d5ae45 Look for VECTOR_SHUFFLE that's identity operation on either LHS or RHS. This can happen before DAGCombiner catches it. 
llvm-svn: 37636
 2007-06-19 00:02:56 +00:00
Dan Gohman
bff1054303 Define the pushq instruction for x86-64. 
llvm-svn: 37625
 2007-06-18 14:12:56 +00:00
Bill Wendling
94f3474832 Revert patch. It regresses: 
define double @test2(i64 %A) {
   %B = bitcast i64 %A to double
   ret double %B
}

$ llvm-as < t.ll | llc -march=x86-64

before:

         .align  4
         .globl  _test2
_test2:
         movd %rdi, %xmm0
         ret

after:

_test2:
         subq $8, %rsp
         movq %rdi, (%rsp)
         movsd (%rsp), %xmm0
         addq $8, %rsp
         ret

llvm-svn: 37617
 2007-06-16 23:57:15 +00:00
Bill Wendling
a1f8f0aa97 Fix a failure to bit_convert from integer GPR to MMX register. 
llvm-svn: 37611
 2007-06-16 06:17:31 +00:00
Dan Gohman
2fd7d26df8 Rename MVT::getVectorBaseType to MVT::getVectorElementType. 
llvm-svn: 37579
 2007-06-14 22:58:02 +00:00
Dale Johannesen
62f49dd524 Do not treat FP_REG_KILL as terminator in branch analysis (X86). 
llvm-svn: 37578
 2007-06-14 22:03:45 +00:00
Dan Gohman
35f2b4d716 Add a target hook to allow loads from constant pools to be rematerialized, and an 
implementation for x86.

llvm-svn: 37576
 2007-06-14 20:50:44 +00:00
Dan Gohman
74c92798d8 Eliminate some redundant newlines in asm output. 
llvm-svn: 37574
 2007-06-14 15:00:27 +00:00
Dale Johannesen
7e3253f115 Handle blocks with 2 unconditional branches in AnalyzeBranch. 
llvm-svn: 37571
 2007-06-13 17:59:52 +00:00
Chris Lattner
5f85da00bb fix x86-64 mmx calling convention for real, which passes in integer gprs. 
llvm-svn: 37534
 2007-06-09 05:08:10 +00:00
Chris Lattner
e965432273 fix mmx handling bug 
llvm-svn: 37533
 2007-06-09 05:01:50 +00:00
Evan Cheng
1a6c0341fd Add a utility routine to check for unpredicated terminator instruction. 
llvm-svn: 37528
 2007-06-08 21:59:56 +00:00
Evan Cheng
fdfe615197 Misuse of hasExternalLinkage(), should be checking isDeclaration(). 
llvm-svn: 37419
 2007-06-04 18:54:57 +00:00
Dan Gohman
1b1932dda5 Add explicit qualification for namespace MVT members. 
llvm-svn: 37320
 2007-05-24 14:33:05 +00:00
Bill Wendling
26eb9fb1e0 We only need to specify the most-implied feature for an architecture. 
llvm-svn: 37275
 2007-05-22 05:15:37 +00:00
Evan Cheng
3f386274c0 BlockHasNoFallThrough() now returns true if block ends with a return instruction. 
llvm-svn: 37266
 2007-05-21 18:44:17 +00:00
Chris Lattner
a7834d79a0 add a note 
llvm-svn: 37239
 2007-05-18 20:18:14 +00:00
Dan Gohman
ec87afe526 Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE. 
llvm-svn: 37234
 2007-05-18 18:44:07 +00:00
Evan Cheng
90b0ff05f6 RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted. 
llvm-svn: 37193
 2007-05-18 00:18:17 +00:00
Evan Cheng
1b4af5f975 Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an optimization to fold VECTOR_SHUFFLE to a zero vector. 
llvm-svn: 37173
 2007-05-17 18:45:50 +00:00
Evan Cheng
9c4e69e6e5 Added missing patterns for UNPCKH* and PUNPCKH*. 
llvm-svn: 37172
 2007-05-17 18:44:37 +00:00
Chris Lattner
9a53871650 This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn't 
cause other regressions.

llvm-svn: 37160
 2007-05-17 17:13:13 +00:00